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2014-05-15baytrail: nvm: use proper types for checking eraseAaron Durbin
The current byte value was being converted to an int when checking against literal 0xff. As the type of the current pointer was char (signed) it was sign extending the value leading to 0xffffffff != 0xff. Fix this by using an unsigned type and using a constant type for expected erase value. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmwareupdate. Noted that MRC cache doesn't think the erased region isn't erased. Change-Id: If95425fe26da050acb25f52bea060e288ad3633c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182154 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5044 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: mrc_cache: check region erased before erasingAaron Durbin
On a firmware update the MRC cache is destroyed. On the subsequent boot the MRC region was attempted to be erased even if it was already erased. This led to spi part taking longer than it should have for an unnecessary erase operation. Therefore, check that the region is erased before issuing the erease command. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmeareupdate. Noted no error messages in this path. Change-Id: I6fadeb6bc5fc178abb0a7e3f0898855e481add2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182153 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5043 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15rambi: disable SERIRQ native functionalityAaron Durbin
Nothing can actually use this as the EC cannot speak using baytrail's SERIRQ protocol. Also, the voltage bridge is going away so nothing will be hooked up to it. Therefore disable this it. BUG=chrome-os-partner:24693 BRANCH=rambi TEST=Built and booted. Change-Id: I406bb9c227578ec0a75eaf67143b3b27cb7880ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182082 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5042 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-14southbridge/amd/cimx/sb800: Unused func smbus_delay()Edward O'Callaghan
Change-Id: Icc12aafc1462c08bca77a1798d4fae86b8250708 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5748 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-05-14mainboard/lenovo/t520: too many arguments to pc_keyboard_initEdward O'Callaghan
Fix build regression introduced in: a823f9b mainboard/lenovo: Add Lenovo Thinkpad T520 support Change-Id: I60d92f8cceda6427f43e6be9d78c2af82af4b061 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5738 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-14intel: Drop obsolete comments on MTRR usageKyösti Mälkki
Problem with UMA region allocation was fixed when MTRRs changed to use memrange implementation. Change-Id: I420dac30de2836a91596d81f88bb45b46f248532 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5719 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-05-13mainboard/lenovo: Add Lenovo Thinkpad T520 supportZaolin
Short list of known issues for this patchset: * Suspend/Resume - does not work * Combi pci card for SD/MMC card reader with IEEE1394 - not found * Shutdown - sometimes does not work as expected * At least mysterious harddrive i/o Change-Id: Iaba8d1f5e471cfeca20d82f4e1b416641e1f2ae9 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/5672 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-13cpu/intel: Add CPU socket rPGA988BZaolin
Used by the Lenovo ThinkPad T520 Change-Id: I1009616cc4c18ebd0e3be7ceb50398617b49e3a3 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/5671 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins)
2014-05-13baytrail: add C0 microcode updateAaron Durbin
Include C0 microcode drop. BUG=None BRANCH=rambi,squawks TEST=Built. Booted B3 part. Change-Id: If454658235cd5a7b8640de0b3fa12dccddb0e9f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182080 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5041 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: reboot with EC in S0 with no MRC cache and EC in RWAaron Durbin
This improves boot time in 2 ways for a firmware upgrade: 1. Normally MRC would detect the S0 state without an MRC cache even though it's told to the S5 path. When it observes this state a cold reset occurs. The cold reset stays in S5 for at least 4 seconds which is time observed by the end user. 2. As the EC was running RW code before the reset after firmware upgrade it will still be running the older RW code. Vboot will then reboot the EC and the whole system to put the EC into RO mode so it can handle the RW update. The issues are mitigated by detecting the system is in S0 with no MRC cache and the EC isn't in RO mode. Therefore we can do the reboot without waiting the 4 secs and the EC is running RO so the 2nd reboot is not necessary. BUG=chrome-os-partner:24133 BRANCH=rambi,squawks TEST=Booted. Updated firmware while in OS. Rebooted. Noted the EC reboot before MRC execution. Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182061 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5040 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chromeec: add function to reboot on unexpected imageAaron Durbin
It's helpful to have a generic function that will tell the EC to reboot if the EC isn't running a specified image. Add that and implement google_chromeec_early_init() to utilize the new function still maintaing its semantics of if recvoery mode is enabled the EC should be running its RO image. There is a slight change in that no communication is done with the EC if not in recovery mode. BUG=chrome-os-partner:24133 BRANCH=rambi,squawks TEST=Built and boot with recovery request. Noted EC reboot. Change-Id: I22240f6a11231e39c33fd79796a52ec76b119397 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182060 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5039 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: dptf: Add disable trip point methodsDuncan Laurie
Added a method in each temp sensor to disable the aux trip points and then a wrapper function to call this method for each enabled temperature sensor. The event handler function is changed to not use a switch statement so it does not need to be serialized. This was causing issues with nested locking between the global lock and the EC PATM mutex. Some unused code in temp sensors that was added earlier is removed and instead a critical threshold is specified in _CRT. The top level DPTF device _OSC method is expanded to check for the passive policy UUID and initialize thermal devices. This is done for both enable and disable steps to ensure that the EC thermal thresholds are reset in both cases. Additionally the priority based _TRT is specified with TRTR=1. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, load esif_lf kernel drivers and start esif_uf application. Observe that temperature thresholds are set properly when running 'appstart Dptf' and that they are disabled after running 'appstop Dptf' Change-Id: Ia15824ca42164dadae2011d4e364b70905e36f85 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182024 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5037 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13rambi: dptf: Set critical thresholdsDuncan Laurie
Set critical temperature thresdholds to 70C. This will cause DPTF framework to shut down the system so it may need to be higher or lower but will need some testing. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, start DPTF framework and observe it using specified critical thresholds. Change-Id: Ibbf6d814295eb5ff006cb879676b7613f5eb56a3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182025 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5038 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: Fix temperature calcualtion in PATx methodsDuncan Laurie
The PATx methods will be passed a temperature in deci-kelvin, so it needs to be converted back to kelvin before being sent to the EC. The PAT disable method is changed to take the temperature ID as an argument so individual sensors can be disabled. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, load esif_lf kernel drivers and esif_uf userspace application. Start and stop DPTF and see that temperature thresholds are set to sane values. Change-Id: Ieeff5a5d2d833042923c059caf3e5abaf392da95 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182023 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5036 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: call DPTF thermal threshold event handlerAaron Durbin
When an EC thermal event occurs call the DPTF thermal threshold event handler to handle notifications. Change-Id: Ica928790bb478fccf8a46afef4eb7800589518b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5726 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: Updates for DPTF ACPI frameworkDuncan Laurie
- Remove some unused functions from CPU participant that were confusing the userland component since the CPU does not have an ACPI managed sensor. - Guard the charger participant with an ifdef so it can be left out if not supported. - Use the EC methods for setting auxiliary trip points and for handling the event when those trip points are crossed. - Add _NTT _DTI _SCP methods for thermal sensors. I'm not clear if these are required or not but they seem to be expected by the other DPTF framework components. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi and load ESIF framework Change-Id: I3c9d92d5c52e5a7ec890a377e65ebf118cdd7087 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5028 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: Update header and add functions to support DPTFDuncan Laurie
The EC now supports two auxiliary programmable trip points for thermal monitoring. These are expected to be used by DPTF and need to be exported. In order to support these the header was updated from the latest chrome ec source. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi Change-Id: I257d910daac4e36280c0cecf4129381a32ffcb9a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181661 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5027 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13rambi: Update the DPTF configurationDuncan Laurie
- Add passive thresholds for thermal participants - Disable the charger participant and remove from _TRT BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi and start ESIF framework Change-Id: Ie5917413aceadee6e39594257aaafb0bcb399d09 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181663 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5029 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: don't SMI on tco timer firingAaron Durbin
The SMI on TCO timer timeout policy was copied from other chipsets. However, it's not very advantageous to have the TCO timer timeout trigger an SMI unless the firmware was the one responsible for setting up the timer. BUG=chromium:321832 BRANCH=rambi,squawks TEST=Manually enabled TCO timer. TCO fires and logged in eventlog. Change-Id: I420b14d6aa778335a925784a64160fa885cba20f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181985 Reviewed-on: http://review.coreboot.org/5035 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: clear the pmc wake status registersAaron Durbin
The PMC in baytrail maintains an additional set wake status in memory-mapped registers. If these bits aren't cleared the device won't be able to go to S5 or S3 without being immediately woken up. Therefore clear these registers. BUG=chrome-os-partner:24913 BRANCH=rambi,squawks TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work correctly. Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181984 Reviewed-on: http://review.coreboot.org/5034 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: log reset, power, and wake events in elogAaron Durbin
When CONFIG_ELOG is selected the reset, power, and wake events are logged in the eventlog. BUG=chrome-os-partner:24907 BRANCH=rambi,squawks TEST=Various resets and wake sources. Interrogated eventlog to ensure results are expected. Change-Id: Ia68548562917be6c2a0d8d405a5b519102b8c563 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181983 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5033 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: snapshot power state in romstageAaron Durbin
The memory reference code doesn't maintain some of the registers which contain valuable information in order to log correct reset and wake events in the eventlog. Therefore snapshot the registers which matter in this area so that they can be consumed by ramstage. BUG=chrome-os-partner:24907 BRANCH=rambi,squawks TEST=Did various resets/wakes with logging patch which consumes this structure. Eventlog can pick up reset events and power failures. Change-Id: Id8d2d782dd4e1133113f5308c4ccfe79bc6d3e03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181982 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5032 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: add cpuid for C0Aaron Durbin
The C0 part uses a new cpuid. BUG=None BRANCH=squawks,rambi TEST=None. Change-Id: Iddf1bc4d6f7bbec3ca92bff8edf613e00a4b4286 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181980 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5031 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13rambi: Move KBD_IRQ pin for Rambi 2.0 boardShawn Nematbakhsh
KBD_IRQ# is moved to GPIO SC101, with SC50 going back to its original SERIRQ function. Note that this change breaks Rambi 1.5 keyboard functionality. BUG=chrome-os-partner:24424 TEST=Manual on Rambi 2.0. Verify KB functions in OS with SC50 / SERIRQ KB interrupt toggling removed from EC code. BRANCH=Rambi, Glimmer, Clapper Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I3fa40441741ea9d52a6e2ff15925570510b5b82b Reviewed-on: https://chromium-review.googlesource.com/181757 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5030 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13src/*: Remove the last remnants of struct keyboardEdward O'Callaghan
Change-Id: I7d0e8d2119a470428cfc01c0738b8988ab75ba2d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5624 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13superio/*: Remove redundant chip.h headerEdward O'Callaghan
Change-Id: If7141112ea67071ee05c52f455c3b2496aa7e17e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5622 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13superio/*: Deal with some chip.h special casesEdward O'Callaghan
While backing out the empty pc80 keyboard struct we encountered some special cases where chip.h is used for other purposes. Deal with these cases. Change-Id: Ib11a46cfd14d050d5daa213623b9d8a401c06410 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5621 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13src/drivers/pc80: Remove empty struct keyboardEdward O'Callaghan
This is a empty struct that has propagated through the superio's & ec's but really does nothing. Time to get rid of it before it adds yet more cruft. However, since this touches many superio's at once we do this in stages by first changing the function type to be a pure procedure. Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5617 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-13southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridgeEdward O'Callaghan
We should configure i8254/i8259 down in to the southbridge rather than romstage of every AGESA/CIMx board much like Intel boards do. Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5669 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-12Rambi: Enable 32k SUSCLK signalKyösti Mälkki
The SoC needs to provide a 32k clock signal SUSCLK for some modems to work properly, so this enables the signal. BUG=chrome-os-partner:24425 TEST=Manual, check SUSCLK pin with a scope. Change-Id: Ibc0d5bb38a2c3e16f381dfc256097fdced67fd1c Reviewed-on: https://chromium-review.googlesource.com/180101 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5722 Reviewed-by: Aaron Durbin <adurbin@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12rambi: Make eMMC CLK pull-down and change pull strengths to 20KShawn Nematbakhsh
eMMC CLK was incorrectly configured as PULL_UP, but should have been PULL_DOWN. 2K pulls somehow masked this problem. BUG=chrome-os-partner:24353 TEST=Verify eMMC is bootable on Rambi on boards that previously failed with an all-20K, all-PU eMMC pin configuration. BRANCH=None Change-Id: I0cbb6ebbb6818f83402b99330728266b09a0f5d6 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181034 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5026 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12baytrail: align with intel recommendationsAaron Durbin
The BISOC.EXIT_SELF_REFRESH_LATENCY field should not be updated from the default. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I6e701a520513372318258648e998dd8c7ab29ea4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180730 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5025 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12rambi: specify reference code index in vboot areaAaron Durbin
Rambi's reference code will live at slot 3 in the verified firmware section. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. Verified correct area where reference code was loaded from. Change-Id: I8bee46600429ac8f732fe334852f69aff1324150 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180027 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5024 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12baytrail: add way to load reference code from vboot areaAaron Durbin
When employing vboot firmware verification the reference code loading should load from the verified firmware section. Add this ability. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted rambi. Noted firmware being loaded from rw verified area. Also noted S3 resume loading from cached area. Change-Id: I114de844f218b7573cf90107e174bf0962fdaa50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180026 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5023 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-12baytrail: Expose IOSF as ACPI objectDuncan Laurie
The kernel iosf driver uses HID INT33BD to probe and be provided the 12 bytes in PCI for access. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, load iosf_mbi driver and verify that it gets address 0xe00000d0 Change-Id: I865eafe664f00f21d1ebb967c291083830d895b9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180098 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5021 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12rambi: Disable HSUART2 and SPI interfacesDuncan Laurie
Not used currently on rambi board. Disable in case it saves power. BUG=chrome-os-partner:23862 BRANCH=none TEST=build and boot on rambi Change-Id: Idb870c2cfa88cb6c3f1ada3caf0db566e33ec1eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180084 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5020 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12rambi: Enable SCC devices in ACPI modeDuncan Laurie
With the ACPI GNVS exported and depthcharge changed to initialize eMMC in ACPI mode we can now put the SCC devices into ACPI mode. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot on rambi, test eMMC and SD card Change-Id: I39716198f8227c0c3293ac23eb09660792e2c51b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179901 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5018 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12baytrail: Put devices in ACPI mode after setupDuncan Laurie
Make sure reg_script is executed before the device is put into ACPI mode. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi from eMMC in ACPI mode Change-Id: I4090babbfc7fb0f3be4da869386e998d87a513ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5017 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12baytrail: Add header include wrapper and offset defineDuncan Laurie
Since this file will get added to payloads it is useful if it exports what offset in NVS it lives. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi with emmc in ACPI mode Change-Id: I52860980c91dfe2525628e142b34ca192e69b258 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179848 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5014 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12superio/ite/it8718f: Remove hard coding from romstageEdward O'Callaghan
Make use of the ITE common Super I/O framework and there-by removing any hard coding of Super I/O base address. Change-Id: I14af89d2727d7c6bac0f9840043c430726297429 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5717 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-11superio/ite/*: Factor out generic romstage componentEdward O'Callaghan
Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5585 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-11superio/ite/it8728f: RAMstage PNP configuration componentEdward O'Callaghan
Provide devicetree.cb RAMstage configuration of this superio component. Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5668 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-11SeaBIOS: Fix cpp usePatrick Georgi
No need to pass CPP down to SeaBIOS, it's not architecture specific and they define their own variable. Change-Id: I811aaf3929fa11cc01b7f168ccd310008e21e60c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5715 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10Arch-level Kconfig menu cleanupFurquan Shaikh
Remove arch-level Kconfig menu option as it shows all available architectures in make menuconfig. Instead pull the bootblock options for choice and update image to top-level Kconfig since it is already present for both x86 and arm. Change-Id: Iab9c4539f05cd54a7f751565fefcaf7b6f0edc86 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5673 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
Lines with 'select SERIAL_CPU_INIT' where redundant with the default being yes. Since there is no 'unselect SERIAL_CPU_INIT' possibility, invert the default and rename option. This squelches Kconfig warnings about unmet dependencies. Change-Id: Iae546c56006278489ebae10f2daa627af48abe94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5700 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-10mainboard/jetway/nf81-t56n-lf: Toggle WDT and CIR in devicetree.cbEdward O'Callaghan
Turn on WDT support in the devicetree. Turn off CIR support. Dispense with old commentary. Change-Id: Icf0c0e12a0ed7ce6c3b6176653e076ffc2ba937e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5698 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10superio/fintek/f71869ad: Fix incorrect LDN'sEdward O'Callaghan
Turns out there are a few minor differences of the LDN's in the AD rev. of this Fintek chip. 0x07 is in fact the WDT so renaming and remove the now incorrect io mask. Add missing CIR LDN functionality and touch up src inline doc. Change-Id: I440aebad71d62d199d3283dd061933e76b21dda5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5696 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: cache reference code for S3 resumeAaron Durbin
In order to use the same reference code on S3 resume that was booted the program needs to be cached. Piggy back on the ramstage cache to save the loaded reference code program. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Noted locations of reference code caching and load addresses in console. Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179777 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5013 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: allow ramstage_cache_location() usage in ramstageAaron Durbin
To prepare for caching reference code for S3 resume the ramstage cache needs to be accesible in ramstage as well. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179776 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5012 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10ramstage_cache: allow ramstage usage add valid helperAaron Durbin
Allow ramstage cache to be used from ramstage proper. Also add a helper function for checking validity of ramstage cache structure. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: If1f2ad1bcf64504b42e315be243a12432b50e3d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179775 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5011 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 12:12:57 +0000