summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2015-04-10broadwell: Only do pre-graphics delay when running option romDuncan Laurie
This changes the broadwell graphics init path to only do the delay before initializing graphics when running chromeos if we are also going to execute the option rom. BUG=chrome-os-partner:33671 BRANCH=samus TEST=build and boot on samus Change-Id: Idb7d39b22f7f6dc3be6dfbd2fa3cc2e33d78a397 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f7ed93504a74760f16acb8fb3c6c57ac514b7260 Original-Change-Id: I350f85738efe3d17152de4f025adbfd52ae15b95 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228882 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10PCI - Add interrupt disable bit definitionLee Leahy
BRANCH=none BUG=None TEST=Build Braswell/Strago Change-Id: I11a4c02af3b40edf2252b9e20298941b99f31d21 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 1629d7454a3d4adb8930d14849c41c9a711f4c9a Original-Change-Id: Ie907637f7c823de681ef2e315e803dffc6ad33d3 Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241081 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9487 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Add ACPI binding for rt5677 codec SPIBen Zhang
We'll need to find a real ACPI device ID for the rt5677 SPI driver. "RT5677AA" is temporary. BUG=chrome-os-partner:33495 BRANCH=samus TEST=load firmware via SPI; hotword detection works Change-Id: I6dc55c4641c27a38570debe841a6afeb048eb868 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f0d7013b62c78deb82db1a431f079c79eded5270 Original-Change-Id: Ifb4a1b12776669e21c0b7c4679246717d72981ad Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/235902 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9486 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Fix PCIe ports programming sequences to enable HSIOPCWenkai Du
HSIOPC/GPIO71 is used to control power to VCCHSIO, VCCUSB3PLL and VCCSATA3PLL in S0. PCH will drive HSIOPC low when all the high speed I/O controllers (xHCI, SATA, GbE and PCIe) are idle. This patch added a few additional PCIe programming steps as required in 535127 BIOS Writer Guide Rev 2.3.0 to enable this power saving mode. BUG=none BRANCH=none TEST=tested on Paine watching GPIO71 toggling as expected Change-Id: Ica6954c125ec3129e2659168f1f23dc861ce5708 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e38f9ef57c480ca5ee420020eb80a1adb3c381d3 Original-Change-Id: I88ef125c681c8631e8b887f7ccf017b90b8c0f10 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238580 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9482 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Add RT5677 ACPI/DT bindings with _DSDDuncan Laurie
To support the ACPI device specific properties that conform to the existing devicetree bindings for this codec (in upstream kernels) add a _DSD object to the existing codec device. BUG=chrome-os-partner:29649 BRANCH=samus TEST=build and boot on samus Change-Id: Ice808ba7bf2f0378ac5a38afd27dbf6c8cac0da5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b3fc2d7e5a5878b1fff7627f803b883b38fea28d Original-Change-Id: I344636171a3086a72087314503bfc99de5945b1f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238857 Original-Reviewed-by: Ben Zhang <benzh@chromium.org> Reviewed-on: http://review.coreboot.org/9483 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Update SATA Gen3 TX adjustment registersDuncan Laurie
The registers that were used here are for CPT/PPT and not for HSW/BDW chips. Update this to update just the Gen3 TX Output Voltage Downscale Amplitude Adjustment field in the SATA ECR T88. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I94b702dc4a3c98678ba048ff9cfa4a85cc5b1eed Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4c5816cc647b84266751e8a591eb85d7735fee12 Original-Change-Id: I98ec9678938a6675828721d5b57683077f555d21 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238800 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9484 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Add a few bits to finalize stepDuncan Laurie
Added a few bits to set in finalize step from scrubbing BWG and reference code. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus Change-Id: I7b0c4dd3f14c06175c973561760ad1bdafd46fbb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3802aef908849fe6ea2bb0034d884064154ae9da Original-Change-Id: Ia62055b32be039eef84a0f60f0ba307eb5dce6a1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239958 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9485 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10baytrail: fix the coding error on PCIe L1 exit latencyKevin L Lee
The original code uses L1EXIT_MASK to shift the bit for PCIe L1 exit latency, the code should use L1EXIT_SHIFT for bit shifting. BUG=chrome-os-partner:34037 BRANCH=None TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15] set to 010b. Correspond WIFI device performance got improvement. Signed-off-by: Kevin L Lee <kevin.l.lee@intel.com> Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92 Original-Reviewed-on: https://chromium-review.googlesource.com/234673 Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9480 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10TPM: Reduce buffer size to fix stack overflowJulius Werner
The TPM driver by default allocates a 4K transfer buffer on the stack, which leads to lots of fun on boards with 2K or 3K stack sizes. On RK3288 this ends up writing over random memory sections which dependent on the memlayout of the day might contain timestamp data (no big deal) or page tables (-> bad time). This patch fixes the problem by reducing the buffer size to slightly above 1K, which still seems to work as far as I can tell. There was already some really odd code that #undef'ed this value and redefined it with the lower number in one .c file (unfortunately not the one with the buffer declaration), with no explanation whatsoever... I'm removing that and just assume the smaller value will be fine for everything. BRANCH=veyron BUG=None TEST=Booted Pinky and Falco. Change-Id: I440a5662b41cbd8b7becab3113262e1140b7f763 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3d3288041b6629b7623b9d58816e782e72836b81 Original-Change-Id: Idf80f44cbfb9617c56b64a5c88ebedf7fcb4ec71 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236976 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 msKevin Hsieh
Using REG_PCI_POLL32 to check if the LINK is active with 50ms timeout. BRANCH=none BUG=chromium:431169 TEST=Test on Enguarde, compile ok and boot OS Change-Id: If98ab4e31d17ec4e62d68b93edcec6d9aee87367 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: cf692ae9aebb43ab46cb07d36b62b300b16be1dc Original-Change-Id: I490e6ffa40979628edf52a7444808b6d25a6e83d Original-Signed-off-by: Kevin Hsieh <kevin.hsieh@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231777 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9478 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Remove error message for unknown resource typeDuncan Laurie
This is being triggered because the base address is added, but there is nothing that needs done with it in set_resources step and the ERROR message is tripping suspend resume test scripts. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=boot on samus and check for ERROR strings, successfully run suspend_stress_test without failures Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/231603 (cherry picked from commit bb789492965d92e309a913dc7b9f09f7036c5480) Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I565c8af954f1c5a406d2c65f01c274e9259e43ec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9062734d884f814dc880589ee615b4d7e1fdc61a Original-Change-Id: I2b5f44795f1ee445d509b29bd56f498aea7b7fe3 Original-Reviewed-on: https://chromium-review.googlesource.com/231604 Original-Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9476 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10Broadwell: Set boot_mode of pei_data before running reference codeKenji Chen
Some actions are needed and some are not on the way resume from S3. BRANCH=master BUG=chrome-os-partner:33025,chrome-os-partner:33796 TEST=Built the image and confimed the boot_mode is correctly configured. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: If400df94f970a55f3921a5a2df24038d28beb489 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 40e719618ec101235cdb1755933e719abd873239 Original-Change-Id: Ia042ea8c63c2306e9d6a80d8efa66c4fc0722d85 Original-Reviewed-on: https://chromium-review.googlesource.com/229615 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9475 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Move board version to a separate fileDuncan Laurie
This combines the board version reading and parsing to a separate file that is compiled in both romstage (for early serial output) and ramstage (for smbios tables). It also adds a new board version that is wrapped back to number zero as we are running out of available IDs. BUG=chrome-os-partner:32895 BRANCH=samus TEST=build and boot on samus EVT1 and EVT2 and check for proper board versions reported in console and smbios. Change-Id: I8c8f17708ced7167277a98529ff4597589f53095 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3ab8bba1021a8dd41dd2210ba73efd2231eb596c Original-Change-Id: I2aa03e7486a9581f94dc4e12f6f29eb0c5b3bdbb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229041 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Add ramstage driver and interrupt configurationDuncan Laurie
This adds a ramstage driver for the TPM and allows the interrupt to be configured in devicetree.cb. The interrupt vector is set like other PNP devices, and the interrupt polarity is set with a register configuration variable. These values are written into locality 0 TPM_INT_VECTOR and TPM_INT_ENABLE and then all interrupts are disabled so they are not used in firmware but can be enabled by the OS. It also adds an ACPI device for the TPM which will configure the reported interrupt based on what has been written into the TPM during ramstage. The _STA method returns enabled if CONFIG_LPC_TPM is enabled, and the _CRS method will only report an interrupt if one has been set in the TPM itself. The TPM memory address is added by the driver and declared in the ACPI code. In order to access it in ACPI a Kconfig entry is added for the default TPM TIS 1.2 base address. Note that IO address 0x2e is required to be declared in ACPI for the kernel driver to probe correctly. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=manual testing on samus: 1) Add TPM device in devicetree.cb with configured interrupt and ensure that it is functional in the OS. 2) Test with active high and active low, edge triggered and level triggered setups. 3) Ensure that with no device added to devicetree.cb that the TPM is still functional in polling mode. Change-Id: Iee2a1832394dfe32f3ea3700753b8ecc443c7fbf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fc2c106caae939467fb07f3a0207adee71dda48e Original-Change-Id: Id8a5a251f193c71ab2209f85fb470120a3b6a80d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226661 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9469 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Move the LPC TPM driver to a subdirectoryDuncan Laurie
This moves the LPC TPM driver to drivers/pc80/tpm so it can be turned into a ramstage driver with a chip.h It includes no other changes yet. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=emerge-samus coreboot Change-Id: Iac83e52db96201f37a0086eae9df244f8b8d48d9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: be2db391f9da80b8b75137af0fe81dc4724bc9d1 Original-Change-Id: I60ddd1d2a3e72bcf169a0b44e0c7ebcb87f4617d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226660 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9468 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Increase I2C SDA hold timing to 300nsChiranjeevi Rapolu
I2C bus SDA hold time can be marginal with 60ns value, especially when there is level shifter on the bus. So program it to 300ns based on Fast-mode specification, which is between 0 to 900ns. Apply the same timing for Standard-mode as well. Refer to original bug on BayTrail chrome-os-partner:28092, this is to carry forward the fix to Broadwell. BRANCH=chromeos-2013.04 BUG=chrome-os-partner:33378 TEST=suspend resume test, watch for I2C errors Change-Id: I93200b141602163903f5c9f52b94013bcf3382a5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 72b82a1d5d836594e7d0f95972cc0dc91ae7ff8c Original-Change-Id: I995d6868a44f2578a6d0b18dd5e8548f3c3cd494 Original-Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226386 Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9467 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: add RCBA posting read after writingWenkai Du
MEI PCI device has internal logic to flush out the posted writes before returning completion for non-posted request. When doing a RCBA write to function disable and then using the PCI CFG RD cycle, need to do RCBA posting read after writing to it to make sure the write went through. As Aaron sugegsted, abstracted function disable path to a common function. BUG=chrome-os-partner:33048 TEST=run warm and cold reboot testing Change-Id: I40d374f1712a9137b3b1eac6bbf2d71078840406 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f10b368e01aae1fc5dda63f7ac0641dd2636c949 Original-Change-Id: I87aa8ccd604446263fc3621c9a01839a5a75b644 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223715 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9462 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10Broadwell: Synchronization with FRC for Root Port Power ManagementKenji Chen
BUG=chrome-os-partner:31424 TEST=Build a image and run on Samus proto boards to confirm if the settings are applied correctly. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: I9147da86ce26ce7ef1c7034bc3dde0b27b63befa Original-Commit-Id: 1717505a3fdf41c5972b1c929872577247f9e3b5 Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I8138507506771148420a585fd12897a3bfe91916 Original-Reviewed-on: https://chromium-review.googlesource.com/221387 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9463 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Skip DDI-A enable in S3 resumeDuncan Laurie
DDI-A should not need re-enabled in the resume path, just the resume path when we did not execute VBIOS. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus, test suspend+resume Change-Id: I29d67591ac903bc1d712a956462bcf4a764ef2eb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c3fbeac10f3834a6d848154aa3449672871b13df Original-Change-Id: Iaf7d083c5c92c42b7a117e2d2c9546ada6bf5f76 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221988 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9461 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Add support for ACPI \_GPE._SWSDuncan Laurie
In order to report the GPE that woke the system to the kernel coreboot needs to keep track of the first GPE wake source and save it in NVS so it can be returned in \_GPE._SWS method. This is similar to the saving of PM1 status but needs to go through all the GPE0_STS registers and check for enabled and triggered events. A bit of cleanup is done for areas that were touched: - platform.asl was not formatted correctly BUG=chrome-os-partner:8127 BRANCH=samus,auron TEST=manual: - suspend/resume and wake from EC event like keyboard: ACPI _SWS is PM1 Index -1 GPE Index 112 ("special" GPIO27) - suspend/resume and wake from RTC event: ACPI _SWS is PM1 Index 10 GPE Index -1 (RTC) - suspend/resume and wake from power button: ACPI _SWS is PM1 Index 8 GPE Index -1 - suspend/resume and wake from touchpad: ACPI _SWS is PM1 Index -1 GPE Index 13 - suspend/resume and wake from WLAN: ACPI _SWS is PM1 Index -1 GPE Index 10 Change-Id: I574f8cd83c8bb42f420e1a00e71a23aa23195f53 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d4e06c7dfc73f2952ce8f81263e316980aa9760f Original-Change-Id: I9bfbbe4385f2acc2a50f41ae321b4bae262b7078 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220324 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9460 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10baytrail: Switch from ACPI mode to PCI mode for legacy supportMarc Jones
Most Baytrail based devices MMIO registers are reported in ACPI space and the device's PCI config space is disabled. The PCI config space is required for many "legacy" OSs that don't have the ACPI driver loading mechanism. Depthcharge signals the legacy boot path via the SMI 0xCC and the coreboot SMI handler can switch the device specific registers to re-enable PCI config space. BUG=chrome-os-partner:30836 BRANCH=None TEST=Build and boot Rambi SeaBIOS. Change-Id: I87248936e2a7e026f38c147bdf0df378e605e370 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: dbb9205ee22ffce44e965be51ae0bc62d4ca5dd4 Original-Change-Id: Ia5e54f4330eda10a01ce3de5aa4d86779d6e1bf9 Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219801 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Mike Loptien <mike.loptien@se-eng.com> Original-Tested-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/9459 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10southbridge/intel/fsp_rangeley/ : Spellcheck + Formattingnicky sielicki
Changes: acpi.c - Capitalize an acronym. early_spi.c - Spelling error. gpio.c - Capitalization of acronym + sentences. gpio.h - Capitalization of sentences. lpc.c - Capitalization of sentences. soc.c - Spelling error + capitalization of acronym. I just wanted to go through the process of commiting something onto Gerrit. Change-Id: Iad2ac5409f883c5b7cbc25e4e296f386ad7e13d0 Signed-off-by: nicky sielicki <nlsielicki@wisc.edu> Reviewed-on: http://review.coreboot.org/9510 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-04-10vboot: Remove unused 2lib header pathRandall Spangler
Before the change to use vb2_api.h, coreboot needed to know where to find the vboot2 header files. Now those are all included by vb2_api.h, so coreboot doesn't need to know about firmware/2lib/include (and in fact, the 2lib directory is about to go away). BUG=chromium:423882 BRANCH=none TEST=emerge-veyron_pinky coreboot Original-Change-Id: I7f69ca9cf8d45c325219efceca0cb8d1340f7736 Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/233223 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit b4d4a2da1c8b5a5f8f8da51f009227d3a616b096) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4006f38835ea0f927142a8133bc24caaf2b7a214 Reviewed-on: http://review.coreboot.org/9447 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10vboot: Include vb2_api.h, instead of lower-level vboot2 header filesRandall Spangler
This will allow vboot2 to continue refactoring without breaking coreboot, since there's now only a single file which needs to stay in sync. BUG=chromium:423882 BRANCH=none TEST=emerge-veyron_pinky coreboot CQ-DEPEND=CL:233050 Original-Change-Id: I74cae5f0badfb2d795eb5420354b9e6d0b4710f7 Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/233051 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit df55e0365de8da85844f7e7b057ca5d2a9694a8b) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I999af95ccf8c326f2fd2de0f7da50515e02ad904 Reviewed-on: http://review.coreboot.org/9446 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10vboot2: Reduce minimum required work buffer sizeJulius Werner
Apparently our initial submission of 16K was a little too generous for the vboot2 work buffer, and I hear that we should also be well within bounds for 12K. This patch reduces the minimum asserted by memlayout so some of our low-mem boards can get a few more kilobytes back for discretionary spending. Also changes the required minimum alignment to 8 since that's what the current vboot code aligns it to anyway, and add a warning comment to make it clearer that this is a dangerous number people should not be playing with lightly. BRANCH=None BUG=None TEST=Built and booted on Pinky. Original-Change-Id: Iae9c74050500a315c90f5d5517427d755ac1dfea Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232613 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 64e972f10363451cd544fdf8642bd484463703bc) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I362b8c33cf79534bb76bd7acda44d467563fe133 Reviewed-on: http://review.coreboot.org/9445 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10vboot: add physical recovery switch supportDaisuke Nojiri
PHYSICAL_REC_SWITCH is set n by default and y for panther and stumpy. BUG=none BRANCH=ToT TEST=Built nyan_blaze using vboot1/2. Built falco, lumpy, nyan, blaze, parrot, rambi, samus, storm, pinky with default configuration. panther and stumpy are not tested because they currently don't build on ToT. Original-Change-Id: Ic45f78708aaa7e485d2ab459fd1948524edb412f Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227940 Original-Reviewed-on: https://chromium-review.googlesource.com/229602 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit edb2ba347b48887ffe450586af0351e384faad59) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I277f665cd4f3e1c21745cdc5c7a2cfe148661abe Reviewed-on: http://review.coreboot.org/9444 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10vboot2: update fw_version_tpm when creating vboot1 shared dataDaisuke Nojiri
This changes copies firmware version from vboot2 shared data to vboot1 shared data. This fixes FAFT firmware_TPMVersionCheck test. BUG=none BRANCH=ToT TEST=firmware_TPMVersionCheck passed on Nyan Kitty. Original-Change-Id: Idfd282931421dc16cd1aa82c7ccb6c6790a4d0d7 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230186 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Tested-by: Yen Lin <yelin@nvidia.com> (cherry picked from commit 1f590741893bee75d872184eba01c62e92455816) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I205b651976d047923815efcd45b114cc7bf866e4 Reviewed-on: http://review.coreboot.org/9443 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10ramoops: Add support for passing ramoops region through cb tables.Furquan Shaikh
CQ-DEPEND=CL:228856 BUG=chrome-os-partner:33676 BRANCH=None TEST=ramoops buffer verified on ryu. Original-Change-Id: I29584f89ded0c22c4f255a40951a179b54761053 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e8b2c8b75c51160df177edc14c90e5bd3836e931) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I5fdeb59056945a602584584edce9c782151ca8ea Reviewed-on: http://review.coreboot.org/9442 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10chromeos: Add correct dependency on HAVE_ACPI_TABLES for gvns and ramoops.Furquan Shaikh
CQ-DEPEND=CL:228856 BUG=chrome-os-partner:33676 BRANCH=None TEST=Compiles successfully for samus, link, rush_ryu. Original-Change-Id: I8499cab5dd08981a558688964b99b65d78bde476 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228743 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e6aa03752ba8c22b303f3fa590cbc9cf938872ef) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib229756d8dece6f5670460702413f74bc2c692df Reviewed-on: http://review.coreboot.org/9441 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10vboot: reduce references to parent's files in MakefilesDaisuke Nojiri
this change also allows vboot1 code to use flash as nvram device. BUG=none BRANCH=ToT TEST=Built nyan_blazw using vboot1/2. Built falco, lumpy, nyan, blaze, parrot, rambi, samus, storm, pinky with default configuration. Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ie97a4436d4fc10851a535adfdb45c4d499e45b5d Original-Reviewed-on: https://chromium-review.googlesource.com/229598 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8ac8ff28bab1337782e8694275bb2c644b86f38a) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ief087fedbf29b4b82c1668ad5603c121323dcbf2 Reviewed-on: http://review.coreboot.org/9440 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10vboot: fix invalid check for the returned value from spi_flash->writeDaisuke Nojiri
spi_flash->write returns non-zero on error and zero on success, not the number of bytes written. BUG=none BRANCH=ToT TEST=Booted storm. Verified successfully nvdata was saved. Original-Change-Id: If50cc1a62a4f06398d1830cca60085b6f925fff3 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229389 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 1e8cdbdb07e99c3f72c35f76d68144f46107acd9) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I216e97f734da8d4b52c2da8329f4143b7b0656cd Reviewed-on: http://review.coreboot.org/9439 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10cbtables: Add RAM config informationDavid Hendricks
This adds the RAM config code to the coreboot tables. The purpose is to expose this information to software running at higher levels, e.g. to print the RAM config coreboot is using as part of factory tests. The prototype for ram_code() is in boardid.h since they are closely related and will likely have common code. BUG=chrome-os-partner:31728 BRANCH=none TEST=tested w/ follow-up CLs on pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Idd38ec5b6af16e87dfff2e3750c18fdaea604400 Original-Reviewed-on: https://chromium-review.googlesource.com/227248 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 77dd5fb9347b53bb8a64ad22341257fb3be0c106) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ibe7044cafe0a61214ac2d7fea5f7255b2c11829b Reviewed-on: http://review.coreboot.org/9438 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-04-10vboot: adding VBSD_BOOT_FIRMWARE_WP_ENABLED logicGediminas Ramanauskas
BUG=chrome-os-partner:33395 BRANCH=none TEST=emerge and test using crossystem Original-Change-Id: I0d49f85219d45c837a7100e0195bef86da2c6cdd Original-Signed-off-by: Gediminas Ramanauskas <gedis@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227546 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5a2868e04140973691136adfd7d9e6d1aa1f6dae) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I93c1ea9ce1270c2c143fd44ead2291dfbc114c00 Reviewed-on: http://review.coreboot.org/9437 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10fmap: use CBFS for all other than x86 platformsVadim Bendebury
The architectiure check in fmap.c is in fact used to delineate between platforms where SPI flash is mapped to memory address space and where it needs to be accessed through CBFS. In fact cosmos board uses an ARM SOC which also maps SPI flash to processor address space, this will have to be addressed when that SOC's support is introduced, for now let's just presume that all but X86 platforms require CBFS layer to access fmap. BRANCH=none BUG=chrome-os-partner:31438 TEST=none Original-Change-Id: Id135dc63278555a7fc5039a568fb28864f7cb8d1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226180 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit b3c04f84504380066c54a6dec93781a4f25a5fc6) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I3a0a70fe583b69b1c9cd8729817bd7062126e1a9 Reviewed-on: http://review.coreboot.org/9436 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10chromeos: Add a function to copy VPD WiFi calibration data to CBMEMVadim Bendebury
This patch adds functions looking in the VPD for WiFi calibration data, and if found, copying the calibration blobs into CBMEM. Two possible key names templates are used: wifi_base64_calibrationX and wifi_calibrationX, where X is replaced by the WiFi interface number. Up to four interfaces can be provisioned. The calibration data will be retrieved from CBMEM by the bootloader and placed into the device tree before starting the kernel. The structure of the WiFi calibration data CBMEM entry is defined locally: it is a concatenation of the blob names and their contents. Each blob is padded as necessary to make sure that the size divisible by four. To make sure that the exactly required amount of memory is allocated for the CBMEM entry, the function first scans the VPD, caching the information about the available blobs and calculating their combined size. Then the required size CBMEM entry is allocates and the blobs are copied into it. BRANCH=storm BUG=chrome-os-partner:32611 TEST=when this function is called, and the VPD includes calibration data blobs, the WIFI entry shows up in the list of CBMEM entries reported by coreboot. Original-Change-Id: Ibe02dc36ff6254e3b9ad0a5bd2696ca29e1b2be3 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225271 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9fe185ae5fdc1a896bf892b498bff27a3462caeb) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia60f0c5c84decf9854426c4f0cb88f8ccee69046 Reviewed-on: http://review.coreboot.org/9435 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10vboot: move vboot files to designated directoryDaisuke Nojiri
This moves vboot1 and vboot2 files to their designated directory. Common code stays in vendorcode/google/chromeos. BUG=none BRANCH=none TEST=built cosmos, veyron_pinky, rush_ryu, nyan_blaze, samus, parrot, lumpy, daisy_spring, and storm. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia9fb41ba30930b79b222269acfade7ef44b23626 Original-Reviewed-on: https://chromium-review.googlesource.com/222874 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit cbfef9ad40776d890e2149b9db788fe0b387d210) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia73696accfd93cc14ca83516fa77f87331faef51 Reviewed-on: http://review.coreboot.org/9433 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10build system: Fix SeaBIOS integration with multilib compilersPatrick Georgi
SeaBIOS doesn't like CC and LD to contain arguments, so split those out. Change-Id: Id651719d529adfa8602a3e4f6685228330f36432 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9378 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2015-04-10mainboard/biostar: Add support for Biostar AM1ML ver7.xSergej Ivanov
Adds AM1ML board. This board has AM1 Socket and supports all new AM1 APUs from AMD. Based on asrock/imb-a180 board. Successfully tested with SeaBIOS and Linux 3.8.x and Windows XP. Successfully tested audio, video, network, PS/2 keyboard and mouse, PCIe x16, COM port, SATA and USB. LPT port is not tested yet and it’s unknown if it’s work. Change-Id: I9ebb9acc590d38e47579adc263f45ae3f607684e Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: http://review.coreboot.org/9293 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-04-10vendorcode/amd/agesa/f16kb: Enable support for AM1 socketSergej Ivanov
Adds option FORCE_AM1_SOCKET_SUPPORT to disable package type mismatch check between cpu and northbridge. Default agesa for kabini doesn't know about AM1 socket so it returns FALSE, that stops memory config code. With this hack current agesa version supports the AM1 socket. Change-Id: I99e9cec5cd558087092cf195094df20489f6d3b5 Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: http://review.coreboot.org/9291 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-04-10southbridge/amd/agesa/hudson: Fix LPC_DEV definitionSergej Ivanov
In agesa code for hudson southbridge LPC_DEV is not defined, but used. Define LPC_DEV as done in southbridge/amd/cimx/sb800. This fixes it. Change-Id: Ie7db791e9eb607008e70e446fc6fd28114742750 Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: http://review.coreboot.org/9292 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-04-10google/cosmos: don't enable CHROMEOS by defaultPatrick Georgi
This isn't done in upstream. Change-Id: Ief1fea0f231d609372f065f6f6aee7bceaf31efc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9458 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10util/bimgtool: Add verification modeVadim Bendebury
When only one argument is passed on the command line, consider this argument the name of the BIMG formatted file, and verify its integrity. Update the help/usage text to match new behavior. BRANCH=none BUG=none TEST=when the corrupted coreboot BIMG image is passed as the only argument, this utility reports the problem. With the build fixed, the check passes without errors (the second invocation below). $ build/util/bimgtool/bimgtool /build/urara/firmware/coreboot.rom.serial Data header CRC mismatch at 0 $ build/util/bimgtool/bimgtool /build/urara/firmware/coreboot.rom.serial $ Change-Id: I9f0672caa38e3d27917471fc5137ede4ca466e9a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3e631c311dbf2fb04714e437f95c41629155527f Original-Change-Id: Ie56f87f99838891d8e341d7989c614efbcabe0cd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227522 Original-Reviewed-by: Zdenko Pulitika <zdenko.pulitika@imgtec.com> Original-Tested-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/9452 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10ipq806x: Remove extra INCLUDESPatrick Georgi
That variable isn't used anymore and the include statement is already covered in CPPFLAGS_common further down that file. Change-Id: I3e4fd3281dc0d3f73b238e121dbdfc0d29102b27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9448 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush: Add I2C1 init and audio clock enable/resetsTom Warren
This should allow the max98090 codec to play beeps via AHUB/I2S1 thru the depthcharge sound driver. BUG=none BRANCH=none TEST=Saw max98090 codec init signon and register dump. No sound yet. Change-Id: I1ee0b61f5cbfe587ebd16b7dd9dce08d9d62c2c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4ee2ce3704711a9e00531b7599a1bcf194203ec Original-Change-Id: I0bc8401e76b2c80a01083ac933a39f6cd4d1b78a Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229496 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Mike Frysinger <vapier@chromium.org> Reviewed-on: http://review.coreboot.org/9429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add routine to enable all audio periphs under AHUBTom Warren
If all devices under AHUB (AUDIO/I2S/DAM/ADX/etc) aren't clocked and taken out of reset, any access to any audio peripheral will hang the system. BUG=none BRANCH=none TEST=built both Rush and Ryu OK. Change-Id: Iee8e33f005c5abaf09a14104c0b243b06eb4af24 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0016bd533864942225f2fb8e08ce871a186f2746 Original-Change-Id: I741d5ba4dd8bd963b6d261fbf41cfb77c274cb79 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229910 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Mike Frysinger <vapier@chromium.org> Reviewed-on: http://review.coreboot.org/9428 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add I2C1 support to funitTom Warren
I2C1 was missing in the funit/i2c/addressmap tables/code. BUG=none BRANCH=none TEST=Built Rush and Ryu. Built Rush w/code in mainboard.c to enable I2C1 for the MAX98090 audio codec - codec could be configured. Change-Id: I0c678d21546eedb7404a1d3d4329da777430fc97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b623097a2adc4464c17bceed96ec3838beda985 Original-Change-Id: Ibe4f012fa2d427b95cd4672687132b47576b6a9a Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229574 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9427 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Add support for event logFurquan Shaikh
BUG=chrome-os-partner:33764 BRANCH=None TEST=Event logs verified on ryu across multiple boots. Change-Id: Iff4a60b3904ef0fcdd2513df579db8f5877808de Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbe6290de7eaed0d66a26cc2389181a8d38a59d6 Original-Change-Id: I50d052bb15ec6616b0bf82bf1f1acf9080f4c54b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229415 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9426 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10rtc: Add an RTC driver for the TI TPS65913 PMIC.Furquan Shaikh
The TPS65913 PMIC has an RTC built into it. This change adds a driver for it which implements the new RTC API. BUG=chrome-os-partner:33764 BRANCH=None TEST=Compiles and boots to kernel prompt on ryu. Timestamps for event log verified across multiple boots. Change-Id: I49ec9b78afc53f1cbd4be09e448cdae6077fb710 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c16c11e620c830e7a73a2a24fe4823ccea0f3c39 Original-Change-Id: If1d549ea2361d0de6be75fd24b9e9810a6df7457 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229414 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9425 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10elog: Hide elog_flash_offset_to_address() from SMMFurquan Shaikh
Change-Id: Iaef9d4755f07ca03ca823831c3272183b5d6aed1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c3db3d5c8e00b6c273ae240da137062597749aa Original-Change-Id: I5e38966fe06aa3302a7c1b536f5ffd8bb22d4947 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229413 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9450 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10elog: Fix typecast issues related to 64-bit compilation.Furquan Shaikh
BUG=chrome-os-partner:33764 BRANCH=None TEST=Compiles successfully for ryu and nyan. Change-Id: I036fd42d5cd4b71bcb68eea0fdd9a4e1aa4711e9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c3db3d5c8e00b6c273ae240da137062597749aa Original-Change-Id: I5e38966fe06aa3302a7c1b536f5ffd8bb22d4947 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229413 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9424 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 13:12:22 +0000