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2014-12-19libpayload: hexdump: Use `p` as conversion specifier for pointersPaul Menzel
Change-Id: Ie5c279ef90bd9ed5e2624bf852dcff1f06531a13 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4767 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-19intel/i945: Use define for `BSM`Paul Menzel
Change-Id: Ia58d8b410a145f27f0b267c115714580c366e063 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5929 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-19libpayload/libc/hexdump.c: Take `const void *memory` as argumentPaul Menzel
`*memory` is not changed in `hexdump()` and just read so make it `const`. Change-Id: I9504d25ab5c785f05c39c9a4f48c21f68659a829 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5403 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-19intel/truxton: Add dummy cache-as-ram regionKyösti Mälkki
Board has no chance of working without a cache_as_ram.inc, but without a specified CAR region we also break builds. Change-Id: I98e9db38c5e0a7bf4a1b8d2f8a693cc8d0c773b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7863 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19gigabyte/ga-b75m-d3h: Drop redundant EARLY_CBMEM_INITKyösti Mälkki
It is implied by DYNAMIC_CBMEM. Change-Id: I6859c4950ce568fb76c7604e9e994031a3d94d78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7857 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19beaglebone: use new arm bootblock infrastructureAlexander Couzens
8b685398 change config flags for cpu and mainboard bootblock initialization. Tested on beaglebone black. Change-Id: Ifac4a18a2e380c3472f51aaa7cc7842b01a2553e Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/7190 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-12-19arm/ti/am335x: use new arm bootblock infrastructureAlexander Couzens
commit 8b685398 (ARM: Overhaul the ARM Makefile.) changes config flags for cpu and mainboard bootblock initialization. Tested on beaglebone black. Change-Id: I70cbe3abad8443c5dc71c8ba76a35973a5284477 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/7189 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-12-19AMD amdfam10: Drop EXT_CONF_SUPPORTKyösti Mälkki
Only used for AMD K8 siemens/sitemp_g1p1 with southbridge rs690. Change-Id: Ie98a77ce190b1bd35996c7f25da0a0fe9819c9c3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7809 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19AGESA fam12 fam14: Drop EXT_CONF_SUPPORTKyösti Mälkki
Only used on non-AGESA board siemens/sitemp_g1p1 and already dropped from other AGESA families. Change-Id: Ifa726d38216c8b684af06af26b701daa99c42e8c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7808 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19AMD binaryPI: Drop EXT_CONF_SUPPORTKyösti Mälkki
Change-Id: I2ec08df2eb8e65bc759de9917894df9d0c8b1995 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7807 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19spd_cache debug: Log invalid CRC checksumTobias Diedrich
"SPD has a invalid or zero-valued CRC" is not a very useful message, so show the actual and expected values. Change-Id: I31a1cdacc82240c699627769d490b94f5d378e86 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/7393 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-19mainboard: Strip out some dead includesEdward O'Callaghan
Change-Id: I0079fa089ba863c6e447bcee3440a7e0ba0f2372 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7429 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-12-19build system: allow defining alignment for cbfs-filesPatrick Georgi
Just set $(filename)-align to the desired alignment, and the build system will figure it out using cbfstool locate. Change-Id: I44369d947888041c21ff51ae49f9aacf510918a0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7728 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@gmx.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-19util/superiotool: change displayed name of chip id 0xc333 (nct6776)Felix Held
nct6776f and nct6776d are just two package variants containing the same die Change-Id: I4d319fa0e791e66ad04857dede2fdfc8e42dd45a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/7806 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-19util/superiotool: fix default values for nct6776 (rev. c)Felix Held
change default values according to the datasheet in revision 1.2 Change-Id: Iec1d55dd7b906a7a41940f3f8e42413922883efd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/7805 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-19ifdtool: Add O_BINARY to open flags for Windows compatibilityScott Duplichan
Windows requires O_BINARY when opening a binary file. Otherwise \n characters get expanded to \r\n and <ctrl>z is treated as end of file. For compatibility with non-Windows hosts, the patch defines O_BINARY if it is not already defined. Change-Id: I04cd609b644b1edbe9104153b43b9996811ffd38 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/7789 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19arm_boot_tools: Add 'b' to fopen flags for Windows compatibilityScott Duplichan
Windows requires the 'b' (binary) flag when using fopen to open a binary file. Otherwise \n characters get expanded to \r\n and <ctrl>z is treated as end of file. Change-Id: I3b85e4f9a8f7749801a39154881fe2eedd33f9b8 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/7790 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19AMD 00730F01: Change Makefile to use BLOB sizes for packingBruce Griffith
The new AMD PSP and SMU BLOBs currently have fixed sizes in the southbridge Makefile. Future PSP and SMU updates may require more space and thereby cause the make to fail with cryptic error messages. Change the makefile to compute CBFS locations and the corresponding PSP pointer table entry values based on the actual file sizes. Additionally, the FWM directory has expanded to 4096 bytes. The Avalon makefile is modified to zero-pad the FWM directory using the "dd" system command. There is dead code in the makefile to allow hardware validated boot ROMs, but the option is hard-coded to be disabled. Remove the HVB dead code. Change-Id: I4705cede8ed001a71bb4f49598444255c9609d52 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/7726 Reviewed-by: Marshall Dawson <marshall.dawson@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19southbridge/amd/cimx/sbX00/early.c: Update grammar in commentsMartin Roth
Along with the spelling fixes, it was requested that I correct this comment. Updating "LocateImage() take minutes" to "LocateImage() takes minutes" everywhere that comment occurs. Change-Id: I28cd47476cb42ba3e404e064695a7fd97d581834 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7848 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19fsp_baytrail: Initialize LPC pads in bootblock for port 80Martin Roth
Port 80h codes were coming out of bootblock and romstage scrambled, or were not coming out at all. Initializing the LPC signal pads as LPC fixes that issue. Change-Id: I16943513f2eb6fe8fa58766aaa82dac182440c34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7802 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@gmx.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19fsp_baytrail: Remove GPIO_NC1 #defineMartin Roth
The GPIO_NC1 #define was added to handle GPIOs that are not on func0. This is already handled elsewhere in the GPIO code, so is not needed. - Remove the single GPIO_NC1 from platforms using fsp_baytrail - Revert the GPIO_INPUT_PU_10k #define to remove the _func argument. Update everywhere this macro is called. - Remove GPIO_NC1 Change-Id: I32f337af7bc88eab821d9a8c375145b45718275f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7849 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19baytrail SOCs: Add missing comma in gpio.hMartin Roth
The GPIO_OUT_LOW #define was missing an internal comma in both soc/intel/baytrail and soc/intel/fsp_baytrail. Thanks to Werner Zeh for pointing this out. Change-Id: I2e5507058739e5fdc2c0e43e0380058458870e46 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7801 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
2014-12-18amd/olivehillplus/romstage.c: remove not useful variable 'halt'WANG Siyuan
The variable 'halt' is not useful and results in a compile error because of: 1b2f2a07 Introduce halt() build error: src/mainboard/amd/olivehillplus/romstage.c: In function 'cache_as_ram_main': src/mainboard/amd/olivehillplus/romstage.c:43:15: error: declaration of 'halt' shadows a global declaration [-Werror=shadow] In file included from src/include/cpu/x86/lapic.h:6:0, from src/mainboard/amd/olivehillplus/romstage.c:29: src/include/halt.h:31:32: error: shadowed declaration is here [-Werror=shadow] cc1: all warnings being treated as errors make: *** [build/mainboard/amd/olivehillplus/romstage.pre.inc] Error 1 Change-Id: Id67a0dcb192fb6478115e489f46bfb07021afd90 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/7847 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-18i82371eb & qemu: Move to per-device ACPI.Vladimir Serbinenko
This one is special because qemu is really far from anything real but shares some common features. Change-Id: Ia1631611724a074780e1fece50166730b2ee94ae Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6939 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-18nvidia/cbootimage: update to latest upstreamPatrick Georgi
Scott Duplichan provided a win32 related fix that we want to use. Change-Id: I791b470f9f6c5bf140fc190d290741f35f05d254 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7827 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop VIA Epia-NStefan Reinauer
ROMCC cleanup. Change-Id: Id72e6fcb89165f28cad8bf3a5b632d3fa094b7dd Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7855 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop VIA Epia-M series of boardsStefan Reinauer
ROMCC cleanups Change-Id: Ic4c9d9eb8c7edc506c8a8e8eeeacf759cbaead74 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7854 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop VIA Epia mainboardStefan Reinauer
.. and also drop the northbridge and southbridge used by the board. This is one of the last boards to not use ROMCC for romstage. Let's get rid of it. Change-Id: I0a864b2c4ce3eeb7d3e199944eedef0cd71a85e6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7853 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop Intel E7520 and E7525 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Also drop unused dependencies Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7836 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18intel/truxton: Un-romcc-ify boardStefan Reinauer
Change-Id: Iaf1756321960041f6a152d5dd4c9108291f51300 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7852 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-18AMD Trinity: Update SMU firmware from 10.9 to 10.14Zheng Bao
The first dword in FirmwareTN has been changed from 0xa0009 to 0xa000e. The FirmwareTNHeader is not called by any one in latest PI. It seems to be useless for now. Change-Id: Ic7a20e0bcca8de0b56c7bc5d01e0ce86347bde21 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-12-17chromeos: Add empty functions when CONFIG_CHROMEOS is disabledDuncan Laurie
This allows the chromeos header and functions to be included without needing to guard with #if CONFIG_CHROMEOS. BUG=chrome-os-partner:28234 BRANCH=None TEST=emerge-rambi coreboot Original-Change-Id: I523813dc9521d533242ae2d2bc822eb8b0ffa5e2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196265 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit b78ccada9a01f54a60993dfc2c618201d31df9ad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic2f7127966da716e114336c30829a6403d82e180 Reviewed-on: http://review.coreboot.org/7843 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17elog: Fix chromium merge issueMarc Jones
This cleans up a mis-merge in elog.c and puts the following change back: drivers/elog: Unmangle header include out of pre-proc cond commit a3119e5835e4b8fd510d046c56a3bf2bf43a5c0d Change-Id: Iafbbd381efdb103717022d2a3c342da376a9428f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17baytrail: initialize backlight PWM frequencyAaron Durbin
In order to protect ourselves from the kernel driver not honoring or placing the correct frequency in the backlight register always set one. This code path picks 200Hz as the default if nothing is specified in device tree. It's somewhat arbitrary but that frequency is valid for all the eDP panel specs we've seen being used on baytrail devices. BUG=chrome-os-partner:28267 BRANCH=baytrail TEST=Built and booted in normal mode. Noted register write stuck. Original-Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196821 Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com> (cherry picked from commit 2eaa650860ebbc838dbf8c1c1ca2259ac64141ac) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5 Reviewed-on: http://review.coreboot.org/7845 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17rambi: align gpu pipea settings with the VBIOSAaron Durbin
In the normal mode case these settings aren't overwritten by the VBIOS because the VBIOS does not run. Therefore, the settings need to align with what the VBIOS programs so that there is a consistent panel power sequencing. BUG=chrome-os-partner:28267 BRANCH=baytrail TEST=Built and booted. Noted settings set by firmware for both dev and normal mode match. Original-Change-Id: Iccf65e2a6bce6859fd7cb0f466d4b44d654523ce Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196822 Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com> (cherry picked from commit 12999018f2b08df0c3b9cdac1f16e9c4517ea803) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idf1a701ffcb1c990cec2ca1ccca24cc0d26fabbf Reviewed-on: http://review.coreboot.org/7846 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17x86: Initialize SPI controller explicitly during PCH initDavid Hendricks
This ensures that SPI is ready when eventlog code is used. x86 platforms which use eventlog invoke elog_clear() in GSMI and elog_add_event_raw() when deciding the boot path based on ME status. For the SMM case spi_init() is called during the finalize stage in SMM setup. For the boot path case we can call spi_init() at the beginning of BS_DEV_INIT and it will be ready to use when the boot path is determined from the ME status. BUG=none BRANCH=none TEST=tested on Link (bd82x6x), Beltino (Lynxpoint), and Rambi (Baytrail) with follow-up patch Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id3aef0fc7d4df5aaa3c1c2c2383b339430e7a6a1 Original-Reviewed-on: https://chromium-review.googlesource.com/194525 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 173d8f08e867bab8c97a6c733580917f5892a45d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifaed677bbb141377b36bd9910b2b1c3402654aad Reviewed-on: http://review.coreboot.org/7756 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-17chromeos: vboot_loader: Add support for SW_WP_ENABLED flagShawn Nematbakhsh
Set VB_INIT_FLAG_SW_WP_ENABLED according to the status returned by an optional platform / mainboard function vboot_get_sw_write_protect(). BUG=chrome-os-partner:26777 TEST=Manual on Rambi with all patches in sequence: `crossystem sw_wpsw_boot` prints 0 `flashrom --wp-enable` and reboot `crossystem sw_wpsw_boot` prints 1 BRANCH=Rambi Original-Change-Id: Ifb852d75cc106d10120cfee0a396b0662282051a Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190096 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c4668fc8a9ab31d9cf876b3d9ad3405756d4d683) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idace325439958f6b490d2e6705d55e95305c4b2a Reviewed-on: http://review.coreboot.org/7750 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: cbmem: Move the call to cbmemc_reinit.Gabe Black
The call was after the call to vboot_verify_firmware and so would only be called when falling back to RO, aka recovery mode. This change moves it to before vboot_verify_firmware so we'll always have the cbmem console. BUG=None TEST=Built and booted on nyan and verified that the cbmem console was the same as the serial output. Built for big and blaze. BRANCH=nyan Original-Change-Id: I02d01110659689b08d32777dae384ac3e01b3b9f Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/196158 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d3e4a778e4a0f5ade7d633d8ce7e72ef06c44086) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id14a19a78bcb21cb0c4030c2e41195e491f690d5 Reviewed-on: http://review.coreboot.org/7777 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17tegra124: modify panel init sequenceKen Chang
Panel datasheet defines some delay between PWM signal out and backlight enable. This change fixes the current sequence and makes the delays adjustable by dt setting. BRANCH=none BUG=chrome-os-partner:28008 TEST=Verified on Big DVT and Nyan/Norrin panels. Panel works fine with dev mode, and the measurement of power on sequence meets panel requirements. Original-Change-Id: If6015bbb6015a3b203d425f5e90f676ad786b5e8 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/196183 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 2bbcaa7281222ffc0b4026e8b1eb4c210a8e308a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id6424f66eb8dc6adeb70eaa33df742f4e57983c3 Reviewed-on: http://review.coreboot.org/7776 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: enable CLAMP_INPUTSKen Chang
Enable pinmux clamp function to avoid pinmux conflict. For pins which are configured to tristate enabled, the inputs to the controller will be clamped to zero. This can be used to avoid pinmux conflicts since the tristate bit is set to 1 in the power-on-reset pinmux setting. With pinmux clamp enabled, we need to configure all the input pins to tristate disabled. BUG=chrome-os-partner:27091 BRANCH=None TEST=built and booted successfully, display worked fine. Original-Change-Id: Id79a717f2025c812908c7152d439351208aee8d2 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194060 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c95d6fe79810612cfad721667657cdcb87068d23) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1b23df8b90f83ea2b2c08c4364d90fe71533a5a0 Reviewed-on: http://review.coreboot.org/7775 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: Add eventlog supportDavid Hendricks
This enables event logging support for Nyan platforms. Right now this doesn't do a whole lot. We can add events in later CLs. BUG=none BRANCH=none TEST=built and booted for Nyan Rev. 1, eventlog gets initialized if necessary and can be printed by "mosys eventlog list" Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id77a78f55c8bff9ef0ffc7109c8b03c270e8b6b1 Original-Reviewed-on: https://chromium-review.googlesource.com/191200 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 1bb1a00863a63e53379b02f2b466d4d8ae3cef50) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3a5d896d97dfc66ec37114bd3bac3f34e1c22bf7 Reviewed-on: http://review.coreboot.org/7774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-17Revert "elog: Use the RTC driver interface instead of reading CMOS directly."Marc Jones
This reverts commit 474313d1b6556ad8b3e6750a4096b5735cbfc846. This reverted commit was applied out of sequence and there are a number of dependencies that need to be in place prior to adding it. Remove it for now. Change-Id: If80c40867098dee2feff2b9a1d824558f4d7028d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17lib/edid.c: Use 'hh' instead of 'h' length modifier in printkAlexandru Gagniuc
The length modifiers for unsigned char were accidentally changed from 'hh' to 'h' with commit: * 1c8ee21 edid: Change static variables to auto variables. Change-Id: I4b3e63cbcde7635b842894f776373f7946bd0df8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4477 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-17intel/minnowmax: Determine board type from GPIOsMartin Roth
SSUS GPIO 5 reflects the Minnowboard Max SKU: --- GPIO 5 low is a 1GB board --- GPIO 5 high is a 2GB (or 4GB in the future) board. This allows us to determine the board type at runtime and configure the FSP appropriately. Change-Id: I9f75df5413d23d63280b601457ea9a1ff020d717 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7797 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-17fsp_baytrail: Add code to read GPIOs in romstageMartin Roth
- Build gpio.c into romstage - Add functions to translate the GPIO # to a pad #, then return the value read from the GPIO. - Add functions to configure the GPIO - Function, Pull up/down, pull strength, Input/Output, and Output level. Change-Id: Ic37dfc9a74a598023bdf797d31087428adec176a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7796 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
2014-12-17southbridge/amd rs690 & rs780 spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: I5a5af71ea49152accd92dc331a19e57f3717e4ff Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7841 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17southbridge/amd agesa & cimx spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: I5d2d4ba098d2a95f7643f000f4b48b3349a8e6cf Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7839 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17southbridge/amd amd81XX, cs553X & sr5650 spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: Ice5d8ce9408356c866a9a2ee5a03f704f55ddc2a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7842 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-17southbridge/amd sb600, sb700 & sb900 spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: I31333742d9c90cf6d7ae3d2f324880ed53807d7f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7840 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17southbridge/nvidia: Spelling/comment fixMartin Roth
Change-Id: I4f9b2b8375abe4691f279df649eaf822b87509e5 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7731 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 13:15:53 +0000