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2018-01-30soc/amd/stoneyridge: initialize i2c buses marked as early initAaron Durbin
Initialize the i2c buses that are marked as early init in the device tree. BUG=b:70232394,b:69250772 Change-Id: Iced1797f3bb4765646736c423b081cdc33c12a48 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30soc/amd/stoneyridge: fix gpio_acpi_path()Aaron Durbin
The path for the GPIO devices needs to be '\_SB', not '\SB'. Fix the path so that it references the system bus. BUG=b:72121803 Change-Id: I7c6c38ecea0f8f95ff52b3390f92c5b7e79bcd6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23501 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30soc/amd/stoneyridge: use new host controller programmingAaron Durbin
The SPI controller on stoneyridge apparently has a large fifo and an alternate method for programming the controller. The fifo is directly accessible as well as the rx and tx pointer in addition to the execute bit. Remove the unneeded #defines and program the host controller with the above changes in mind. In addition, add debug hooks to the driver so one can dump the state of the controller when in operation. The time it took to read 4KiB of flash in the elog driver went from 20593 microseconds to 5693 microseconds on cdx03/kahlee. BUG=b:65485690 Change-Id: Ie7ea9d18cef5511686700ad9b2b9fdfeb6d5685b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23493 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30soc/amd/stoneyridge: utilize full SPI flash controller fifoAaron Durbin
The spi flash host controller has a dedicated register for the opcode. Therefore, indicate to the spi subsystem that the opcode size should not be taken into account when determining maximum payload size in spi_crop_chunk(). This allows the full use of the fifo when doing transfers. BUG=b:65485690 Change-Id: Iab27a69ca72fd02bc443f0673983f3b22ffca0f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23492 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30drivers/spi: support cmd opcode deduction for spi_crop_chunk()Aaron Durbin
spi_crop_chunk() currently supports deducting the command length when determining maximum payload size in a transaction. Add support for deducting just the opcode part of the command by replacing deduct_cmd_len field to generic flags field. The two enums supported drive the logic within spi_crop_chunk(): SPI_CNTRLR_DEDUCT_CMD_LEN SPI_CNTRLR_DEDUCT_OPCODE_LEN All existing users of deduct_cmd_len were converted to using the flags field. BUG=b:65485690 Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23491 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-29google/scarlet: Add initialization sequence for Innolux P097PFG panelLin Huang
Innolux didn't deliver a working init sequence yet for devices without OTP programming. The sequence in this change has been derived from a register dump of a mostly working panel with OTP. It is not meant to be final, but to make devices with unprogrammed OTP work, while Innolux is figuring out a proper sequence. There is a known issue with an artifact line in the lower third of the display. Change-Id: I7096506208e4cb29c5f31a7ac502231a6c23ac92 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-29rockchip/rk3399: Support LONG_WRITE type in MIPI DSILin Huang
Some panels need to transfer initial code, and some of them will be over 3 bytes, so support LONG_WRITE type in driver. Refactor mipi dsi transfer function to support it. Change-Id: I212c14165e074c40a4a1a25140d9e8dfdfba465f Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-29google/fizz: Adjust PL2 and PsysPl2 values for power lossShelley Chen
Set PsysPl2 values to 90% of max adapter power for all types of adapters (typeC and barrel jack) to account for a 10% power loss from the adapter to the soc. BUG=b:71594855 BRANCH=None TEST=reboot device and make sure Pl2 and PsysPl2 MSRs are properly set with iotools rdmsr command on both U42 and U22 skus with both typeC and barrel jack power adapters. Change-Id: I8425c6d4d669449eccb9324ff58ff6d1662c5c43 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-29mb/google/kahlee: Fix I2C bus 1 timing for GruntJustin TerAvest
I measured the rise and fall times for I2C bus 1 from userspace manually, using "i2cdetect 1" called from userspace and an oscilloscope. This commit fixes the values there to reflect reality. BUG=b:72442912,b:70232394 Change-Id: I4f593cb2674006060cad9a77753c23f7d9828c9b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23459 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-29Makefile: Add filelist to helpMartin Roth
The filelist target has been around for a while, but was never added to the help. Add it now. Change-Id: Idc24ecc8028fc61c6b798c0c81431b05dfa25b0e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-29util/lint/checkpatch.pl: Untaint filenameMartin Roth
This fixes the warning that is seen on the jenkins server: Insecure dependency in piped open while running setgid at util/lint/checkpatch.pl line 958. Change-Id: I476efa76ef6a275584a47ec0ecf2315948d53e9d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-29intel: Prepare registers so Windows drivers are happierPatrick Georgi
Change-Id: I12ebed30de4df9814ccb62341c7715fc62c7f5b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/23431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-28soc/intel/denverton_ns: Rename HARCUVAR macros to DENVERTONJulien Viard de Galbert
Harcuvar is the board name, Denverton is the SoC. So macros in files under soc/ should be named after the SoC not the board. Change-Id: I1c7d5b93fba386b8e9bd86cf599508e642e21a75 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shine Liu <shine.liu@intel.com> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-28amd/stoneyridge: Add NV storage to ramtopMarshall Dawson
The scratch registers in northbridge used for storing the top of cacheable memory are volatile. Use the BiosRam storage in the FCH instead. TEST=Suspend and resume Kahlee with complete S3 patch stack BUG=b:69614064 Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26drivers/spi/spi_flash: honor spi controller fifo size for readsAaron Durbin
The spi_flash_cmd_read_fast() and spi_flash_cmd_read_slow() were just passing full size buffers to the spi controller ops. However, the code wasn't honoring what the spi controller can actually perform. This would cause failures to read on controllers when large requests were sent in. Fix this by introducing a spi_flash_cmd_read_array_wrapped() function that calls spi_flash_cmd_read_array() in a loop once the maximum transfer size is calculated based on the spi controller's settings. BUG=b:65485690 Change-Id: I442d6e77a93fda411cb289b606189e490a4e464e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-26soc/intel/cannonlake: Add Cannonlake D0 support in mpinit and reportLijian Zhao
Both early platform information reporting in bootblock and common code CPU driver will add support for cannonlake D0 stepping processor. BUG=None TEST=Boot up system with D0 stepping CPU installed, check serial log that can display as D0 stepping. Change-Id: I76ee974ee027100d7853a110f95b1601987492e4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26soc/intel/apollolake: select NO_UART_ON_SUPERIORavi Sarawadi
If not, legacy COM ports will be enumerated by kernel and console will not work. localhost ~ # cat /proc/tty/driver/serial serinfo:1.0 driver revision: 0: uart:16550A port:000003F8 irq:4 tx:0 rx:0 1: uart:16550A mmio:0xC112D000 irq:4 tx:764 rx:0 RTS|DTR 2: uart:16550A mmio:0xC112F000 irq:6 tx:0 rx:0 3: uart:unknown port:000002E8 irq:3 With this fix: 0: uart:16550A mmio:0xC112D000 irq:4 tx:0 rx:0 1: uart:16550A mmio:0xC112F000 irq:6 tx:858 rx:42 RTS|DTR 2: uart:unknown port:000003E8 irq:4 3: uart:unknown port:000002E8 irq:3 Change-Id: Iac5bf65900e090d4e785e0cd828272ebff209458 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-26amd/stoneyridge: Convert BiosRam access to MMIOMarshall Dawson
Change the BiosRam read/write functions to use the fixed MMIO range at 0xfed80500. This is faster than two accesses per byte when using I/O 0xcd4/0xcd5. Note that BiosRam may only be accessed byte-by-byte. It does not decode normally. Change-Id: I9d8baf2bd5d9d48a87bddfb6a0b86e292a8fdf7d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23436 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-26nb/intel/sandybridge: Use common mrc cache functionsArthur Heymans
This uses the functions in include/mrc_cache.h instead of northbidge/intel/common/mrc_cache.h Tested working on Lenovo Thinkpad x220, mrc_cache region gets written and S3 resume still works fine. Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26ec/google/chromeec: Add _PRW property to CREC deviceFurquan Shaikh
This change adds _PRW property to CREC device that allows Linux kernel to identify CREC as a wakeup source. BUG=b:69118395 TEST=Verified following steps: 1. Under sys devices for CREC: "echo enabled > wakeup" 2. Lid close/Lid open -- Verified that wakeup_count increases 3. Mode change -- Verified that wakeup_count increases Change-Id: Ib0a687e171c7e5c81325b39f47c9a2462553fe3e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-26mb/*/*/cmos.layout: Fix the values for the console levelArthur Heymans
Fix the values that were off by one. This was discovered when using postcar stage that prints with debuglevel BIOS_NEVER. Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-26util/lint: Apply `final newlines` check to scriptsAlex Thiessen
The `lint-extended-015-final-newlines` script skips over executable files and thus leaves script files unchecked. Use `file` to find scripts and include them in the `final newlines` checks. Whitelisting is used including bash, perl, python and sh scripts. Change-Id: I8649b261b7e2cbbac7f9b90a9ace3f1c7b0eedeb Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23325 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-26smbios: handle DIMM of 32G or moreJulien Viard de Galbert
According to SMBIOS Reference Specification (1) section 7.18.5 Memory Device — Extended Size When the size cannot be represented in the size field, it must be set to 0x7fff and the real size stored in the extended_size field. 1: https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.1.pdf Change-Id: Idc559454c16ccd685aaaed0d60f1af69b634ea2e Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-26mb/google/poppy/variants/soraka: Configure unused pins as NCFurquan Shaikh
This change configures unused pins as not connected. Change-Id: I6779d9fba73da8fb2faa08ad5d2236b813105720 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23416 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-26mb/google/poppy/variants/nautilus: Update camera power enable GPIOsFurquan Shaikh
This change updates the camera power enable GPIOs as per the latest schematics. With this update, since one of the enable GPIOs is using a UART0 pin, set UART0 to PchSerialIoSkipInit in devicetree so that FSP-S does not re-configure the UART0 GPIOs. BUG=b:68964831 Change-Id: I5d9126ed8ca2b714f6276f4d3a24c243d7654774 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26mainboard/google/zoombini/variant/meowth: add PCH_WP_ODNick Vaccaro
Configure GPP_H12 as an input for PCH_WP_OD. BUG=b:72202352 BRANCH=none TEST=none Change-Id: Ie5b60644a24d745add4d0d38c1421974b8a0017b Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26soc/amd/stoneyridge: fix compilation errorAaron Durbin
The following two patches were independent, but they were merged together. However, the first one changed the API that the second was originally was written against. Fix build. b94a2750 (i2c/designware: reduce API complication for bus config) 13101a7b (soc/amd/stoneyridge: Add I2C devicetree support) BUG=b:72121803 Change-Id: I3678a8f414572dd2227c42ce5585daf6bc933df5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23445 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-26libpayload: allow x86 devices to provide non-tsc implementationAaron Durbin
Make is so that a different timer source can be provided instead of TSC on x86 platforms. BUG=b:72378235,b:72170796 Change-Id: I6faeecf7624a5aa4e1af8862036f1fbd2f54eb51 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25soc/amd/stoneyridge: remove dependence on TSCAaron Durbin
The TSC rate is empirically swinging during early boot. That leaves timestamps and udelay()s to not be correct. To rectify this stop using TSC for all of these time sources. Instead use the performance TSC which is at a fixed 100MHz clock. That provides stable time sources and legit timestamps. BUG=b:72378235,b:72170796 Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25arch/x86: allow timestamp source to not be TSCAaron Durbin
Some x86 platforms don't have a TSC that is invariant w.r.t. rate to get accurate timestamps. As such a different timestamp is required. Therefore, allow one to specify non-TSC timestamp source and not compile in the default x86 TSC code. BUG=b:72378235,b:72170796 Change-Id: I737fcbba60665b3bc2b5864269536fda78b44d90 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-25cpu/x86: don't utilize UDELAY_IO if GENERIC_UDELAYAaron Durbin
If GENERIC_UDELAY is selected don't try to use UDELAY_IO as there will be a udelay() conflict at link time. BUG=b:72378235,b:72170796 Change-Id: I9e01c9daddd0629ecc38a809889b39a505c0e203 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25lib: include timer.c for all stages for GENERIC_UDELAYAaron Durbin
In order to fully utilize GENERIC_UDELAY in smm and postcar the udelay() implementation needs to be included. Do that. BUG=b:72378235,b:72170796 Change-Id: Ia20c1ed41ee439bb079e00fb7bd9c1855e31e349 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25drivers/i2c/designware: reduce API complication for bus configAaron Durbin
Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement that callback for obtaining the bus config. However, we're currently forcing another parameter of struct device so one can do the lookup. This works for Intel-based systems since the struct device was needed to program the BAR, etc. However, from an API standpoint, it just complicates matters by needing to obtain the struct device. The SoC already has knowlege of its own devices so it can get the config itself by bus number. Therefore, remove that contraint from the API. BUG=b:70232394 Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23420 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25mb/google/kahlee: Add Grunt touchscreen supportJustin TerAvest
This commit adds support for an Elan touchscreen device connected over I2C via devicetree. BUG=b:72121803 TEST=Confirm the device is probed for. Change-Id: Ia9e427dbeab9088f77e3cd751b561f7b9a8cb400 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-25mb/google/kahlee: Add Grunt devicetree i2c bus cfgJustin TerAvest
I2C bus configuration is generally set up in devicetree.cb. This change establishes listings for the buses so that they can be used (though followup changes should update the buses to have correct timings). BUG=b:72121803 Change-Id: I2b12c82d2bab42ab470aa207880be8876e7cb75f Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25mb/google/kahlee: Select DRIVERS_I2C_GENERICJustin TerAvest
This is required to add support for I2C devices on Kahlee to ACPI tables via devicetree.cb. Without this, operations are not emitted for I2C devices and the proper ACPI table entries are not generated. BUG=b:72121803 Change-Id: I1cfe12f3cc23e90ec74b739678f5a5a73257c2c2 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-25soc/amd/stoneyridge: Add I2C devicetree support.Justin TerAvest
This commit establishes the stoneyridge implementation for i2c entries in the devicetree.cb file. BUG=b:72121803 Change-Id: I0d923609bd8fce94c9aee401a5ae2811281b60e5 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25src/amd/stoneyridge: Add devicetree ACPI namesJustin TerAvest
This commit adds device name to ACPI name bindings for various entries in the devicetree. BUG=b:72121803 Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25mb/google/kahlee: Correct grunt HWID in GBBJustin TerAvest
Chrome OS reports that "GRUNT TEST XXXX" is an invalid hwid. The 8296 comes from the lower four numbers from running: $ printf "%d\n" 0x$(crc32 <(echo -n 'GRUNT TEST')) BUG=b:72436450 Change-Id: Ib0044442396cad65c25c107feb35a30a2f70b769 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23411 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-25sconfig: Add a new mmio resource typeJustin TerAvest
Add support for a mmio resource in the devicetree to allow memory-mapped IO addresses to be assigned to given values. AMD platforms perform a significant amount of configuration through these MMIO addresses, including I2C bus configuration. BUG=b:72121803 Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25src/soc/amd/stoneyridge/Kconfig: Use vbios new locationRichard Spiegel
3rdparty/blobs was updated to move northbridge/amd/00670F00 contents into soc/amd/stoneyridge. Now soc/amd/stoneyridge/Kconfig needs to be updated to use VBIOS.bin new location. BUG=b:70785272 TEST=Update 3rdparty/blobs master branch, try to build kahlee. It should fail. Update soc/amd/stoneyridge/Kconfig, try to build kahlee again, it should work (need to rebuild .config first). CQ-DEPEND=CL:881709 Change-Id: I8cb9874eedc4a5d41d42b3f727c6d3cb9b920b5a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-25soc/intel/skylake: Clean up the skylake PCH H device ID macrosV Sowmya
Rename the device ID macros as per the skylake PCH H external design specification. Change-Id: I4e80d41380dc1973d02bc69ac32aad5c4741a976 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23381 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25mb/google/poppy/variants/nami: Disable SATAKane Chen
This change disables SATA controller in order to make SATA IP enter low power status. BUG=b:72332817 TEST=cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status and verify SATA IP enters low power state Change-Id: I72a98bc3d0b47aebc0d7be534f4a7503084b257f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23354 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-25mb/intel/glkrvp: Select SOC_ESPI to enable eSPIShaunak Saha
Add config option SOC_ESPI in glkrvp Kconfig. This is to disable LPC and enable eSPI instead. TEST=Boot to OS Change-Id: I3116b656d41d1d7719c254888d1e3640628a97ca Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-25soc/intel/cannonlake: enable pch link in bootblockCaveh Jalali
This moves the call to pch_enable_lpc() from romstage to bootblock. In other words, it happens earlier in the boot process. Turns out, we need this to talk to the EC to determine if we're in recovery mode or not. BUG=b:69011806 TEST=boots to linux Change-Id: I899bf343d705fe19a2978917bc88990495ebb5a3 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25mainboard/google/zoombini: add ACPI entry for cr50Caveh Jalali
This adds coreboot device tree entries on zoombini & meowth for the cr50. Also, fixes the GPIO pin IRQ settings to be falling edge. This is based on what we do for fizz. BUG=b:71722449 TEST=booted to linux on meowth: tpm_version command now sees the cr50. localhost ~ # tpm_version TPM 2.0 Version Info: Chip Version: 2.0.0.0 Spec Family: 322e3000 Spec Family String: 2.0 Spec Level: 0 Spec Revision: 116 Manufacturer Info: 43524f53 Manufacturer String: CROS Vendor ID: xCG fTPM TPM Model: 00000001 Firmware Version: 0ad551830bcf7a82 localhost ~ # uname -a Linux localhost 4.14.13 #3 SMP PREEMPT Sat Jan 13 02:55:45 PST 2018 x86_64 Genuine Intel(R) CPU 0000 @ 1.00GHz GenuineIntel GNU/Linux localhost ~ # and we see interrupts when talking to the cr50: localhost ~ # grep cr50 /proc/interrupts ; tpm_version ; grep cr50 /proc/interru pts 84: 4687 IO-APIC 84-edge cr50_spi TPM 2.0 Version Info: Chip Version: 2.0.0.0 Spec Family: 322e3000 Spec Family String: 2.0 Spec Level: 0 Spec Revision: 116 Manufacturer Info: 43524f53 Manufacturer String: CROS Vendor ID: xCG fTPM TPM Model: 00000001 Firmware Version: 0ad551830bcf7a82 84: 4799 IO-APIC 84-edge cr50_spi localhost ~ # Change-Id: I9d503334502503ef49515e4a8736d967bc454a98 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-01-25mb/google/poppy/variants/nami: Enable elan touchpad wakeup system from S3/S0ixVan Chen
BUG=b:71839089 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. powerd_dbus_suspend 3. touch touchpad to wakeup system 4. localhost ~ # cat /var/log/eventlog.txt | 2018-01-21 17:01:59 | S0ix Enter | 2018-01-21 17:02:04 | S0ix Exit | 2018-01-21 17:02:04 | Wake Source | GPIO | 80 Change-Id: Ie550cfa3f7b5fd105f89c16076d428743392d0e4 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23363 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-25soc/intel/skylake: Send correct ddr_type to SMBIOS TableBarnali Sarkar
The FSP 2.0 Memory_Info_HOB for KBL is not sending "MemoryType" value as what is required for SMBIOS Table according to SMBIOS Spec. Thus, converting the value retrieved from FSP HOB to the correct value. This change will not be required for upcoming SOCs since FSP have fixed this issue in its next platforms and thus it will take care and send the correct value in "MemoryType" field based on SMBIOS spec. Thus this conversion from coreboot will not be required in the next platfoms. "MemoryType" value can be directly passed to dimm_info_fill() function. BUG=none BRANCH=none TEST=Tested in Soraka, and getting the value as 0x1D for LPDDR3 memory. dmidecode (latest version 3.1) Command Type 17 will also show correct information. Currently, it was showing "Unknown". Change-Id: I75d6cca464680a88bf836e25bf5440a9cdbc738e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/23384 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-24payloads/nvramcui/payload.sh: Fix shellcheck warningsMartin Roth
In payloads/nvramcui/payload.sh line 5: DIR=`dirname $0` ^-- SC2006: Use $(..) instead of deprecated `..` ^-- SC2086: Double quote to prevent globbing and word \ splitting. In payloads/nvramcui/payload.sh line 6: lpgcc -o $DIR/nvramcui.elf $DIR/nvramcui.c 2>&1 >/dev/null || exit 1 ^-- SC2086: Double quote to prevent globbing and word \ splitting. ^-- SC2086: Double quote to prevent \ globbing and word splitting. ^-- SC2069: The order of \ of the 2>&1 and the \ redirect matters. The \ 2>&1 has to be last. Change-Id: Iceab2d0df49c642f54e6b911793aa1479f542644 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-24soc/amd/stoneyridge/spi: do not open code existing CAR APIsAaron Durbin
The CAR APIs already exist to deal with proper type useage. Don't open code things that already exist. BUG=b:65485690 Change-Id: I09593401513f6060a30cf5c02c94d14afbe8f4fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 19:50:18 +0000