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2016-09-23mainboard/nvidia/l1_2pvv: Use tabs for indentsElyes HAOUAS
Change-Id: I4171e9bbf14c9aa65f698feabd78aa8fbf2a105f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16687 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-22soc/intel/apollolake: Initialize processor count in GNVSDuncan Laurie
Initialize the PCNT variable in GNVS so it is available to ACPI code that expects to know the number of CPUs. Change-Id: I7a6e003ac94218061bf98e8883ed2c62d856af8d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-22Build system: Remove IASL_WARNINGS_ARE_ERRORS optionMartin Roth
All systems are building with IASL warnings as errors enabled. Remove the option to disable it. Remove the notification at the end of the build. Change-Id: I5c6218c182fdf173b4026fd010d939a5fa36040e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16606 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21buildgcc: Build gnat by default if host compiler seems compatibleNico Huber
Change-Id: I2a13e188ddb0b7d64d3c0ec979a1a493bf160afc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16678 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21buildgcc: Ask the user to install gnat if it's missingNico Huber
Change-Id: Ib840eac29fc8cedfaef4847fd9700bd4a70300ba Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16677 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21buildgcc: Don't try to build gnat with a different versionNico Huber
Change-Id: I64a33d2cc4793e54a50fa439a4461c40d424b569 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16676 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-21buildgcc: Warn when building GCC with a different major versionNico Huber
GCC build instruction recommend to bootstrap a native compiler first. Not sure, when that is really necessary. A major version change seems reasonable. Change-Id: I80a9ec25739b7d33a1d1c7b4b2140d19d89a99ae Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21buildgcc: Add functions to test GCC versionsNico Huber
Just add some helpers that show parts (major, major.minor) of the GCC version to be built (buildcc_*) and of the host compiler (hostcc_*). They will be used in follow-up commits. Change-Id: I37c12ad1a2d08645f40a9f0f0a479c8d7cc3e127 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16674 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-21buildgcc: Show excessive arguments and bail outNico Huber
Also remove a dead line that checks for unknown options: We already let `getopt` check that. Change-Id: I0e829b266e192757d6e455ee4cc608315bb4b7be Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16681 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21buildgcc: Check exit status of `getopt`Nico Huber
We accidentally checked the status of `eval` instead. Change-Id: I1ba258944184ed707ed1f176e528d8266656cb59 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21buildgcc: Fix GNU getopt usageNico Huber
Looks like this never worked correctly: There are three argument formats to GNU getopt and none of them matches what we fed it. The missing double dash before the `set` arguments proves that we always called it with parameters that `getopt` did NOT parse. Change-Id: Ib8343976ef31774b18567a9fc9745a9f58dd287a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16679 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-21buildgcc: Fix option argumentsNico Huber
As we support `getopt` versions that don't know long options, every option arguments needs a short option. Also add the long options `--urls` and `--nocolor` to the `getopt` string. Change-Id: I11c393c3d90c7a16cdda119594221c85f902ed40 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16682 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-21northbridge/amdk8: Improve code formattingElyes HAOUAS
Change-Id: I1c2786dfb166904ff8b19a663c5e2e8156b7aedf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16644 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-21northbridge/amd/amdmct: Improve code formattingElyes HAOUAS
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21google/enguarde: Adapt to current treePatrick Georgi
Some changes were made in upstream in the meantime that broke the build: - CHROMEOS_VBNV_CMOS was renamed to VBOOT_VBNV_CMOS - recovery_move_enabled() -> vboot_recovery_mode_enabled() - chromeos.asl was replaced by an acpi generator Change-Id: Icd4ed5111cce9db79e12efb0cb7e898bba725c20 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16683 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-21inteltool: add --ahci for printing AHCI registersIru Cai
According to datasheets for Intel ICH/PCH, it works for chipsets from ICH7 to 9-series PCH, with PCI device address D31:F2. Change-Id: If1ddd7208108bda949b5a94894a7bf9e8bfe1e5f Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/15106 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21google/enguarde: Upstream Lenovo N21 ChromebookMatt DeVillier
Migrate google/enguarde (Lenovo N21 Chromebook) from Chromium tree to upstream, using google/rambi as a reference. original source: branch firmware-enguarde-5216.201.B commit cf1f57b [Enguarde: Adjust rx delay for norm.] TEST=built and booted Linux on enguarde with full functionality blobs required for working image: VGA BIOS (vgabios.bin) firmware descriptor (ifd.bin) Intel ME firmware (me.bin) MRC (mrc.elf) external reference code (refcode.elf) Change-Id: I3ccda29d1e095d8b1b36766cda913172f72233a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/15444 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21southbridge/sis/sis966/aza.c: Improve code formattingElyes HAOUAS
Change-Id: If5342a2b5bae18b70ea671522efd2691bc9872dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16602 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21northbridge/amd: Improve code formattingElyes HAOUAS
Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21soc/apollolake: Correct the comment section in gpio.aslShaunak Saha
This patch corrects the comment section in gpio.asl for GPE method. Change-Id: I45771a295ee1eda00b9699f42cddd120223ff7bf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16647 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21mainboard/google/reef: Enable cr50 TPM interruptDuncan Laurie
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16673 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Support interrupts for statusDuncan Laurie
Support reading the ACPI GPE status (on x86) to determine when the cr50 is ready to return response data or is done processing written data. If the interrupt is not defined by Kconfig then it will continue to use the safe delay. This was tested with reef hardware and a modified cr50 image that generates interrupts at the intended points. BUG=chrome-os-partner:53336 Change-Id: Ic8f805159650c45382cacac8840450a1f8b4d7a1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16672 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21soc/intel/apollolake: Add function to read and clear GPE statusDuncan Laurie
Implement the generic acpi_get_gpe() function to read and clear the GPE status for a specific GPE. Tested by watching GPE status in a loop while generating interrupts manually from the EC console. BUG=chrome-os-partner:53336 Change-Id: I482ff52051a48441333b573f1cd0fa7f7579a6ab Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16671 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21soc/intel/apollolake: Initialize GPEs in bootblockDuncan Laurie
Initialize the GPEs from mainboard config in bootblock, so they can be used in verstage to query latched interrupt status. I still left it called in ramstage just to be sure that the configuration was not overwritten in FSP stages. Tested by reading and reporting GPE status in a loop in verstage and manually triggering an interrupt on EC console. BUG=chrome-os-partner:53336 Change-Id: Iacd0483e4b3229aca602bb5bb40586eedf35a6ea Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16670 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21x86: acpi: Add function for querying GPE statusDuncan Laurie
Add a function that can be implemented by the SOC to read and clear the status of a single GPE. This can be used during firmware to poll for interrupt status. BUG=chrome-os-partner:53336 Change-Id: I551276f36ff0d2eb5b5ea13f019cdf4a3c749a09 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16669 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Improve data handling and function namesDuncan Laurie
Unify the function names to be consistent throughout the driver and improve the handling while waiting for data available and data expected flags from the TPM. BUG=chrome-os-partner:53336 Change-Id: Ie2dfb7ede1bcda0e77070df945c47c1428115907 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16668 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Clean up locality functionsDuncan Laurie
Clean up the mask and timeout handling in the locality functions that were copied from the original driver. BUG=chrome-os-partner:53336 Change-Id: Ifdcb3be0036b2c02bfbd1bcd326e9519d3726ee0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16667 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Rename i2c read/write functionsDuncan Laurie
Rename the low-level functions from iic_tpm_read/write to cr50_i2c_read/write to better match the driver name, and pass in the tpm_chip structure to the low-level read/write functions as it will be needed in future changes. BUG=chrome-os-partner:53336 Change-Id: I826a7f024f8d137453af86ba920e0a3a734f7349 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16666 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Clean up timeoutsDuncan Laurie
Use two different timeouts in the driver. The 2ms timeout is needed to be safe for cr50 to cover the extended timeout that is seen with some commands. The other at 2 seconds which is a TPM spec timeout. BUG=chrome-os-partner:53336 Change-Id: Ia396fc48b8fe6e56e7071db9d74561de02b5b50e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16665 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Reduce max buffer sizeDuncan Laurie
Reduce the static buffer size from the generic default 1260 down to 64 to match the max FIFO size for the cr50 hardware and reduce the footprint of the driver. BUG=chrome-os-partner:53336 Change-Id: I6f9f71d501b60299edad4b16cc553a85391a1866 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16664 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm: Split cr50 driver from main driverDuncan Laurie
Originally I thought it would be cleaner to keep this code in one place, but as things continue to diverge it ends up being easier to split this into its own driver. This way the different drivers in coreboot, depthcharge, and the kernel, can all be standalone and if one is changed it is easier to modify the others. This change splits out the cr50 driver and brings along the basic elements from the existing driver with no real change in functionality. The following commits will modify the code to make it consistent so it can all be shared with depthcharge and the linux kernel drivers. BUG=chrome-os-partner:53336 Change-Id: I3b62b680773d23cc5a7d2217b9754c6c28bccfa7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm: Move common variables to headerDuncan Laurie
Move the common enums and variables to tpm.h so it can be used by multiple drivers. BUG=chrome-os-partner:53336 Change-Id: Ie749f13562be753293448fee2c2d643797bf8049 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16662 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21Makefiles: update cbfs types from bare numbers to valuesMartin Roth
These values are found in util/cbfstool/cbfs.h. Change-Id: Iea4807b272c0309ac3283e5a3f5e135da6c5eb66 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16646 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20buildgcc: Update to acpica version 20160831Martin Roth
Change-Id: I3e3973e1c47505718cf73435156104ab73680441 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16387 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20Makefile.inc: Add aliases for submodule updates to gitconfig targetMartin Roth
Updating submodules seem to give people headaches, so this adds a pair of git aliases to update them. 'git sup' updates the submodules to the latest versions, but leaves any locally modified files. 'git sup-destroy' will remove the current submodules and re-initialize them. This deletes any local changes. Change-Id: Id62a30d88b3b6d285b3f00555d7609509aa1561f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16573 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/lenovo-winent: Add space around operatorsElyes HAOUAS
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/getac - kontron: Add space around operatorsElyes HAOUAS
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/amd/amdfam10: Improve code formattingElyes HAOUAS
Change-Id: I86a252598666af635281eaa467020acb53d71c77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20selfboot: Move the usable-RAM check into a functionSimon Glass
In preparation for making this check optional, move it into its own function. load_self_segments() is already long and we don't want to make it longer. BUG=chrome-os-partner:56314 BRANCH=none TEST=boot on gru and see that BL31 loads and runs correctly Change-Id: If48d2bf485a23f21c5599670e77a7b8b098f1a88 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 2381e02efa2033857ac06acbc4f0c0dd08de1080 Original-Change-Id: I005e5e4d9b2136605bdd95e9060655df7a8238cb Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381092 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16585 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-20arm_tf: Fix code style nits and commentsSimon Glass
Tidy up a few things which look incorrect in this file. BUG=chrome-os-partner:56314 BRANCH=none TEST=build for gru Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 434e9ceb5fce69b28de577cdc3541a439871f5ed Original-Change-Id: Ida7a62ced953107c8e1723003bcb470c81de4c2f Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376848 Original-Commit-Ready: Simon Glass <sjg@google.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Change-Id: If8c283fe8513e6120de2fd52eab539096a4e0c9b Reviewed-on: https://review.coreboot.org/16584 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20gru/kevin: Decrease voltage for little cpu 1.5G to 1.15vShunqian Zheng
In kernel side we set 1.1v for 1.5G, even for coreboot RO, a higher voltage could be safer, 1.2v now seems too high. BRANCH=none BUG=chrome-os-partner:56948 TEST=bootup Change-Id: I852e0d532369aad51b12770e2efb01aacf6662ce Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 000b5c099373be2a1f83c020ba23a0e79ea78fab Original-Change-Id: Iecc620deee553c61a330353ac160aa3a36f516df Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380896 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16583 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20rockchip: spi: Improve SPI read efficiencySimon Glass
The SPI driver is quite slow at reading data. For example, with a 24MHz clock on gru it achieves a read speed of only 13.9Mbps. We can correct this by reading the status registers once, then reading as many bytes as are available before checking the status registers again. It seems likely that a status register read requires synchronizing with the SPI FIFO clock domain, which takes a while. BUG=chrome-os-partner:56556 BRANCH=none TEST=run on gru and see the speed increase from 13.920 Mbps to 24.712 Mbps Change-Id: I24aed0c9c6c5445634c4e056922afaee4e9a7b33 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 49c2fc20d7d7d703763e9b0a6f68313a349a84b9 Original-Change-Id: I42745f01f0fe069f6ae26d866004d36bb257e6b2 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376945 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20Veyron: Increase bit-per-pixel to 32Daisuke Nojiri
This enhances gradation of some icons on vboot screens. BUG=chrome-os-partner:56056 BRANCH=none TEST=Booted Jerry Change-Id: Ia19d585b69e7701040209e8bf0b8a6990a166c95 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4e7a42c999673ebd89c5b30845a4a5ec93852166 Original-Change-Id: I126cb7077c834e1a8b0a625a592dce8789b5876c Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376884 Reviewed-on: https://review.coreboot.org/16581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20google/gru: Fix up PWM regulator rangesJulius Werner
We did yet another small adjustment to the PWM regulator ranges for Kevin rev6... this patch reflects that in code. Also rewrite code and descriptions to indicate that these new ranges are not just for Kevin, but also planned to be used on Gru rev2 and any future Gru derivatives (which as I understand it is the plan, right?). BRANCH=None BUG=chrome-os-partner:54888 TEST=Booted my rev5, for whatever that's worth... Change-Id: Id78501453814d0257ee86a05f6dbd6118b719309 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4e8be3f09ac16c1c9782dee634e5704e0bd6c7f9 Original-Change-Id: I723dc09b9711c7c6d2b3402d012198438309a8ff Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/379921 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16580 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20Gru: Increase bit-per-pixel to 32Daisuke Nojiri
This enhances gradation of some icons on vboot screens. BUG=chrome-os-partner:56056 BRANCH=none TEST=Booted kevin-tpm2 Change-Id: I2fc943f89386ccc6cd9293f5811182a5a51d99b0 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: bb1f0fb00d023c045305edc6c9fc655b764a4e8c Original-Change-Id: Ieb61830b9555da232936087cdcf7c61a1e55bab4 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376883 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16579 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20gru: Add watchdog reset supportJulius Werner
This patch adds support to reboot the whole board after a hardware watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to Veyron. From my tests it looks like both SRAM and PMUSRAM get preserved across warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that makes it easier to deal with in coreboot (PMUSRAM is currently not mapped as cached, so we don't need to worry about flushing the results back before reboot). BRANCH=None BUG=chrome-os-partner:56600 TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30 seconds. Confirm that system reboots correctly without entering recovery and we get a HW watchdog event in the eventlog. Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098 Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/375562 Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16578 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20vboot/vbnv_flash: Binary search to find last used entryRandall Spangler
This improves the previous linear search to O(log n). No change in storage format. BUG=chromium:640656 BRANCH=none TEST=Manual (test empty) flashrom -i RW_NVRAM -e Reboot; device should boot normally. (start using records) crossystem kern_nv=0xaab0 crossystem recovery_request=1 && reboot Device should go into recovery mode with reason 1 Reboot again; it should boot normally. crossystem kern_nv (should still contain 0xaab0) Repeat steps several times with request=2, 3, etc. flashrom -i RW_NVRAM -r nvdata Modify nvdata to copy the first record across all valid records flashrom -i RW_NVRAM -w nvdata Reboot; device should boot normally. Change-Id: Ieb97563ab92bd1d18a4f6a9e1d20157efe311fb4 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: db9bb2d3927ad57270d7acfd42cf0652102993b1 Original-Change-Id: I1eb5fd9fa6b2ae56833f024bcd3c250147bcc7a1 Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376928 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16577 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20checkpatch.pl: ignore '#define asmlinkage'Martin Roth
checkpatch warns that the asmlinkage storage class should be at the beginning of the declaration when we define it to be an empty value. Change-Id: I12292d5b42bf6da9130bb969ebe00fca8efcf049 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16358 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20lint/lint-007-checkpatch: Update lint scriptMartin Roth
- Check Kconfig files as well. - Accept a list of directories to check as a command line argument. - Only look at src & util directories by default. - Skip src/vendorcode. - Remove bypass of payloads/coreinfo/util/kconfig directory, it no longer exists. Change-Id: Ia522d3ddc29914220bdaae36ea23ded7338c48fd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16359 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/via: Add space around operatorsElyes HAOUAS
Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16623 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 22:02:26 +0000