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2017-07-01mb/google/eve: Set TOUCHSCREEN_STOP_L GPIO to inputDuncan Laurie
Make this pin a GPI as it is supposed to be an input from the touch controller and not driven by the AP. BUG=b:35581264 TEST=check pin state with a scope Change-Id: Ife5f84fcc614255b20e44389279d515a12f5751d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-01mb/google/eve: Do not limit memory speed on new SKU 5 boardsDuncan Laurie
Board changes in rev6+ have a fix to VDDQ that should fix the issue that was being seen with this SKU, so only lower the memory speed on older boards. BUG=b:37172778 TEST=memory stress testing on rev6 boards Change-Id: I6d6fe730cabd74af23eab3f02feef9da01a35fd4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-01mb/google/eve: Implement EC device events for S3 wakeDuncan Laurie
Add support for waking from and logging device events that originate in the Embedded Controller. As this device uses Deep S3 it relies on the EC to wake the AP from the trackpad and DSP wake sources. BUG=b:30624430 TEST=manual testing on Eve: wake from Deep S3 via trackpad and DSP and verify the event log contains the expected device event. Change-Id: I0d6a9c5bfd4cea85e13446ffaa6fe3dab0db96a2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-01ec/google/chromeec: Add support for EC device eventsDuncan Laurie
Add support for the new EC device event interface which is used to report events from devices that are connected behind the EC. This can be used to differentiate wake sources from the EC in the case that the EC has the wake pins from various devices. This can be used in case the AP is unable to directly wake from the device itself, for example when using the Deep S3 state on Intel platforms only a few pins can directly wake the AP. BUG=b:30624430 TEST=build google/* boards that use chrome EC. Feature is used and tested further in a subsequent commit. Change-Id: I5126c6d6ffb6b0ef6e8db8dcd5aec62db925a371 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-01elog: Update for EC Device EventsDuncan Laurie
Replace the unused "thermal overload" event with the new "device event" and define the first few device events that are supported by the Chromium EC. BUG=b:30624430 TEST=build for google/* mainboards Change-Id: I1f3aeedb87c2aad29a0a67b5c50c29a6961fb45f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-01ec/google/chromeec: Sync header with Chromium EC codebaseDuncan Laurie
Update this header from the upstream source so new host commands can be used in coreboot. https://chromium.googlesource.com/chromiumos/platform/ec commit bbb759ceaa843f548f90c35d1668e17c8879bad3 BUG=b:30624430 TEST=build google/* and intel* boards Change-Id: I56c9f891262d8984b6a9a69d96752c2dd6bb2371 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-01mainboards: Remove unused EC event for thermal overloadDuncan Laurie
The Chrome EC event for "thermal overload" was never implemented and is being repurposed as the EC event mask is out of free bits. Remove this from the boards that were enabling it. BUG=b:36024430 TEST=build coreboot for affected boards Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-01Makefile: Update clean targetsMartin Roth
- Clean utilities directories on clean & distclean - Have the distclean target clean up after 'what-jenkins-does' Change-Id: I7d25d8234528b19bf36df6845a4500dbe1cbf9a4 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/19000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-01riscv: Update the gcc built-in macro __riscv__wxjstz
The architecture is determined by __riscv__ in the LZ4_copy8 function (located in src / commonlib / lz4_wrapper.c). __riscv exists in gcc7.1.1. But __riscv__ does not exist. Change-Id: I38fd41da9afd76c254f0c3d6984579c3790e5792 Signed-off-by: XiangWang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/20125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Waterman <aswaterman@gmail.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-07-01nb/intel/i945/gma.c: Remove redefined "DISPPLANE_BGRX888"Elyes HAOUAS
DISPPLANE_BGRX888 defined in drivers/intel/gma/i915_reg.h included in i915.h file Change-Id: I4e9414f39a29e4eac7e325672ce6520a5654d3bc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-07-01nb/intel/i945/gma.c: Add whitespace around '<<'Elyes HAOUAS
Change-Id: Ic01bbae9acaabaade777db52825aa80d25fc5961 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-06-30mb/siemens/mc_apl1: Set up RTC backup mode to primary cellWerner Zeh
Set RX6110SA RTC backup mode to primary cell. This mode reduces the backup current consumption of the RTC. Change-Id: I7c0c26a0ed5d8f48587acc917f8bb1c5c2b8869a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-30mb/siemens/mc_bdx1: Set up RTC backup mode to primary cellWerner Zeh
The used RTC6110SA has issues to enter backup mode when the power supply decreases too slow when the mainboard is turned off. Switch to backup mode "primary cell" to make sure backup mode will be entered correctly on power-off. In addition set IOCUTEN to minimize the backup current consumption of the RTC. Change-Id: I9733aa9f2981a25f6d42279eff0c4980e5eb5a5a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-30rx6110sa: Add a software reset sequence in case of power lossWerner Zeh
According to the datasheet the RTC needs a power rising slope of no more than 100µs/V to ensure a correct power-on reset. If the mainboard that hosts the RTC cannot guarantee this, a software reset sequence is needed in the case where the battery was drained completely. As the rising slope of the power supply depends on so many parameters and is highly mainboard specific, refactor the initialization code to perform a software reset every time a power loss event is recognized by the RTC. Change-Id: If64d672e51667523058041bd00e1e50ac047143d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-30southbridge/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-06-29lib/spd_bin: Use proper I2C addressesNico Huber
Use the plain address instead of the weird shifted encoding (e.g. if we'd use `0xa0` as address, it's actually `0x50` encoded into a write command). Change-Id: I6febb2e04e1c6de4294dfa37bde16b147a80b7a8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-29soc/intel/skylake/Kconfig: Drop useless FSP1.1/2.0 promptsNico Huber
There is no choice, if not leaving it with the default the build will fail. Change-Id: Id91e3ce87f8ced3001fcd2125f8f6781b270f5bc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29soc/intel/cannonlake: Add UART initializationAndrey Petrov
Cannonlake has built-in UART driver as part of LPSS block. However port mapped decoders are in use as well. Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29arch/x86: update assembly to ensure 16-byte alignment into CAaron Durbin
When the C compiler expects 16-byte alignment of the stack it is at the call instruction. Correct existing call points from assembly to ensure the stacks are aligned to 16 bytes at the call instruction. Change-Id: Icadd7a1f9284e92aecd99c30cb2acb307823682c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-29soc/intel/common/block/gpio: Port gpio code from Apollolake to commonHannah Williams
Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29soc/intel/cannonlake: Add initial dummy directoryLijian Zhao
Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29soc/amd/stoneyridge: Convert monotonic timerMarshall Dawson
Use the TSC for the Stoney Ridge monotonic timer. Modern AMD CPUs have invariant timestamp counters. This patch brings the feature more in line with other devices and allows the use of typical monotonic timer functions. BUG=chrome-os-partner:62578062 Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-29util/abuild: Update abuildMartin Roth
- Improve logging - Add location of logfiles to failed board log. - Log when the shared utilities fail to build. - Log passing configs and print count of tested configs that passed. - Disable a couple of shellcheck warnings. - Remove some unused code. Change-Id: Ic2cf1c0a5f123d759aac7ce55092ad71314a8c9d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-29util/lint: Update checkpatch & files to upstream linuxMartin Roth
- Update checkpatch.pl to version 522b837 (checkpatch: warn when formats use %Z and suggest %z) - This update moves the const_struct definitions into an external file. coreboot will want to update this file, but for now I'm just pulling it in directly from the linux tree. - Update spelling.txt used by checkpatch.pl to version 505d308 (scripts/spelling.txt: add "overide" pattern and fix typo instances) - Add better notes where things have been changed for coreboot to make future merges easier. Change-Id: I0ef067874fe7b1d23276a10e63858895d6083f69 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-29mb/siemens/mc_bdx1: Set bus master bit for on-board PCI devicesWerner Zeh
There are up to two on-board PCI devices where bus master has to be enabled in PCI config space. As there is no need for a complete PCI driver for these devices just set the bus master bit in mainboard_final(). In a perfect world that would be the task of the runtime driver which unfortunately don't do that. Change-Id: Ic2896d5e7568a455737af26b14b2c398caae5f72 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-29nb/haswell: set ASLB gnvs to OpRegion ACPI memory addressMatt DeVillier
The ALSB gnvs variable is used to load the OpRegion memory address into the ASLS register on the S3 resume path, and must therefore first be set on the normal boot path. This patch brings Haswell in line with SNB/IVB/Nehalem, which already save the OpRegion address in ASLB. Change-Id: Ie062cbfe7e7f60c2a4e2b9111f6b6da87ced7a39 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-06-28soc/amd/stoneyridge: Revise pci_devs.h fileMarshall Dawson
Now that pci_devs.h is part of soc/ and not used for multiple southbridges: * Remove devices not present in the Stoney Ridge APU * Complete the list to include additional devices besides those in the FCH. BUG=chrome-os-partner:62578372 Change-Id: I1cd2d5e41473f362bbfd28ee93788a292bc33991 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20370 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28soc/amd/stoneyridge: Fix device IDsMarshall Dawson
Update pci_devs.h to the correct IDs for Stoney Ridge. BUG=chrome-os-partner:62578372 Change-Id: Ic1a7fe8d95c34b80e21cc089168732372d9690a3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20200 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28amd/family15h: Add defines for boost and P-stateMarshall Dawson
Add definitions for the P-state 0 MSR and Core Performance Boost Control. BUG=chrome-os-partner:62578062 Change-Id: I0c16dde17f1be41a3310c3ccefe3936aba0e8ec0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28soc/amd/stoneyridge: Enable early cbmemMarshall Dawson
Add a memmap file with a cbmem_top() function. Remove the LATE_CBMEM_INIT, allowing the default of EARLY. Remove calls to the late-only set_top_of_ram() function. Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28amd/gardenia: Init cbmem in romstageMarshall Dawson
Change-Id: I6ede71ec660678bb5f77693a9095aa0f198e4e26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28src/ec: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: Ic2cdfa08cdae9f698eb2f8fa4c4ae061f1a7d903 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-28src/device: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I66cde1adcf373889b03f144793c0b4f46d21ca31 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28device/oprom/yabel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I82bf68a7ee54ff88f65aacc9eb0dbc30d013aae0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28cpu/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28cpu/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I9f4155285529ec28e826637a61436478f648704c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28mainboard/google/fizz: Add audio devicesKevin Cheng
- Describe RT5663 headphone codec in ACPI so it can be enumerated by the OS. - Supply NHLT binaries for RT5663 BUG=b:62872377 TEST=Apply full patch set and UCM, verify basic audio works. Signed-off-by: Kevin Cheng <kevin.cheng@intel.com> Change-Id: I5bbd58b0e660cdf5089e6a6dd35a757ecf8ec076 Reviewed-on: https://review.coreboot.org/20305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-28libpayload: Add mouse cursor driverPatrick Rudolph
Add a driver to handle multiple low level mouse drivers and provide basic cursor acceleration support. Tested on Lenovo T500. Change-Id: Ib7cec736631b8acf81a14d28daa29ff720777b10 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28nb/amdk8/debug.c Fix building with CONFIG_DEBUG_SMBUSArthur Heymans
Problem was introduced by fb2f667da2 "nb/amd/amdk8: Link raminit_f.c" which linked debug.c and was not tested with this option. Change-Id: I8597a6915c65ea783a864110cb23ecb34ea0611b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Swift Geek <swiftgeek@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28util/superiotool: Check for libpci before builingArthur Heymans
Check is adapted from inteltool's Makefile. Change-Id: Ife01ef20d9284cb0a68719757856f9a66a4de452 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28cpu/intel/pineview: Include speedstepArthur Heymans
Needed to generate cpu entries. Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28northbridge/amd/agesa/*: Add whitespace around '<<'Elyes HAOUAS
Change-Id: I56cb941d07ac48f8209a892ec18af8f5090765f7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28cpu/*: Add whitespace around '<<'Elyes HAOUAS
Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28payloads: Add whitespace around '<<'Elyes HAOUAS
Change-Id: I0659f6ec59fb808b4cedf57d60d737c13c250042 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20396 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27clang: Allow initializer overridesStefan Reinauer
In the code we do the following in a number of places to pre-initialize an array with a certain value before overwriting some of the array with other values: u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F, } clang does not like that behavior unless we specify the option -Wno-initializer-overrides. Remove the check for gcc in those places, too, because 1) it would silently change array contents between compilers 2) the check isn't sufficient to determine compilation on clang vs gcc Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I93cc121b6fec099fcdbd5fd1114c2ff7cbc291dc Reviewed-on: https://review.coreboot.org/20384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27xcompile: silence clang when referencing packed structs' membersPatrick Georgi
clang complains that the access might be unaligned. Yes, we know. Yes, that's exactly what we want. You have _one_ job. Change-Id: I5400f50d8b5b462270c700f7ff90d9d517278e71 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/19659 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-27sis/sis966: Clean up sata.cStefan Reinauer
Wow, this one is disliked by clang for the empty for() loop, but looking at the file just makes my eyes bleed a little bit. I remember the circumstances under which we let this code go in. It was supposed to save contributions from a vendor, but that never worked out. Just to keep the little chunks down, here's an indent run and some of the cruft removed that doesn't actually contribute to functionality in any way. Change-Id: Ie82166ca82f09c4b66decfde5ad194a2d70b0708 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27commonlib/storage: Zero extend MMC capacityLee Leahy
Fix CID 1376472 detected by coverity. Zero extend the capacity instead of sign extending it. TEST=Build and run on reef Change-Id: I6aac422fb1dacb75e0cc44a94ff1f467ce9f529e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27xcompile: Also try clang variants under the $triplet-clang schemePatrick Georgi
That seems to be the more reliable way to build clang cross compilers for now. Change-Id: I14fe767d20f91b64e96c909291760bddcd108e5c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/19660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27soc/amd/stoneyridge: Add tseg size to KconfigMarshall Dawson
Add a SMM_TSEG_SIZE symbol that can be used in top of memory calculations. Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19750 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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