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2020-04-28drivers/ipmi: Add uid parameter to struct drivers_ipmi_configFurquan Shaikh
This change adds uid parameter to drivers_ipmi_config that can be used by ipmi_ssdt() to store the uid value to be used by ipmi_write_acpi_tables. This allows to remove the requirement in ipmi_ssdt() to update dev->command. This is being done in preparation to make the struct device * parameter to fill_ssdt as const. Change-Id: Ieb41771c75aae902191bba5d220796e6c343f8e0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40705 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28i2c/designware: Constify struct device * parameter to dw_i2c_soc_dev_to_busFurquan Shaikh
dw_i2c_soc_dev_to_bus() does not need to modify the device structure. Thus, this change makes the struct device * parameter to dw_i2c_soc_dev_to_bus as const. Change-Id: Ibf5c8d8127dff2ab2ccbd1f6b4f553e98e81955f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40704 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to dev_nameFurquan Shaikh
dev_name() does not need to modify the device structure. Hence, this change makes the struct device * parameter to dev_name() as const. Change-Id: I6a94394385e45fd76f68218bf57914bddd2e2121 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40703 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28arch/x86/acpi_device: Constify struct device * parameter to UID functionsFurquan Shaikh
acpi_device_uid() and acpi_device_write_uid() do not need to make changes to the device structure. Thus, this change marks struct device * parameter to these functions as const. Change-Id: I3755223766c78f93c57ac80caf392985cfd5c5e5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40702 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28soc/amd/{common,picasso}: Move GFX device from static ASL to SSDTFurquan Shaikh
This change: 1. Adds PCI device for graphics controller in ACPI SSDT tables using acpi_device_write_pci_dev(). 2. Gets rid of IGFX device from picasso acpi/northbridge.asl. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769 Change-Id: I3a967cdc43b74f786e645d3fb666506070851a99 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28soc/amd/picasso: Use common block graphics driverFurquan Shaikh
This change selects common block graphics driver for Picasso and also adds PCI ID for Family 17h graphics controller to the graphics driver. Since the common driver provides .acpi_name() callback for graphics device, soc_acpi_name() no longer needs to provide the ACPI name for graphics device. BUG=b:153858769 Change-Id: Id3ffcb05d8f8a253a0b27407d52d7907c507cabb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28soc/amd/common: Add a common graphics block device driver for AMD SoCsFurquan Shaikh
This change adds a common graphics block device driver for AMD SoCs. In follow-up CLs, this driver will be utilized for Picasso. This driver is added to enable ACPI name and SSDT generation for graphics controller. BUG=b:153858769 Change-Id: I45e2b98fede41e49158d9ff9f93785a34c392c22 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28amd/family17h: Add PCI device IDs for all controllers in AMD Family17hFurquan Shaikh
This change adds all the missing PCI device IDs for AMD Family 17h. IDs that were already present are updated to include _FAM17H_ in the name instead of _PCO_ and _DALI_. This ensures that the PCI IDs match the family and models as per the PPR. In cases where the controller is present only on certain models, _MODEL##H_ is also included in the name. BUG=b:153858769 BRANCH=None TEST=Verified that trembyle and dalboz still build. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia767d32ec22f5e58827e7531c0d3d3bac90d3425 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28soc/amd: Update macro name for IOMMU on AMD Family 17hFurquan Shaikh
IOMMU for AMD Family 17h Model 10-20h uses the same PCI device ID 0x15D1. This change updates the name to indicate that the PCI device ID is supported for FP5(Model 18h) and FT5(Model 20h). BUG=b:153858769 BRANCH=None TEST=Trembyle and dalboz still build. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I17c782000ed525075a3e438ed820a22d9af61a26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28arch/x86/acpi_device: Add a helper function to write PCI deviceFurquan Shaikh
This change adds a helper function to write a PCI device with _ADR and _STA defined for it. BUG=b:153858769 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I932af917d91198876fe8e90af9bb7a2531bd8960 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40674 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/deltaur: Disable POWER_OFF_ON_CR50_UPDATEEric Lai
This is missing configuration of Wiloc projects. Following Wilco projects configuration. CB:32436 The power architecture on this platform is different than most of our other x86 devices and needs some special handling to ensure it powers up again after an EC reset. BUG=b:150165131 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I6da89de9401793a4e5c56a23c1018527819718cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40663 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/deltaur: Change H1 I2C speed to STANDARDEric Lai
Currently, Deltaur’s I2C speed has not been tuned yet, so slow down the H1 I2C to avoid I2C error for short term. Error logs: Reading cr50 TPM mode I2C receive timeout I2C read failed: bus 3 addr 0x50 BUG=b:154310066 TEST=Check H1 has no I2C error occurring and can be updated by gsctool. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I85a63c1ab9a51d254873377a36d56823af11f0a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40644 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/deltaur: Enable PS/2 keyboardEric Lai
By default, the ACPI status method _STA returns false for the PS/2 keyboard and mouse device of the Wilco EC, so the OS does not enable it. Enable these devices, by defining the macro SIO_EC_ENABLE_PS2K. BUG=b:154790509 TEST=Check Keyboard is functional under OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I31c74ddb3608589e5a4753c7e487f250b112bb1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40745 Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/intel/common/block/smbus: Set SPD array NULL if no DIMM presentEric Lai
Set SPD array NULL if no DIMM present. do_smbus_read_byte returns negative value if SMBus transaction fails. BUG=b:154445630,b:151702387 TEST=Check SPD is NULL if no DIMM in the slot. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie81adbfab5bb1d5c557fe549a158cb68e26b1162 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-28soc/intel/cannonlake: Report driver strength by _DSM in eMMC ACPI deviceKane Chen
According to doc 621880, it suggests setting 40 ohm in byte 185 in extCSD. This commit provides _DSM method for driver to query driving strength. TEST=mmc extcsd read |grep HS_TIMING and found bit[7:4] is set to 4 BUG=b:154159888 Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I1b4df8b0d1d2cad3a7f521ad47ee5a4b3320c767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-28soc/intel/cometlake: Add ucode from repoFelix Singer
On Comet Lake, add the following microcode updates from the 3rdparty repository: - 06-8e-0c (CPUID signature: 0x806ec) - 06-a6-00 (CPUID signature: 0xa0660) Tested with Clevo N141CU. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Id10b013df8ce98a4e9830782570e20fbcfad05c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-04-283rdparty/intel-microcode: Update submodule pointer to 20191115 releaseFelix Singer
Update submodule pointer to 20191115 release to include the microcode update for CML-U62, and others. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I4765a70be0b1182acd340a3c31a5d71fd0ab500f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28mb/intel/jasperlake_rvp: Configure GPIO for JSLRVPRonak Kanabar
We need to configure GSPI related gpios for external EC and TPM. Along with GSPI configuring gpios for LAN (power down), FSP_INT and PCH_INT. BUG=None BRANCH=None TEST=External EC card works and LAN is powered down. Change-Id: I1f2d32537b56802d0631a94590a6ebe156c5cdd0 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40362 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/intel/jasperlake_rvp: Update SMBIOS data for JslrvpMeera Ravindranath
1)Change Mainboard Part Number to jslrvp 2)Change Mainboard Family to Intel_jslrvp 3)Generate SMBIOS table and fill sku id information in SMBIOS BUG=None BRANCH=None TEST=Mosys works on jslrvp and Sku ID info is generated Change-Id: Iad0b394fea017223a5b98fff0cb4c2bd1d5a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40011 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/intel/jasperlake: Add new MCH device idsMaulik V Vaghela
Add new MCH device-ids for jasperlake. Reference is taken from jasperlake EDS volume 1 chapter 13.3. BUG=None BRANCH=None TEST=code compiles and able to boot the platform. Change-Id: I38e09579c9a3681e9168c66085cbb3a092dc30cc Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-04-28soc/baytrail/raminit: Populate SMBIOS type 17 tablesMatt DeVillier
Populate SMBIOS type 17 tables using data from SPD and read via IOSF. Refactor print_dram_info() to pass thru SPD data and channel/speed info. Move call to print_dram_info() after cbmem initialization so the SMBIOS data has somewhere to go. Test: build/boot google/swanky, verify via dmidecode. Change-Id: I1c12b539c78d095713421b93115a4095f3d4278d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28mb/google/octopus: add default non-ChromeOS FMAPMatt DeVillier
Add a FMAP which supports SMMSTORE and non-ChromeOS payloads, since GeminiLake-based devices like Octopus cannot use an automatically-generated FMAP due to strict layout requirements. Change-Id: Iebacbea5b3a782b2abf1d6e28acd21b87dc9402b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40596 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/octopus: Add VBT for ampton variantMatt DeVillier
Add VBT file, extracted from stock Google firmware, and select its use via Kconfig. Change-Id: I256c1c72d1d1e40ea9426fa717bfc4f9c950a91f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28drivers/intel/gma: put controller in separate headerMatt DeVillier
Including i915.h just for the GMA/SSDT related functions means dragging along all of i915_reg.h as well, which is problematic since some platforms (like Apollo Lake) use overlapping symbols. To avoid this conflict, break out the GMA/SSDT bits into their own header which can be included without conflict. Change-Id: I73fb7ef01abaafdcdbc44f1e3f5eb1883fc31616 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-04-28payloads/tianocore: Allow custom boot splash for UefiPayloadPkgMatt DeVillier
Allow a custom boot splash to be used with UefiPayloadPkg: - remove Kconfig guards restricting to CorebootPayloadPkg - set destination path for logo file based on bootloader selected Test: build/boot qemu with UefiPayloadPkg with custom boot logo Change-Id: Ia0a10d1528f516f6b9d3645b83be0fb4e85bc348 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28payloads/tianocore: Init submodulesMatt DeVillier
Recent changes to upstream edk2 necessitate ensuring that Tianocore's submodules exist and are up to date, otherwise building UefiPayloadPkg will fail. Change method used to detect a dirty tree so that initialized submodules do not taint the result. Test: build qemu with Tianocore UefiPayloadPkg option successfully. Change-Id: Ie2541f048966ec0666d8196508ccdb6c5f089de6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28Documentation: Spell vboot all lowercasePatrick Rudolph
Update all occurrences of vboot and spell it lowercase. Change-Id: I432b0db8a3dda43b71844e557a3d89180f25f1c3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-04-28security/lockdown: Write-protect WP_ROPatrick Rudolph
Allow to write protect only the WP_RO region in case of enabled VBOOT. One can either lock the boot device in VERSTAGE early if VBOOT is enabled, or late in RAMSTAGE. Both options have their downsides as explained below. Lock early if you don't trust the code that's stored in the writeable flash partition. This prevents write-protecting the MRC cache, which is written in ramstage. In case the contents of the MRC cache are corrupted this can lead to system instability or trigger unwanted code flows inside the firmware. Lock late if you trust the code that's stored in the writeable flash partition. This allows write-protecting the MRC cache, but if a vulnerability is found in the code of the writeable partition an attacker might be able to overwrite the whole flash as it hasn't been locked yet. Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-04-28security: Add common boot media write protectionPatrick Rudolph
Introduce boot media protection settings and use the existing boot_device_wp_region() function to apply settings on all platforms that supports it yet. Also remove the Intel southbridge code, which is now obsolete. Every platform locks the SPIBAR in a different stage. For align up with the common mrc cache driver and lock after it has been written to. Tested on Supermicro X11SSH-TF. The whole address space is write-protected. Change-Id: Iceb3ecf0bde5cec562bc62d1d5c79da35305d183 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-28drivers/spi/tpm: Add support for non CR50 SPI TPM2Patrick Rudolph
Add support for a STM SPI TPM2 by adding checks for CR50. Tested using ST33HTPH2E32. Change-Id: I015497ca078979a44ba2b84e4995493de1f7247b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-27mb/google/deltaur: Enable DRIVERS_I2C_HID for TouchpadEric Lai
Cirque touchpad uses I2C_HID driver. BUG=b:152931802 TEST=Touch pad can work well in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3f8d5abad2f153f395ba7e3f979ad3d2526e040c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-27mb/google/deltaur: Move the code under domainEric Lai
Chip drivers not overrided if out of domain. Only device can get override, so move the code under domain. BUG=b:152924290,b:152931802 TEST=Touch screen and Touch pad can work well. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iaaa73e36ec268d26ebd3cafab79179fe22a926a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-27arch/x86/acpigen: Add helpers for generating _ADRFurquan Shaikh
This change adds the following helpers: acpigen_write_ADR: Generates _ADR object using provided 64-bit address acpigen_write_ADR_pci_devfn: Generates _ADR object for PCI bus device using devfn as input. acpigen_write_ADR_pci_device: Generates _ADR object for PCI bus device using struct device * as input. BUG=b:153858769 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I139dfc30aa7db303c1e8bd4a8f9ee0933a60139b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40670 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-27mb/google/hatch/var/jinlon: Update DPTF parametersWisley Chen
The change applies the DPTF parameters received from the thermal team. 1. Set PL1 Min to 3W 2. Set sample period of TCPU/TSR0/TSR1 to 30 Sec 3. Enable EC_ENABLE_MULTIPLE_DPTF_PROFILES and add trigger points for tablet mode. 4. Update trigger points of CPU/TSR0/TSR1 BUG=b:154564062, b:154290855 BRANCH=hatch TEST=build and verified by thermal team. Change-Id: I87170e63de222487a3bda1217c4ee87a2ec1984f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-27sb/pi/hudson: Const'ify pci_devfn_t devicesElyes HAOUAS
Change-Id: I9e63c811c4ac5674b2930304455d828ee516b521 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-27sb/amd/cimx/sb800: Const'ify pci_devfn_t devicesElyes HAOUAS
Change-Id: I25a6c3ac2426881c6b3f6390ffdc76f08944b7fa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-27sb/amd/agesa/hudson: Const'ify pci_devfn_t devicesElyes HAOUAS
Change-Id: I5a9078baa2224865d0746b6d41f6053ac3a51e09 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-27Documentation: Add vboot on Lenovo devicesPatrick Rudolph
Describe vboot implementation details for retrofitted Lenovo ThinkPad devices. Change-Id: Ibabcc939d9d01f00a93fd42adc48057966ad877e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39151 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-27mb/google/volteer: add touchscreen entry to VolteerAlex Levin
BUG=b:149588766 TEST=ELAN and Goodix touchscreen works. Signed-off-by: Alex Levin <levinale@chromium.org> Change-Id: I1c3e75eb03a8ab434ee58bf36a155f2255612083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-04-26soc/intel/apollolake: Avoid CONFIG_PCIEX_LENGTH_256MB selectionSubrata Banik
This patch removes APL SoC selecting CONFIG_PCIEX_LENGTH_256MB Kconfig as default configuration for CONFIG_SA_PCIEX_LENGTH_MIB is 256MB. TEST=Able to build and boot APL platform. Change-Id: I61249f0adff5e03c07a568556e1ff76b27c6d368 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40378 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-25mb/google/deltaur: Move early gpio table to variantsEric Lai
If set variant early gpio table NULL, it will override the baseboard table. Move early gpio table to variant level. BUG=b:154310066 TEST=Check H1 has no I2C error occurs. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie4c4648ccf918446a499019a4f77f64e43a92c76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-25mb/google/hatch/var/jinlon: Tune i2c frequency under 400 KHzWisley Chen
Tuning i2c frequency for jinlon: I2C0: 392.7 KHz I2C1: 390 KHz I2C3: unused I2C4: 388.8 KHz BUG=b:154900217 BRANCH=hatch TEST=emerge-hatch coreboot chromeos-bootimage, and measured with scope Change-Id: I9b186193f34027d03dd349cf1e29bb266b167383 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-25mb/lenovo/x200: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad X200 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight I have tested it on an X200 with Kernel 5.4 and it seems to work fine. Change-Id: I14752ab33484122248959517e73f96b6783b1f65 Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-25mb/lenovo/{x201,t410}: Move ThinkLight codeStefan Ott
This patch moves the code to control the ThinkLight to the common ACPI folder for h8. This reduces code duplication and allows other ThinkPads to include the same code for ThinkLight support. Change-Id: I57de7516051bdcbb23fc21b4de352f265075893b Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-25asus/p2b-ls: Replicate OEM GPO configurationKeith Hui
Replicate the GPO configurations from OEM BIOS, obtained via inteltool. Among the GPOs are termination controls for the onboard SCSI buses. TEST=read/write Maxtor Atlas 10k3 18GB HDD connected to Ultra2 LVD port Change-Id: I86183acd8e1a830d7639c21ec179fbdbe937f8ee Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38354 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-25include/device/azalia: Add enums and MACROsPatrick Rudolph
Instead of only using magic values add enums and defines to allow writing the codec init sequence in human readable form. This will replace the magic numbers in mainboards HDA verb tables. Change-Id: Icad07c2b550657b879ad9328a70ba44629a0c939 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-25soc/intel/tigerlake: Fix FSP SPD index for DDR4Furquan Shaikh
For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1 to set SPD for index 4. This change adds a helper macro to translate DDR4 channel # to the index # that the FSP expects. BUG=b:154445630 TEST=Verified that memory initialization for DDR4 is successful. Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-24soc/intel/xeon_sp/cpx: Calculate number of threads based on socketsAndrey Petrov
Assuming given system is populated with multiple CPUs of same SKUs, calculate number of threads based on MAX_SOCKET. This is a stop gap solution until proper way of identifying total number of sockets is determined. Change-Id: I7ebad3d57c47b9eeb7d727ffb21bc0a1a84734fd Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-24soc/intel/xeon_sp/cpx: Bump MAX_CPUSAndrey Petrov
Some dual-socket socket systems offer over 100 threads available. Other multi-socket configurations potentially offer even greater numbers of CPUs (over 9000!). Bump MAX_CPUS to 255. Change-Id: I50a181b89f40777a9f7b3881280c7bacf1b947cb Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 01:27:15 +0000