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2020-11-13vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1454Subrata Banik
List of changes: 1. FSP-M Header: - Add new UPD Lp5CccConfig - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx, PsOnEnable, RpPtmBytes, PmSupport, GtFreqMax, Hwp, TccActivationOffset, Cx, PchLockDownGlobalSmi, PcieRpLtrMaxSnoopLatency, PcieRpLtrMaxNoSnoopLatency, UnusedUpdSpace45 Change-Id: I973f48b2af0336f04ee16cd1c4c91940a49af0e3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47244 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/{skl,cnl}: replace PM ACPI timer dt option by KconfigMichael Niewöhner
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and set the FSP option for PM ACPI timer enablement from its value instead of using the old devicetree option. Also drop the obsolete devicetree option from soc code and from the mainboards and add a corresponding Kconfig entry instead. Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disablingMichael Niewöhner
FSP already disables the PM ACPI timer, when EnableTcoTimer=0. Test: clevo/l140cu and supermicro/x11ssm-f have the PM ACPI timer disable bit set when EnableTcoTimer=0. Change-Id: If370d3acf87ae6d1d7c64bf27228877cdd92ab2d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-13soc/intel/common: add Kconfig to enable/disable the ACPI PM timerMichael Niewöhner
Currently, the ACPI PM timer state gets set in devicetree by the option PmTimerDisabled. However, it is not board design dependent. Thus, add a user-selectable Kconfig option. Disabling the PM ACPI Timer is only valid when PM Timer emulation is supported and is only possible, when there is a hardware PM Timer (APL does not have one for example). SoCs, where the hardware PM Timer can be disabled must select `PM_ACPI_TIMER_OPTIONAL`. This new Kconfig gets used in the follow-up commits of this series. Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-13mb/hp/folio_9480m: Update northbridge ACPI filenameAngel Pons
Fix build errors, since `haswell.asl` was dropped in commit 79e3a1f8a5 (nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`) Change-Id: Iaec5de2d74dd81c58a581bb511ba6a63629141aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47575 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13Doc/relnotes/4.13: Add several relevant changesAngel Pons
While some of these have little impact, they are worth mentioning here. Change-Id: Idbf629ae77b8918ff1d93edb7b6c4669bbbe17df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-13soc/amd: factor out _SOC_DEV macro into common blockFelix Held
TEST=Timeless build doesn't change for Mandolin and Gardenia. Change-Id: I1aef68459569536207697bfca407145a7b5334f4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-13soc/amd/common/block/include: make include guards more uniformFelix Held
TEST=Timeless build doesn't change for Mandolin and Gardenia. Change-Id: I5d3ae1459c333658f4c86388f1822d92ca13c658 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-13mb/supermicro/x11-lga1151-series: Fix up comment styleAngel Pons
Change-Id: I5b6191d2b5f6fd6d127934eda56e3c24181b0c4c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47565 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13mb/clevo/cml-u: Fix up comment styleAngel Pons
Change-Id: Idefc15fec1d62d68d88e91c76f59e1a60a3996b6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47564 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/broadwell: Split up acpi.cAngel Pons
Change-Id: Ie9c57b6f5c226cee8797027941fa03e69de52923 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46796 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/broadwell: Flatten northbridge folder structureAngel Pons
Having folders for bootblock and romstage is no longer necessary. Change-Id: I7d1f4063de6a1a1ff9ee7478e94f889a50102054 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46795 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/broadwell: Relocate CPU filesAngel Pons
Change-Id: Ib2ddce78db21db9c8deac632a77ecd71eb9887c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46794 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13broadwell: Flatten `acpi_init_gnvs` functionAngel Pons
Instead of relying on mainboards to call it, do like Lynx Point. Change-Id: Idb7457e0734e19d0a26f0762079e273b6e740475 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46793 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13broadwell: Factor out `acpi_fill_madt` functionAngel Pons
It is identical for all Broadwell mainboards, thus deduplicate it. Change-Id: I74559fbe42e44aa4d15ced5d88f6c15a1bf5203b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46792 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13nb/intel/haswell/acpi: Do not add PEG devices for LPAngel Pons
Haswell Low Power variants do not have PEG at all. Change-Id: Ia5577104b00bfc8713b54c3c43f8dcdd3bc367df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46791 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13nb/intel/haswell/acpi: Move PEG and CTDP includes downwardsAngel Pons
This change is just to align with Broadwell. Change-Id: I25a481503f5df79502f5ae60c87e7dacb781adad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46790 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`Angel Pons
Tested with BUILD_TIMELESS=1, Google Wolf remains identical. Change-Id: I710581156937b042ba4cf5948c65d0795ad37bbf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46789 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13nb/intel/haswell/acpi/hostbridge.asl: Drop unused registersAngel Pons
These are not used anywhere and are not present on Broadwell. Change-Id: I2d1359286ac719cb5daefc955d5c6085e2949c1f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46788 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVENAngel Pons
There's no need to perform manual shifting and masking when ACPI allows one to painlessly describe bitfields of a register. The now-unused DVEN definition will be dropped in a follow-up, alongside other definitions. Change-Id: Iab6972c78c1114c8e3dfee28320ae233421ff154 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46787 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/broadwell/acpi: Rename `systemagent.asl`Angel Pons
Rename it to `hostbridge.asl`, which is what Haswell uses. Change-Id: I6f97fc5c9459fe6b66dcfcf51900c751beda0ebe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46786 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13sb/intel/lynxpoint/acpi/pch.asl: Drop unused FD definitionsAngel Pons
These Function Disable definitions have been copied from Cougar Point, are not used by any mainboard, and may be incorrect. So, remove them. Change-Id: I36f732bce22ec33aab42beababe54c4d88e0205b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46784 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13haswell/lynxpoint: Drop remaining uses of `ISLP` methodAngel Pons
There's no need to dynamically differentiate between traditional and Low Power platforms at runtime, and doing so makes code reuse more complex. Change-Id: Id40f2f5f41db00487af9115eabee8874c2399030 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46785 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13sb/intel/lynxpoint/acpi/gpio.asl: Serialize GWAK methodAngel Pons
Commit 576b7c7 (broadwell: gpio.asl: Make GWAK method serialized) made GWAK serialized for Broadwell. This commit follows suit on Lynx Point. The reason to serialize this method is because it creates named objects which depend on input parameters, and thus cannot be created elsewhere. Change-Id: I892700df3bba079e3280008f619017e3954d5a06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46783 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCIAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: I0ce8f1e4aaa86d2f7607fec9214dc64d1f530c88 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46782 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resourceAngel Pons
LynxPoint-LP handles GPIOs differently, and LynxPoint-H has the same GPIO kind as previous-generation PCHs, such as Cougar Point. Remove some unneeded logic from `_CRS` and declare the GPIOBASE resource statically. The preprocessor allows later ACPI deduplication to remain reproducible. Change-Id: If771d5b6c3a1623da7d015ed50199877615409b2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46781 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13sb/intel/lynxpoint/acpi: Statically define _PRW valuesAngel Pons
In order for ACPI deduplication to be reproducible, the `ISLP` method needs to disappear. Replace the _PRW methods with a name and a macro. Change-Id: Id0a46965b66f1a70e8f8868af01a535207c9f5c7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46780 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/broadwell/pch/acpi/hda.asl: Rename to `audio.asl`Angel Pons
This is merely to ease diffing Lynx Point and Broadwell ASL code. Tested with BUILD_TIMELESS=1, Google Buddy does not change. Change-Id: I9f6ab98388d2a2915a48377ebe9e724cfee4b95f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46779 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/broadwell/pch/acpi: Clean up cosmeticsAngel Pons
Use ASL 2.0 syntax where possible and uniformize code style to match the IASL disassembly. Some `Store` in gpio.asl change the binary if touched. Tested with BUILD_TIMELESS=1, Google Buddy does not change. Change-Id: Ic13c081fd7ee2212d851cc14263c1e2fd8970072 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46778 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13sb/intel/lynxpoint/acpi: Clean up cosmeticsAngel Pons
Use ASL 2.0 syntax where possible and uniformize code style to match the IASL disassembly. Some `Store` in gpio.asl change the binary if touched. Also remove outdated comment and remove `LynxPoint` from `serialio.asl`. Tested with BUILD_TIMELESS=1, Google Panther does not change. Change-Id: Ie0994fa546ff54ebb533afcc6205efb36da99a67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46777 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13mb/google/reef: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ifc6dd5f6549e7501f350afe8456a9a8096edcc25 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/poppy: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ida1b1d05b39e67a9eba3bfaecca37f38821a438b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/kahlee: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ib2f203b5f5eea5c25cfd4543f5ed9f15101b1735 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/octopus: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ic334816712370da63471135da8dd598ab02d54ef Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/zork: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I75a92616f11054993ff5a5bfefce5c3f4638c07c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/drallion: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Iff00667377eecedcf0b83bcfc0bf50bd4c3411eb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/deltaur: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I1773973f64bcc5ef6bd1856c5d8eb998bb6a4888 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/hatch: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I320198d56131cf54e0f73227479f69968719b2a7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/volteer: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ie7b82ea07ef97b2096d75229c445bd3a65cb3be0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/dedede: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=emerge-dedede coreboot Change-Id: I9d8fa57ae0f554896a4a0722e3e89567676382d4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/dedede/var/metaknight: enable USB2 port for cameraTim Chen
Enable USB2 port 5 for user facing camera. Enable USB2 port 6 for world facing camera. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Iecb7787d46eab7096dec9f838a16da101105e09a Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-13mb/google/dedede/var/metaknight: Disable I2C port 3Tim Chen
Disable I2C port 3 for metaknight BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Ic4a056d53a8c8abd04a9b786428da0986a255276 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-13MAINTAINERS: add trailing slash to make gerrit add me as reviewerMichael Niewöhner
The trailing slash is required to make gerrit add me on changes for the whole tree, not just for the directory itself, which obviously would only change if being deleted or renamed. This also fixes the behaviour for Felix Singer. Change-Id: I601aebd4335c7326deca0118725a6f25cec524a9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-13soc/intel/xeon_sp: Tidy up adding MADT ioapic entriesArthur Heymans
Add a helper function to print out debug info and add the MADT entry. Change-Id: I1a00f87c6edef530c5352929ee9279782be4b112 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-12mb/amd/mandolin/Kconfig: update help text for AMD_LPC_DEBUG_CARDFelix Held
The existing help text wasn't updated for Mandolin after it was copied from an older reference board and contained some information that doesn't apply to Mandolin. Change-Id: Ib34abb2ee8b289df5f7085957042fe00ad506ca9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-12mb/amd/mandolin/Kconfig: add help text for the EC blobFelix Held
Change-Id: If8d3ebdb9a41330312c26fb5796c07de1b87b3eb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47480 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-12mb/clevo/l140cu: add CMOS layout and defaultsMichael Niewöhner
Add CMOS layout and defaults files and enable CMOS options in Kconfig. Test: changed loglevel setting, rebooted and checked the log. Change-Id: Ia1a27818b2d12fb7578189e5748b8073c8f928e3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46311 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-12soc/intel/xeon_sp: Use a common function to get the IIO HOBArthur Heymans
TESTED ocp/deltalake still boots. Change-Id: I69f336c1ff348b8e820340b84494929f2c58ce72 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47296 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-12drivers/i2c/rx6110sa: Delete unused definesWerner Zeh
The defines for RX6110SA_SLAVE_ADR and RX6110SA_I2C_CONTROLLER are not used anymore and can be deleted. Change-Id: I3cddf7a9e2f757a22c729ae0f0ff767d55909b9c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: siemens-bot Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2020-11-12drivers/i2c/rx6110sa: Add basic ACPI supportWerner Zeh
This patch adds basic ACPI support for the RTC so that the OS is able to use this RTC via the ACPI interface. If the Linux kernel is able to find the RTC in ACPI scope, you should see the following lines in dmesg, where [n] is an enumerated number: rx6110 i2c-RX6110SA:00: rtc core: registered RX6110SA:00 as rtc[n] rtc rtc[n]: Update timer was detected Change-Id: I9b319e3088e6511592075b055f8fa3e2aedaa209 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 08:32:44 +0000