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2012-11-12cbfstool: add add-flat-binary command to add raw executablesStefan Reinauer
Example: cbfstool image-link.bin add-flat-binary u-boot.bin fallback/payload \ 0x100000 0x100020 will add u-boot.bin as fallback/payload with a load address of 0x100000 and an entry-point of 0x10002. Change-Id: I6cd04a65eee9f66162f822e168b0e96dbf75a2a7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1792 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-09libpayload: Add an option to skip console initialization on startup.Gabe Black
A payload may want to decide whether it uses certain input/output consoles, or that it wants support for outputing to a particular device but not to use that device as a console. This change adds a config option which skips the call to console_init in start_main. Change-Id: I32b224d4d0bd3a239b402ecb09ee907d53225735 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1732 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09libpayload: Add CB_ prefixes to some constants in coreboot_tables.h.Gabe Black
This makes their names more consistent with other constants in this header, avoids name collisions, and makes it more obvious where the names came from. Change-Id: I7b8bd4ada0fbaf049f35759a907281265f5bb2e6 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1729 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09libpayload: Change "GPIOs" into flags.Gabe Black
Some constants which were used to interpret the contents of the coreboot tables were moved to the appropriate libpayload header file. The constant which describes the maximum length of a GPIO name was renamed to have a CB_ prefix. That makes it more obvious what sort of GPIO name it describes, and reduces the change of a name collision. It also makes it more consistent with other names in that header, although some other exceptions still exist. Change-Id: I6c0082b3198d34e8a78507fbfac343ee8facf0dc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1728 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09[PATCH] libpayload: Implement EHCI reset functionAnton Kochkov
Added ehci_reset() function to do a full reset of the host controller Change-Id: Ia48db8462ebbb8f260813eb6ba8349d002c4678b Signed-off-by: Anton Kochkov <a.kochkov@securitycode.ru> Reviewed-on: http://review.coreboot.org/1814 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09Make coreboot use the offset parameter in cbfstool createStefan Reinauer
On Sandybridge and Ivybridge systems the firmware image has to store a lot more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware - MRC cache information This option allows to limit the size of the CBFS portion in the firmware image. Change-Id: Ib87fd16fff2a6811cf898d611c966b90c939c50f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1770 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09Prevent inclusion of tsc.h when not neededVadim Bendebury
src/include/timestamp.h is an interface describing timestamp storage in coreboot. Exporting this interface is complicated by inclusion of tsc.h which is needed only for the API and is not used in structure definitions. Including this dependency only when needed fixes the problem. Change-Id: Ie6b1460b1dab0f5b5781cb5a9fa89a1a52aa9f17 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1753 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-09PCH: Add register descriptions used by IGD OpRegionStefan Reinauer
These bits are used by the IGD OpRegion code Change-Id: I89a11fc5021d51e0c1675ba56f6a3bc3b79bb8aa Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1751 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-09Add IGD Opregion variables to NVSStefan Reinauer
In order to support Intel's IGD Opregion standard, we need an additional set of flags shared between firmware, ACPI, SMM, and the graphics driver. Change-Id: I1a9b8dff5e5ee8d501b6672bc3bcca39ea65572e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1750 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09Make register/value lists constStefan Reinauer
These can be stored in the code segment, since it's never changed. Change-Id: I8b3827838e08e6cc30678aad36c39249fbca0c38 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1749 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-09Get rid of hard coded strings in ACPI tablesStefan Reinauer
(cosmetical) Change-Id: I3e01d8fbf2d71abcfcbe47efedd2184566c91df7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1748 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-09Add Gigadevice SPI rom supportMartin Roth
Add support for GigaDevice SPI ROMS. The GD25Q64B device has been tested, the other rom devices added to the file have not. Change-Id: If35676ca6b90329f15667ebb32efa0d1a159ae91 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1747 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09ELOG: Add EC events to elog headerDuncan Laurie
These events were initially for Chrome EC but they can be applied to any EC. Change-Id: I0eba9dbe8bde506e7f9ce18c7793399d40e6ab3b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1746 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09SPI: re-init SMM SPI driver after lockdownDuncan Laurie
If the driver is initialized before the lockdown then it will fail to work after the lockdown bit is set. Change-Id: Idc05d33d8d726bf29cb3c9b1b4604522bd64170a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-09libpayload: Add a function to retrieve the rows and cols of the video console.Gabe Black
This is useful if you need to put some text in a particular place on the screen, for instance in the middle. Change-Id: I3dae6b62ca1917c5020ffa3e8115ea7e8e5c0643 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1734 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09libpayload: Separate video initialization and the video console.Gabe Black
It's possible to want to display text on the display without using it as a console. This change separates the initialization of the video code from setting up the video console by pulling out everything but installing the console into a new function called video_init. Change-Id: Ie07654ca13f79489c0e9b3a4998b96f598ab8513 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1733 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09libpayload: Add support for the CBMEM in memory console.Gabe Black
Change-Id: I1489b5306ef1ca078686fed4dba2d242f70ad941 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1727 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09Change flashmap base to reflect new FMAP in U-bootDuncan Laurie
The RO_FMAP base moved from 0x5f0000 to 0x610000. Also update Kconfig default and add a descripton so the default can be changed by boards. Change-Id: I0caad0ce6e6f19750dbbf042a5a489b558f62b96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1705 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-09ifdtool: Add locking/unlocking and dumping of access permissionsStefan Reinauer
ifdtool will now dump access permissions of system comonents to certain IFD sections: Found Master Section FLMSTR1: 0xffff0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x0c0d0000 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR3: 0x08080118 (GbE) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: disabled Requester ID: 0x0118 Also, ifdtool -u /path/to/image will unlock the host's access to the firmware descriptor and ME region. ifdtool -l /path/to/image will lock down the host's access to the firmware descriptor and ME region. Change-Id: I3e081b80a9bcb398772416f143b794bf307b1c36 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1755 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-09mc146818rtc: Remove the hyphen to build on NetBSD and DarwinZheng Bao
http://netbsd.gw.com/cgi-bin/man-cgi?date++NetBSD-current The NetBSD manual tells us the date in NetBSD doesn't take any flags to enable or disable padding in the format. By default, date pads numeric fields with zeroes. This will convert the number to octal one. So add "0x" to convert it to BCD directly. Change-Id: Icd44312acf01b8232f1da1fbaa70630d09007b40 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1804 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09mc146818rtc: Update the Day of Week in CMOS in the right way.Zheng Bao
The range of weekday in CMOS is 01-07, while the Sunday is 1, and Saturday is 7. The comand date in coreutils defines %u day of week (1..7); 1 is Monday %w day of week (0..6); 0 is Sunday There are 1 day offset for each week day. So we use "%w" and plus 1 before we update the weekday in CMOS. Change-Id: I3fab4e95f04924ff0ba10a7012b57da1d3f0d1a5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1802 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09Makefile.inc: Delete trailing space in build.hZheng Bao
Change-Id: I0c5ed84a405dc9e98e8912ccf1a2f83c4c601fc7 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1803 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09Fix abuild output in JenkinsStefan Reinauer
Ignore the harmless broken pipe messages from "yes" Building amd/pistachio; i386: ok, using i386-elf-gcc Using payload /srv/jenkins/payloads/seabios/bios.bin.elf Creating config file... (blobs, ccache) yes: standard output: Broken pipe yes: write error ok; Compiling image on 4 cpus in parallel .. ok. (took 10s) Change-Id: Ic53e246aac3ab6d7ea7a006a8dfac1c3f85797bc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1813 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09Fix Segmentation Fault in ifdtoolStefan Reinauer
If a section is bigger than the FD file it is injected into, and the FD lies about the size of the FD file, ifdtool would crash because reading in the section writes beyound the FD file in memory. Change-Id: Idcfac2b1e2b5907fad34799e44a8abfd89190fcc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1754 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-08mainboard/roda/rk886ex: Disable CHECK_SLFRCS_ON_RESUMENico Huber
This makes resume from S3 work again. The check is new and fails on other boards, too. Change-Id: I0ada569e4ba649b9ac82768b0888e16104c621e8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1809 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08Add utility for parsing/modifying DTD arrayVadim Bendebury
Detailed timing descriptor (DTD) is an 18 byte array describing video mode (screen resolution, display properties, etc.) in Intel Option ROM. Option ROM can support multiple video modes, specific mode is picked by the BIOS through the appropriate Option ROM callback function. The new utility allows to interpret the 18 byte hex DTD dump, and/or modify certain values, and generate a new DTD. To parse the DTD contents just pass the 18 bytes to the utility in the command line. To modify the existing contents and generate a new dump precede the 18 bytes with '-m' and follow prompts. Change-Id: Ib00bdaf42c350b98b5a48d08e6bb347b5ec25a8b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08Refactor the endianness conversion functions and header files.Gabe Black
The endianness of an architecture is now set up automatically using Kconfig and some common code. The available conversion functions were also expanded to go to or from a particular endianness. Those use the abbreviation le or be for little or big endian. Built for Stumpy and saw coreinfo cbfs support work which uses network byte order. Used the functions which convert to little endian to implement an AHCI driver. The source arch is also little endian, so they were effectively (and successfully) inert. Change-Id: I3a2d2403855b3e0e93fa34f45e8e542b3e5afeac Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1719 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08Update libpayloads understanding of the coreboot tables.Gabe Black
Give it somewhere to put the new info in sysinfo, and tell it how to parse the new tables which it doesn't yet understand. Change-Id: I01d3318138696e6407553c27c1814f79e3fbc4f8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1718 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08Log unexpected post code from the previous bootDuncan Laurie
Read out the post code from the previous boot and log it if the code is not one of the expected values. Test: 1) interrupt the boot of the system, this is easiest with warm reset button when servo is attached 2) check the event log with mosys 65 | 2012-09-09 12:32:11 | Last post code in previous boot | 0x9d Change-Id: Id418f4c0cf005a3e97b8c63de67cb9a09bc57384 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1744 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08Add support for storing POST codes in CMOSDuncan Laurie
This will use 3 bytes of CMOS to keep track of the POST code for the current boot while also leaving a record of the previous boot. The active bank is switched early in the bootblock. Test: 1) clear cmos 2) reboot 3) use "mosys nvram dump" to verify that the first byte contains 0x80 and the second byte contains 0xF8 4) powerd_suspend and then resume 5) use "mosys nvram dump" to verify that the first byte contains 0x81 and the second byte contains 0xFD Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08x86 memcpy: Copy 4 bytes at onceStefan Reinauer
This is a slight improvement over the rep movsb loop Change-Id: Id71d9bfe5330b154a5c62fac85ce3955ae89b057 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08RTC: Don't clear pending interrupt in resume pathDuncan Laurie
The linux kernel relies on the RTC reporting pending interrupts if the RTC alarm was used to wake the system. If we clear these flags here then the rtc-cmos driver in the kernel will think that no interrupts are pending and will not re-start the timerqueue to handle the alarm timerqueue node. This flag doesn't exist in SMM but the rtc code is compiled there. Since rtc_init() is not called by SMM it is guarded with an ifdef. I performed several thousand suspend/resume cycles without seeing an issue where hwclock was unable to read from /dev/rtc. There still is a potential kernel issue where the timerqueue can stall but this makes that much less likely to happen on resume. Change-Id: I5a343da4ce5c4c8ec4783b4e503869ccfa5077f0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1741 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08smi: make tseg_relocate check pointer offsetDuncan Laurie
In case tseg_relocate() is called again on a pointer we should not relocate it again. Change-Id: Ida1f9c20dc94b448c773b14d8864afe585369119 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1740 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08elog: add extended management engine eventDuncan Laurie
We are seeing ME disabled and ME error events on some devices and this extended info can help with debug. Also fix a potential issue where if the log does manage to get completely full it will never try to shrink it because the only call to shrink the log happens after a successful event write. Add a check at elog init time to shrink the log size. Change-Id: Ib81dc231f6a004b341900374e6c07962cc292031 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08spi: fix erase in SMM while SPIBAR is lockedDuncan Laurie
The handling of write enable was not entirely correct, the opcode needs to be skipped when the controller is locked down. Addresses were not getting set properly for erase commands which seemed to mostly work when the previous command had set an address. Tested by adding events to the event log at runtime on a freslhy flashed device (with locked down SPI controller) until the log log shrink happens to ensure it does not hang: hexdump -C elog.event.kernel_clean 00000000 01 00 00 00 ad de 00 00 00 00 for x in $(seq 1 232); do cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog done mosys eventlog list | tail -6 154 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 155 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 156 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 157 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 158 | 2012-09-01 13:54:43 | Log area cleared | 1030 159 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown Change-Id: I3a50dae54422a9ff37daefce3632f8bcbe4eb89f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1717 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08Get more informative output from cbmem.pyVadim Bendebury
This is a cosmetic change which formats timestamp information retrieved by cbmem.py. Instead of printing timestamps in a single line, print them one per line and add time (in us) elapsed since the previous timestamp. time base 4149594, total entries 18 1:56,928 2:58,851 (1,923) 3:175,230 (116,378) 4:175,340 (109) 8:177,199 (1,859) 9:214,368 (37,168) 10:214,450 (81) 30:214,462 (11) 40:215,205 (743) 50:217,180 (1,974) 60:217,312 (132) 70:436,984 (219,671) 75:436,993 (8) 80:441,424 (4,431) 90:442,487 (1,062) 99:553,777 (111,289) 1000:556,513 (2,736) 1100:824,621 (268,107) Change-Id: I0d25cafe766c10377017697e6b206276e1a92992 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1716 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08Fix cbmem to work on 64 bit platformsVadim Bendebury
For some reason which I fail to understand, specifying endiannes using '@' (which means 'native' and should be the same as '<' on x86 platforms) causes cbmem.py to crash the machine on 64 bit systems. What happens is that the addresses read from various table headers' struct representations do not make sense, when bogus address gets passed to get_phys_mem, the crash happens while that function is executed. dlaurie@ found out that replacing "@" with "<" in fact fixes the issue. After some investigation I am just submitting this fix without much understanding of the root cause. Change-Id: Iaba9bc72a3f6b1d0407a5f1e3b459ccf5063969d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1715 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08Make option rom init more verboseStefan Reinauer
When bringing up VGA by running the option rom it's sometimes useful to get more information about the mode that gets set, or the reason why the mode could not be set or a picture could not be displayed. Also prefix the output from VBE mode setting with VBE: Copying VGA ROM Image from fff0fd78 to 0xc0000, 0x10000 bytes Real mode stub @00000600: 867 bytes Calling Option ROM... int15_handler: INT15 function 5fac! ... Option ROM returned. VBE: Getting information about VESA mode 4161 VBE: resolution: 1280x1024@16 VBE: framebuffer: d0000000 VBE: Setting VESA mode 4161 VGA Option ROM has been loaded Change-Id: I2be11f095dc62ed3c99e0d4272ad9d6521608a44 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08cbfstool: add offset parameter to create commandStefan Reinauer
CBFS allows coreboot rom images that are only partially covered by the filesystem itself. The intention of this feature was to allow EC / ME / IMC firmware to be inserted easily at the beginning of the image. However, this was never implemented in cbfstool. This patch implements an additional parameter for cbfstool. If you call cbfstool like this: cbfstool coreboot.rom create 8192K bootblock.bin 64 0x700000 it will now create an 8M image with CBFS covering the last 1M of that image. Test: cbfstool coreboot.rom create 8192K bootblock.bin 64 0x700000 creates an 8M image that is 7M of 0xff and 1M of CBFS. Change-Id: I5c016b4bf32433f160b43f4df2dd768276f4c70b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1708 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08ELOG: Find flash base in FMAP if possibleDuncan Laurie
Now that we have FMAP support in coreboot use it to find the offset in flash for ELOG to use. If coreboot has elog configured with a smaller size then use that over the FMAP size. This is because I set aside a 16KB region in the FMAP but we only use 4KB of it to keep the impact to boot/resume speed to a minimum. FMAP: Found "FMAP" version 1.0 at ffe10000. FMAP: base = 0 size = 800000 #areas = 32 FMAP: area RW_ELOG found FMAP: offset: 3f0000 FMAP: size: 16384 bytes FMAP: No valid base address, using 0xff800000 ELOG: base=0x003f0000 base_ptr=0xffbf0000 ELOG: MEM @0x00190ad8 FLASH @0xffbf0000 ELOG: areas are 4096 bytes, full threshold 3072, shrink size 1024 Change-Id: I3d826812c0f259d61f41b42797c58dd179f9f1c8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1706 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-07ELOG: Don't disable SPI controller lockdownDuncan Laurie
Now that WREN prefix is handled properly ELOG is able to write when the SPI controller is locked down. To test, ensure that runtime SPI write via ELOG is successful by checking the event log for a kernel shutdown reason code: 5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown 6 | 2012-08-27 11:09:50 | System boot | 26 7 | 2012-08-27 11:09:50 | System Reset Change-Id: If6d0dced7cb0f5ca7038b3d758f31b856826d30b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1712 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07SPI: opmenu special case for WREN as atomic prefixDuncan Laurie
The code that attempts to use the opmenu needs to have a special case for write enable now that it is handled as an atomic prefix and not as a standalone opcode. To test, ensure that runtime SPI write via ELOG is successful by checking the event log for a kernel shutdown reason code: 5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown 6 | 2012-08-27 11:09:50 | System boot | 26 7 | 2012-08-27 11:09:50 | System Reset Change-Id: I527638ef3e2a5ab100192c5be6e6b3b40916295a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1710 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07RTC: Write build date in BCD when clearing RTC CMOSDuncan Laurie
Check the RTC on boot after RTC battery failure and ensure that the reported build date matches what is reported: > grep ^rtc /proc/driver/rtc rtc_time : 01:00:21 rtc_date : 2012-08-16 Change-Id: If23f436796754c68ae6244ef7633ff4fa0a93603 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1709 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07libpayload: Turn the "debug" #define into the usb_debug static inline function.Gabe Black
The "debug" macro used internally in the libpayload USB subsystem was very generically named and would leak into consumers of the library that included usb.h directly or indirectly. This change turns that #define from a macro into a static inline function to move away from the preprocessor, and also renames it to usb_debug so it's less likely to collide with something unrelated. Change-Id: I18717df111aa9671495f8a2a5bdb2c6311fa7acf Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1738 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-07libpayload: Take usb_poll out of usb_initialize.Gabe Black
While it might be slightly more convenient to not have to call usb_poll manually after calling usb_initialize, you'll still likely want to call it before trying to use a USB device since one have have been hotplugged since you last looked. By not calling usb_poll, usb_initialize completes quickly and can be called unconditionally without a long delay. The delay can be put off until later when we're sure it's necessary. Change-Id: Ib8b1bdea996702c42d1b7021f492d9f8e174d304 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1737 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-07libpayload: Make usb_initialize more efficient and fix style problems.Gabe Black
The usb_initialize function would scan for USB host controllers by brute force iterating over all possible busses, devices, and functions. This change makes it recursively scan busses only if it finds them on the other side of a bridge, and only scan for functions beyond function 0 if the device claims to be multifunction. This change also takes the opportunity to clean up some style problems throughout the file. Change-Id: I0f5e8b9a454a42a76d30bccca898c8e1af770b2b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1736 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-07libpayload: Add definitions for more config space registers.Gabe Black
Change-Id: I02cf353ce7c955cb11ca11c0d5b8aa630cf15fdb Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1735 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-07libpayload: Add the format attribute to functions in stdio.h.Gabe Black
gcc recognizes the format function attribute which tells the compiler to expect the format string to look a certain way and for its arguments to be of appropriate types. This helps to prevent errors like the one that was recently fixed in libpayload's assert. Change-Id: I284ae8bff32f72cfd2d1a250d126c729b38a5730 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1731 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-07libpayload: Fix the format string of the assert macro.Gabe Black
The assert macro in libpayload was using a format string which printed the line number with %s. The line number came from the __LINE__ predefined macro which resolves to an integer constant. Change-Id: I0e00d42a1569802137cf440af3061d7f397fdd27 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-07libpayload: Add faster, architecture specific versions of memset and memcpy.Gabe Black
Change-Id: I0f3a82de860fd3afa10a557b37fb90fe6b06ae90 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1726 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
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