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2016-02-043rdparty/vboot: update to current masterPatrick Georgi
It provides a few extensions to the API that are required, such as vb2api_check_hash_get_digest() Change-Id: Ib4d8bdc29751f51f0f7532376175490a0ffd84b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13590 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04intel/skylake: Display ME firmware status before os bootDhaval Sharma
Display ME firmware status before os boot. Specifically this patch reads out the ME hfsts1 and hfsts2 status registers that provide information about overall ME health before device gets disabled. This change reused most of the code from bdw me_status implementation. BUG=chrome-os-partner:47384 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Can observe me status table Change-Id: Ia511c4f336d33a6f3b49a344bfbaea6ed227ffeb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a9d0fb411c3921654f0fdcea2a3d4ee601987af2 Original-Change-Id: Ied7e2dcd9a1298a38dfe1eda9296b9ca8eccf6b1 Original-Credits-to: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/323260 Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13573 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04google/chromeec: Add temporary storage interfaceDuncan Laurie
Add support functions for the Chrome EC temporary storage interface. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados with modified coreboot Change-Id: Id2bc46df9cb2d82b15e3309e78d07407a622b6f0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7e6f693666b162e11eb0611715f10a8f465ad88 Original-Change-Id: Ieefabfc5bcb9d8a5064f0da967c46d0f377ca320 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315217 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13572 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04google/chromeec: Update EC command headerDuncan Laurie
Update to the latest EC command header. BUG=chrome-os-partner:46049 BRANCH=none TEST=emerge-glados coreboot Change-Id: I132f91b31931ed40c20c0f5dbbf4449663768418 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e6d9d51cfe99fe7c3806d1f74ea67b2d2ed5e7e Original-Change-Id: I3c2e268689d64683f4a138e20f518e6eda49a138 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315216 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13571 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/intel/quark: Add minimal Quark SoC X1000 filesLee Leahy
Add the files for minimal Quark X1000 SoC support: * Declare pei_data structure * Declare sleep states and chipset_power_state structure * Specify top of memory * Empty FspUpdVpd.h file TEST=None Change-Id: If741f84904394780e1f29bd6ddbd81514c3e21c9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04libpayload: Add timer driver for armada38xRuilin Hao
Add timer driver for armada38x BUG=chrome-os-partner:47462 TEST=emerge-cyclone libpayload BRANCH=tot Change-Id: Iefb6d1fcb907edb54d55ba8addfb66329af6c3c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd467160ecab050a541a445c2afab9e6bc625635 Original-Change-Id: Id42bafdbc34295b6f8afe5610fb3bab0e0e1b6e8 Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313343 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13114 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/marvell/armada38x: Add i2c driver for armada38xRuilin Hao
Port i2c driver from uboot to coreboot BUG=chrome-os-partner:47462 TEST=emerge-cyclone coreboot BRANCH=tot Change-Id: I8ce2a965acaed68ad0f0518648490ec471c6810b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c2e9592662787ebed1d0aa8cafaa00fd12c2e9c Original-Change-Id: If791228edf29405fa4b2f959a21510bd7da9865b Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313342 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/13113 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/marvell/armada38x: Add gpio driver for armada38xRuilin Hao
Port gpio driver from uboot to coreboot BUG=chrome-os-partner:47462 TEST=None BRANCH=tot Change-Id: Ib6cfbb6e44cb642c7af937778076a51d405ff4a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5cf94502faad96147d4a4adb42eb13edb64a6439 Original-Change-Id: Ia2e081a85347e2fc8bb365ca527ee2ee32af86f1 Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313341 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13112 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/marvell/armada38x: Add spi driver for armada38xRuilin Hao
Port spi driver from uboot to coreboot BUG=chrome-os-partner:47462 TEST=None BRANCH=tot Change-Id: I747be7001f4cfb8eec33e8e5bdef3fe5bb0eb2ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9fbc5c2feb6ffacb54ed94e5c7b94b38be2b2ded Original-Change-Id: Ibea9a050ac8bdab6ce4eeb07accde53aeadade5f Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313340 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13111 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/marvell/armada38x: Add generic support for armada38xRuilin Hao
Skeleton for soc armada38x BUG=chrome-os-partner:47462 TEST=None BRANCH=tot Change-Id: I76f631ee6cdfc90c44727cb20aa960796bc785a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e91cc19468325f005c6ac920bbe27a174c409727 Original-Change-Id: Iac5fc34df1ba18b4515029aa2fcff8f78a5df191 Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313179 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Kan Yan <kyan@google.com> Reviewed-on: https://review.coreboot.org/13110 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04northbridge/intel/peg: Disable unused portsPatrick Rudolph
Walk the bus and try to find enabled devices. Disable the PEG port if no devices are attached. Change-Id: I67fcc831fd78ecc6dba83f4e0662ec7549cc2591 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12894 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04nb/intel/sandybridge/raminit: Fix two dimms per channelPatrick Rudolph
Issue observed: The system boots with 4G in channel 0 and 4G in channel 1. The system doesn't boot with any combination of 4G + 1G in channel 0 and 4G in channel 1. In both cases DIMM1 failed, while DIMM0 showed no issues. Problem description: The CLK to CMD/CTL was off by a half clock cycle. The find the issue I X-Y plotted timC vs timB for every lane on the failing rank. You can see an offset by 32 units for timB, that is not present on other ranks. It turns out that the XOVER CMD/XOVER CTL enable bit for DIMM1 was missing in program_timings(), which caused the clock offset. Problem solution: Add two functions to calculate XOVER CMD and XOVER CTL and use both to set XOVER in program_timings() and dram_xover(). Final testing result: The system boots with 4G + 1G in channel 0 and 4G in channel 1. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I88694c86054ade77e9d8bb2f1fdaf7bc559c1218 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13415 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04crossgcc: Add checksum for makeStefan Reinauer
I forgot to add that when I added support to buildgcc. Change-Id: I586d64805e72f9512057a4e0698bdee19cc53146 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13568 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-04crossgcc: Rename x86 to x64Stefan Reinauer
Idee4eb5d112e3f6bffced0681e9112101bed6763 has renamed the architecture by accident. Rename it back. Change-Id: I5509d2aa09df513789325bc24d9b696a09cb898f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-03lib: Support UNCOMPRESSED_RAMSTAGELee Leahy
Selecting UNCOMPRESSED_RAMSTAGE prevents lzma.c from being compiled for romstage. Adjust the logic in rmodule.c to prevent calls to the ulzma routine when UNCOMPRESSED_RAMSTAGE is selected. TEST=Build and run on Galileo Change-Id: I7409e082baab3c2a086c57ad5aa9844ba788c7cd Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13591 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-03chromeos: Sign FW_MAIN_A and FW_MAIN_BPatrick Georgi
This requires payload integration somewhere to be useful, because without that, adding it will (hopefully) break the signature. Change-Id: I67b8267e5040e26353df02d258e92a0610e19a52 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13560 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-03crossgcc: Bring back the old iasl building schemePatrick Georgi
This makes the cross{gcc,tools}-* targets build iasl again, without building it many times for cross{gcc,tools} Change-Id: I7546c2af5f7cce3a4f1a08f593fb5cbc675d69ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13564 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-03chromeos: Add Kconfig options for GBB flagsPatrick Georgi
Use the flags to preset the GBB flags field. The Kconfig defaults are chosen for a "developer" configuration. Change-Id: Ifcc05aab10b92a2fc201b663df5ea47f92439a3f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13559 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03chromeos: Create GBB at build timePatrick Georgi
The GBB contains hardware-specific data plus some configuration. The latter isn't supported by this change yet and will come later. The fields that are supported (hardware ID, bmpfv, vboot keys) are configurable through Kconfig and point to Chrome OS-style default (eg. developer keys). While adding vboot keys, the two keys used to sign RW regions are also added to Kconfig, even if not yet used. Change-Id: Icfba6061ca83182df560cd36052fbb257826d4b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13558 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03build system: Add another post-processing stepPatrick Georgi
files_added is for rules that need to run after all CBFS processing is finished, such as SoC-specific postprocessing of the image, or for vboot, to sign the RW regions (that contain CBFS that shouldn't change afterwards.) Change-Id: I830aa0c93429f4971cd68e4358faba5c206c0038 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13557 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03build_system: Extend site-localMartin Roth
- Add a target at the end of the build that can be used to run additional scripts or additional targets after coreboot.rom is built. - Source a site-local Kconfig file to allow site-specific configuration. This eliminates the need to add a hook for a script at the end of the build because you can add one yourself in site-local. Example site-local/Makefile.inc: build_complete:: ifeq ($(CONFIG_SITE_LOCAL),y) echo "Running additional steps in site-local" # run some script here to make my build unreproducible. endif .phony: build_complete Example site-local/Kconfig: menu "site-local" config SITE_LOCAL bool "site-local enabled" help Enable my site-local configuration to do stuff. endmenu Change-Id: Id4d1e727c69b5cdb05e7d52731bbb1d1e201864a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13413 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-02-03vendorcode/amd/agesa/f1{4,2,0} Sync Include directoryEdward O'Callaghan
Sync and merge useless differences. Change-Id: I4eea66c35af66d473dd56db9ccf105c878266f22 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: https://review.coreboot.org/7513 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03vendorcode/amd/agesa/f15?tn: Strip false/redudant AMD ver tagEdward O'Callaghan
Strip out the AMD internal version tag, e.g. * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ which are false/inconsistent and serve no real meaning or purpose now. Change-Id: I4cca0899eba66a1c361ba784c5ac0222b0ee1aa6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: https://review.coreboot.org/7516 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03util/kconfig:xconf(QT): Update QT version of xconfzbao
Update the qconf.cc and qconf.h to upstream code, which added support of QT5 and removed the support of QT3. All code is ported from kernel.org, with only one line added to qconf.cc. int kconfig_warnings = 0; Change-Id: Ice77cddcc00e43375039379978e55f42acf867f7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13130 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03include/device: Move inline functions from pci_def.h to pci.hAlexandru Gagniuc
pci_def.h is supposed to only contain definitions, such that it may be included in assembly files. Declaration of functions in said file prevents that. Change-Id: I0f90a74291c8a2ef7a1e1027d2d2182f896050fb Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/13300 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-03xcompile: Add a way to specify -march=i586Martin Roth
Instead of instructing users to edit xcompile when they want to build a quark platform, give the build a way to set -march=586 so that the quark code will build correctly. The Quark processor does not support the instructions introduced with the Pentium 6 architecture. Change-Id: I0ed69aadc515f86f76800180e0e33bcd75feac5a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13552 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-03crossgcc: Also add the nds32le architecture to the coreboot MakefilePatrick Georgi
Change-Id: Ibf3346586d188dbd5b7ab10bedfc1609b2bb1499 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13565 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03crossgcc/Makefile.inc: deduplicate cross*-$arch rulesPatrick Georgi
Change-Id: Idee4eb5d112e3f6bffced0681e9112101bed6763 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13524 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03buildgcc: Move all toolchain build targets to util/crossgccStefan Reinauer
There is a lot of potential to completely get rid of Makefile and keep everything in Makefile.inc, but for now this declutters the main Makefile.inc. Change-Id: I653313c74207f955514c036c81efcbfd988827c9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13518 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-03buildgcc: Reorganize when IASL is builtStefan Reinauer
Instead of passing a variable around and painstakingly making sure that one target builds with it, and the others without, make IASL a dependency of the "catch all" targets. This also drops iasl as dependency from individual architecture targets, but things are more orthogonal that way. Note: instead of `make crossgcc-i386`, use `make crossgcc-i386 iasl` Change-Id: I8cd2e89acdd0f795836571470bad28fbf8797f58 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13563 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-03buildgcc: add nds32le compilerStefan Reinauer
Some Chrome ECs are based on that architecture Change-Id: Ib5d0c2f6f518fafc1ceb02c5f71c0935d16c66bb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13562 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-03buildgcc: Rename ARM target from armv7a to armStefan Reinauer
The ARM target can compile for much more than just v7a. Change-Id: Ia4f67abcffdfe9c56c5d1848c75dfea83755e755 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13517 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02soc/intel/common: Use SoC specific routine to read/write MTRRsLee Leahy
The registers associated with the MTRRs for Quark are referenced through a port on the host bridge. Support the standard configurations by providing a weak routines which just do a rdmsr/wrmsr. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The MTRRs are displayed and * The message "FspTempRamExit returned successfully" is displayed TEST=Build and run on Galileo Change-Id: If2fea66d4b054be4555f5f172ea5945620648325 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13529 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-02Documenation: x86 Quark/Galileo remove i586 warningLee Leahy
Leverage patch 13552 by adding USE_MARCH_586 to soc/intel/quark/Kconfig. TEST=None Change-Id: Ifac947db53e967b98b9494db3f6c3f8ee039ac73 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13561 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-02Documentation: Add x86 documentation for required filesLee Leahy
Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02src: Fix various spelling and whitespace issues.Martin Roth
This fixes some spelling and whitespace issues that I came across while working on various things in the tree. There are no functional changes. Change-Id: I33bc77282f2f94a1fc5f1bc713e44f72db20c1ab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13016 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-02build system: add Chrome OS futility to toolsPatrick Georgi
Change-Id: I08925d110c6faa9e37107d63bfa75d0ab677d379 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13545 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-02-02build system: avoid setting HOSTCC to " gcc"Patrick Georgi
Change-Id: I650b3a347edc2d575c5cbee2051f8ed7b4bd1645 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13544 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-02-02commonlib: move uefi includes out of commonlib includesStefan Reinauer
... and move them into the code using them, instead. Change-Id: I2391234797ad00da8038dda198eadf0b0fcaedb2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13526 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02asus/f2a85-m: Configure Hudson to be legacy-freeLoic
Change-Id: I67271f2a209fc96eea6181f8875a5e69cf98d8c4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13511 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02amd/agesa/family15tn: Add Richland CPU IDLoic
Add the AMD A8-660K APU. Change-Id: I210a8ba962529c26a535965689672a46b09e325f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13510 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02arch/x86: Add second paragraph to license headerMartin Roth
Change-Id: Ic1da46d2abc8d20987048e4ef1e7a776d0c685d6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13555 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-02-02Makefile: Add a comment to fix syntax highlightingMartin Roth
Trivial fix for syntax highlighting in editors. Some get confused by the double quote that doesn't have a close quote and stop highlighting at that point. This comment closes the quote and the paren pair so that they can recover. Change-Id: I566e8e0f4412009f679ab079f20ae30c2049b502 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13435 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-02lint: Check license headers for both paragraphs of the GPLMartin Roth
If the GPLv2 or GPLv2+ license header is being used on a coreboot file, make sure it has two paragraphs as specified by the Common License Header section in the developer guidelines in the coreboot wiki. Change-Id: Ifffa0fa7272f5a4b129d4b7b8a515f8795bc2401 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13119 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02payloads/coreinfo: Add defaultbuild targetMartin Roth
Add a single target to do the full coreinfo build using default Kconfig values for both coreinfo and libpayload. Change-Id: Id622fb2df480e826f6d868dbe01385d76587be26 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13426 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02Kconfig: indent with tabs, not spaces.Martin Roth
Change-Id: I8996f8ab739a07014a4189738b5624485d752d9d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13540 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02src/: Fix Kcofig symbols missing CONFIG_ prefixMartin Roth
- Add CONFIG_ prefix to two symbols. - Remove the use of the third symbol as it will never be matched. Change-Id: Ifa7f6884001cb05fb8397f193c4b08a0161f498c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13539 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02lib/gcov-glue.c: Remove trailing number from COVERAGE_MAGIC macroJean Lucas
The COVERAGE_MAGIC macro has a trailing `4' on it, which makes it a 64-bit large integer, as opposed to a 32-bit unsigned integer, as originally designated in `util/cbmem/cbmem.c'. Remove this number so building with CODE_COVERAGE will succeed. Change-Id: Ib5d7f2704a4c092c3eca6f62e219edb30950d793 Signed-off-by: Jean Lucas <jean@4ray.co> Reviewed-on: https://review.coreboot.org/13520 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01cpu/amd/fam10h-15h: Add workaround for AMD Erratum 600Timothy Pearson
Change-Id: Ie175b5b490f77cc380536ebd737da8618d4b448b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13170 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-02-01mainboard/asus/kgpe-d16: Wait for all APs to stop before MCT setupTimothy Pearson
Under certain conditions when the APs are still executing during MCT setup the system can hang. This was the root cause of most of the S3 resume failures on this platform; waiting for AP stop before MCT setup allows for reliable S3 resume. Change-Id: I329eea9a8912d7b57efe6aae327d24fd6c3fd782 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13169 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-30 15:56:17 +0000