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2016-11-07pci_ids.h: Correct recent AMD ID namesMarshall Dawson
Adjust the names to match AMD's convention for family and model. This patch is relevant for: Trinity & Richland: Family 15h Models 00h-0Fh Carrizo: Family 15h Models 60h-6Fh Mullins & Steppe Eagle: Family 16h Models 30h-3Fh Change-Id: I613b84ed438fb70269d789c9901f1928b5500757 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17169 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Martin Roth <martinroth@google.com>
2016-11-07mainboard/google/reef: update DMIC related pins configurationSathyanarayana Nujella
CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be configured as native mode to use them for DMIC record on other potential DMIC's. DMIC blobs configure the clocks. For stereo & quad channel record, both CLK_A1 and CLK_B1 are enabled. For mono channel record, only CLK_A1 is enabled. BUG=chrome-os-partner:56918 BRANCH=None TEST=During DMIC record, check CLK_B1 and DATA_2 lines Change-Id: I838009b85190de5360d593238e48c9593c1dc43a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17199 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07soc/intel/apollolake: Add pmc_ipc device supportLijian Zhao
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver. The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and Punit Mailbox. BRANCH=None BUG=chrome-os-partner:57364 TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: Ib0a300febe1e7fc1796bfeca1a04493f932640e1 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/17181 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-07soc/intel/skylake: Fix SATA booting to OS issueSubrata Banik
SATA device remains unrecognized if connected at Port 2. Port control and Status register (PCS) is by default set by hardware to the disabled state as a result of an initial power on reset. OS read PCS register during boot causes disabling of SATA ports and can't detect any devices. BRANCH=none BUG=chrome-os-partner:59335 TEST=Build and boot SKL from SATA device connected at Port 2. Change-Id: I4866ca44567f5024edaca2d48098af5b4c67a7ac Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07vboot: Disable vboot verification when Chrome EC disabledNaresh G Solanki
When Chrome EC is disabled, vboot hash is not available during S3 resume Hence disable vboot verification when Chrome EC is not available. Change-Id: I665f5f0e2e53da7b735de30443d323572d8a1a9c Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17246 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07soc/intel/skylake: Avoid use of variable Local0 in TEVT in thermal.aslNaresh G Solanki
Avoid use of Local0 variable in TEVT acpi method. If mainboard doesn't expose any thermal sensor, then warning is generated for variable Local0 not been used. Change-Id: I0634961a01144e41a8480c8c6ed8b7fdd358e768 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17245 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07soc/intel/skylake: Add device id for PCH-YNaresh G Solanki
Add device id for PCH-Y used in Kaby Lake RVP3 board. Change-Id: I9235265cf88e4d044e7216f53e6da7021fb68238 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17244 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07riscv: Unify SBI call implementations under arch/riscv/Jonathan Neuschäfer
Note that currently, traps are only handled by the trap handler installed in the bootblock. The romstage and ramstage don't override it. TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux payload. It worked as much as before (Linux didn't boot, but it made some successful SBI calls) Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17057 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-07mb/lowrisc/nexys4ddr: Actually fix the UART clock setupJonathan Neuschäfer
Ron's code calculated the DLL and DLM registers of the 8250 UART, but that's the job of the UART driver. uart_input_clock_divider isn't needed anymore because the default value of 16 works. As a bonus, the baud rate can now be selected in Kconfig, instead of being hardcoded at 115200. TEST=Booted the board at 9600 and 115200 baud. Change-Id: I3d5e49568b798a6a6d944db1161def7d0a2d3b48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17188 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-06soc/intel/common: log event when MRC cache is updatedAaron Durbin
Log when the MRC cache is attempted to be updated with status of success or failure. Just one slot is supported currently which is deemed 'normal'. This is because there are more slots anticipated in the future. BUG=chrome-os-partner:59395 Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17231 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-06elog: add sources to reflect full event type namespace usageAaron Durbin
Some events were added in other places, but coreboot's elog namespace wasn't updated. As such there's a collision with the thermtrip event. This change at least updates the elog information to reflect potential event type uage. BUG=chrome-os-partner:59395 Change-Id: Ib82e2b65ef7d34e260b7d7450174aee7537b69f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17230 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-06elog: fix default elog_add_event_raw() declarationAaron Durbin
When CONFIG_ELOG isn't used default empty inline functions are provided, however the elog_add_event_raw() had the wrong type signature. Fix that. BUG=chrome-os-partner:59395 Change-Id: Iaee68440bbafc1e91c88a7b03e283fc3e72de0a3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17232 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-06Add option to use Ada code in ramstageNico Huber
If selected, libgnat will be linked into ramstage. And, to support Ada package intializations, we have to call ramstage_adainit(). Change-Id: I11417db21f16bf3007739a097d63fd592344bce3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16944 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-04reef: tune trackpad i2c frequency to 400kHzAaron Durbin
This brings the frequency down to 400kHz which is spec for fast i2c. BUG=chrome-os-partner:58889 Change-Id: Ibc5f152e55ed618f18ac6425264f086b1f2d1ffa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17215 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-04reef: tune tpm i2c frequency to 400kHzAaron Durbin
This brings the frequency down to 400kHz which is spec for fast i2c. BUG=chrome-os-partner:58889 Change-Id: I8689a062b5457aa431eaa7fb688a7170dad83fcf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17214 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-03mainboard/intel/kblrvp: Update onboard memory specific configsNaresh G Solanki
1. Update dq, dqs map & Rcomp strength & Rcomp target. 2. Fix rvp3.spd.hex byte 2 to 0x0F(JEDEC LPDDR3 memory type). Change-Id: I7efc3499b915d1e414cfe914830232993ef10ba2 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17162 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2016-11-03mainboard/intel/kblrvp: Update gpio.h, spd.h & mainboard.cNaresh G Solanki
1. Update gpio.h to set proper pad config for Kaby Lake RVP3. 2. Set spd index to zero. 3. Remove nhlt specific init. Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-03google/veyron*: change .ddrconfig from 14 to 3ZhengShunQian
There are two configs, sdram-lpddr3-hynix-2GB.inc and sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14. Changing .ddrconfig from 14 to 3 improves performance especially on contiguous memory accesses. Comparing the .ddrconfig: - if .ddrconfig = 3, C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C--- - if .ddrconfig = 14, C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C--- where - R: indicates Row bits - B: indicates Bank bits - C: indicates Column bits - D: indicates Chip selects bits .ddrconfig = 3 has multiple banks switching which improves DDR timing. BUG=chrome-os-partner:57321 TEST=Boot from fievel and play video BRANCH=veyron Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4 Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/404691 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-03google/veyron*: add DDR configs for new samsung DDRZhengShunQian
Add the new samsung DDR configs for all veyron except veyron_rialto: * K4E6E304EB-EGCE, ramid = 0010, 4GB * K4E8E324EB-EGCF, ramid = 1100, 2GB BRANCH=veyron BUG=none TEST=boot fievel board Change-Id: I747aa86f8c93174651a28face63b3386e22b23b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5f55462e71bd481eda85af3d582cfe5b9873cc9c Original-Change-Id: I19123634c994f685683323f7d85cc4d35814e2ab Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345748 Original-Commit-Queue: Ren Kuo <ren.kuo@quantatw.com> Original-Reviewed-by: Philip Chen <philipchen@chromium.org> Original-(cherry-pick from cc990f27024255a326fd9fa9644deb28b01a31a7) Original-Reviewed-on: https://chromium-review.googlesource.com/404690 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17209 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-03rockchip/rk3399: sdram.c: Fix msch ddrconfig register errorLin Huang
Fix msch ddrconfig register write error. Also make sure that the row number configured in msch is equal to the row number configured in the DDR controller. This would not affect systems with 4GB of memory, but is needed for 2GB configurations. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: Ic95b3371faec5b31c32b011c50e55e83d949e74d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dfa43d3d44839d9685b6393157f51b646e9996de Original-Change-Id: I0c95378bf937a245b7cdc0583c5d2ed1347f2a3e Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399563 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17208 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-03soc/intel/apollolake: Implement SPI flash status register readFurquan Shaikh
This was a dummy implementation until now which returned -1 always. Add support for reading SPI flash status register (srp0). BUG=chrome-os-partner:59267 BRANCH=None TEST=Verified by enabling and disabling write-protect on reef that the value of SRP0 changes accordingly in status register read. Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17205 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-02nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)"Elyes HAOUAS
Change-Id: I230b5425ac9e916a5ee10a49eeaf5d6d44fd49e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17192 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02vendorcode/amd/f14: Fix ignored argument in IDS_HDT_CONSOLEŁukasz Dobrowolski
String format required two arguments however those were packaged in ( , ) so the left one was ignored. Change-Id: I59698319d5ff4215f296356147b4e22229cc9245 Signed-off-by: Łukasz Dobrowolski <lukasz@dobrowolski.io> Reviewed-on: https://review.coreboot.org/17118 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-02riscv: Add a bandaid for the new toolchainRonald G. Minnich
After I did a new toolchain build, I found the the mhartid register value is wrong for Spike. The docs seem to agree with Spike, not the code the toolchain produces? Until such time as the bitstreams and toolchain can find a way to agree, just hardcode it. We've been playing this game for two years now so this is hardly a new approach. This is intentionally ugly because we really need the toolchains and emulators and bitstreams to sync up, and that's not happening yet. Lowrisc allegedly implements the v1.9 spec but it's PTEs are clearly 1.7. Once it all settles down we can just use constants supplied by the toolchain. I hope the syncup will have happened by the workshop in November. This gets spike running again. Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17183 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-02amd/hudson: Add PSP2 build for combo BIOSMarc Jones
The Stoney processor can use multiple directory structures. Turn this feature on in the makefile. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit a3334632fd53c07a046c9b23161f6ee67e5cb16e) Change-Id: I40a9ef2e6bed51bc339d3f9ae7c6f316192c4a78 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17149 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
2016-11-02util/amdfwtool: Increase space used for structuresMarc Jones
Double the space for psp2dir to 0x200. Based on advice from AMD, increase the region containing the signature to 4K. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit e03a9402711c3a210816d0aa32865491a0523639) Change-Id: If60132f913928bab0c2fe4aacedf342080929599 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17148 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
2016-11-02util/amdfwtool: Add PSP2 options to optstringMarc Jones
Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 482b65c219b932fd374f2ac469a023db219a66de) Change-Id: I0a24a0aa4c7d9f4a8cc3ee9b7da60ea7704e6f17 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17147 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
2016-11-02util/amdfwtool: Fix duplicate long option nameMarshall Dawson
Make the PSP2 smufirmware2 name unique so the command-line option gets picked up. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: <marcj303@gmail.com> (cherry picked from commit 98cf3880797f72aeb7169c3f8718a10092af9624) Change-Id: I5430cf8b81fb03c95e6ee9d7e53455e6224256ff Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17146 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02northbridge/amd: Modify 00670F00 chip.h to match DCTMarshall Dawson
The Stoney device supports only a single channel of DRAM with two DIMMs. Correct the dimmensions of the SPD lookup array. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: <marcj303@gmail.com> (cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8) Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17145 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-02northbridge/amd: Update 00670F00 asl for reduced hardwareMarshall Dawson
Remove the language associated with the Carrizo Gfx PCIe bridges. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit cc32b09b0f0137c11d82f35274ca33e013f73748) Change-Id: I8b67a646f98667d500fcee5da8389c10483488da Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17144 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-02northbridge/amd: Update all names and IDs for 00670F00Marc Jones
Modify the new Stoney support files to match the APU's IDs and codename. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit de626730758def76e558294762a06d8ec9950cb9) Change-Id: Idc914bc80a27ac13426fdf00fc3f578ce072086f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17143 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02northbridge/amd: Copy 00660F01 directories to 00670F00Marc Jones
Prepare for new 00670FF00 (StoneyRidge) support. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 037cf16883fafd329a15f903ddf97e24a879bcce) Change-Id: I130d4f13beb2c1d71e4e4e9be5011f7993b34660 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17142 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-02pci_ids.h: Add ID for amd/00670F00 northbridgeMarshall Dawson
Add the D18F0 device ID for the Stoney APU. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit c0fd7f70527c273bcbdce5655a21ca4de4854428) Change-Id: Ib599fc6119a3cef53f4f179c2fcd0e45905d81a4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17141 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02cpu/amd: Update files for 00670F00Marc Jones
Add StoneyRidge specific IDs, code, whitespace, and fix Makefles and Kconfig files. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 0bd1dc834792453d8e66216fa9a70afe2f7537d7) Change-Id: Id79f316a89b3baeae95e221fb872dc8a86e7b0f1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17140 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02cpu/amd: Copy 00660F01 to 00670F00Marc Jones
Prepare for new 00670F00 (StoneyRidge) support. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 87d26e05189247685df0ca6492dc3181a1bad5e8) Change-Id: Ib296ad32a061669b28dae742cac08bb75fdd0de4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17139 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-02soc/intel/apollolake: Skip FSP initiated core/MP initVenkateswarlu Vinjamuri
Enable skip FSP initiated core/MP init as it is implemented in coreboot. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I9417dab3135ca1e0104fc3bde63518288bcfa76a Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/17201 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-02soc/intel/apollolake: Disable Monitor and Mwait featureVenkateswarlu Vinjamuri
Monitor/Mwait is broken on APL. So, it needs to be disabled. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I12cd4280de62e0a639b43538171660ee4c0a0265 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/17200 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-02ec/lenovo/h8: move H8_SOUND_REPEAT downwards to it's commentAlexander Couzens
Change-Id: Ib147d90c31421c46faf99517fd07d290fd6b90a9 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/17036 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-02ec/lenovo/h8: don't load configuration when booting from s3Alexander Couzens
Some user might change some devices. After a suspend this reset to the (nvram) defaults which breaks the user expectation. Change-Id: Ifacca35210474ec3db41a53d2ad18f3798b14077 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16215 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02ec/lenovo/h8: move charge priority into own functionAlexander Couzens
Change-Id: I53c7cffd0f32f9babc5fb70d5a2440a7d3377602 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/17035 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-11-02nb/i945/gma.c: use an if else statement for use of native initArthur Heymans
Change-Id: I1e964ed939ca5282008253e3fbdd1d2fa5cbf278 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17076 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-02nb/i945/gma.c: Do not try to load vbios when selecting native initArthur Heymans
This fixes a typo introduced in 9c5fc62f: "nb/i945/gma.c: use IS_ENABLED instead of #if, #endif". Change-Id: I2c9ca796767a507483c32867f9b7f172842a1ab3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17075 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-02rockchip/rk3399: display: Do not allocate framebuffer in corebootLin Huang
framebuffer address is dynamically chosen by libpayload now, so there's no need to configure it in coreboot. CQ-DEPEND=CL:401402 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, dev screen is visible Change-Id: I9f1e581d5c63b3579b26be22ce5c8d1e71679f6f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3b6675420592c30e1e0abc8f8e9dd6ed5abd04c Original-Change-Id: I7e3162f24a4dc426fe4e10d74865cf0042c80db5 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/401401 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17109 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: sdram: Reset system if switch to index1 failsLin Huang
Near the end of DDR initialization, the system switches to the index1 configuration. Sometimes this failed and a status bit that coreboot was waiting for was never set, hanging the system. Instead, give the system 100ms to reach the new configuration or reboot it, which generally fixes the issue. Also reset when training the index1 configuration fails. BUG=chrome-os-partner:57988 BRANCH=None TEST=The error condition now leads to a reboot of coreboot which recovers the system, instead of hanging. Change-Id: Icb4270369102ff7a4ce91b0677e04b4eb10f1204 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca250d0628ea3b6b39d5131246eaba68637c5140 Original-Change-Id: Id6e8936d90e54b733ac327f8476d744b45639232 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399681 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17106 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: sdram: Fix data training functionLin Huang
1. Update write leveling value to 0x200. When the wrdqs slave delay is changed to 0x200, the phase between the dqs and the clock is 0 degrees. The pcb layout can make sure the tDQSS timing is smaller than 0.25tck, so this value is useful for both higher and lower frequencies. 2. Disable read leveling for LPDDR3. The read leveling result is unreliable - the value is not in the middle of the read eye. To fix this, disable read leveling and fix the read DQSn slave delay setting for DQn to 0x080 (1/4 cycle delay of the input signal). BUG=None BRANCH=None TEST=Boot from kevin; Check by shmoo read eye and stability test, that the updated value of 0x80 is better. Change-Id: Ia72b601d9bf4e34ba1b0b4584b2c5c3ce9dafbd4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37e8dfe783db3ce71aa026b4609ed0bfa16db06f Original-Change-Id: I2a5d40c0348449b2a7c609c1db65da4ed5f1c09f Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Jeff Chen <cym@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/396598 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/17105 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: sdram: also prepare the index1 configurationLin Huang
To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to train alternative configurations first, so do the training and store the values. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: I944a4b297a4ed6966893aa09553da88171307a42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2 Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386596 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17104 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02intel/{skylake,apollolake}: Enable signalling of error conditionPatrick Georgi
Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn returns an int (with -1 for "error"), so use int for devfn. Adapt Change-Id I7d1cdb6af4140f7dc322141c0c018d8418627434 to fix more instances. Change-Id: I001a9b484a68e018798a65c0fae11f8df7d9f564 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1357450, #1357449 Reviewed-on: https://review.coreboot.org/17054 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: Reserve enough framebuffer memory for 32bpp hires panelsJulius Werner
Some of our RK3399 devices have panel resolutions as high as 2400x1600. With 16bpp that barely still fit into an 8MB framebuffer, but then we changed it to 32bpp for better image quality... Note that this is a band-aid. Coreboot-allocated framebuffers shouldn't be used at all on ARM64 devices, since libpayload is perfectly capable to dynamically allocate it with the right size based on EDID-information on this architecture. That will require some more elaborate work to be fixed with later patches. BRANCH=gru BUG=chrome-os-partner:58044 TEST=Warm-reboot Kevin on the dev screen, confirm that you don't see the lower half of the screen that overflowed our allocated framebuffer preserved from the last boot as soon as the backlight turns on. Change-Id: I00a63cfef35a8ee734543abbdb298344fb529283 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2718efcacb50371624d9f6a3b586c298e8c2fec Original-Change-Id: Ia1fa28971c65d7d0639966e715f742309245172b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/399966 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/17108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-01google/eve: Add new boardDuncan Laurie
Add the eve board files using kabylake and FSP 2.0. BUG=chrome-os-partner:58666 TEST=build and boot on eve board Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17177 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-01soc/apollolake: Add soc core initRavi Sarawadi
Add soc core init to set up the following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST= Check C-state functioning using 'powertop'. Check 0xE2 and 0xE4 MSR to verify IO/Mwait redirection. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I99b66b02eb790b6b348be7c964d21ec9a6926926 Reviewed-on: https://review.coreboot.org/17168 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 01:32:45 +0000