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2019-04-24util/sconfig: Throw an error if override tree has no devicesFurquan Shaikh
If override tree does not have any device, then the chip info structure in it cannot be associated with the correct device and ends up being added as a standalone chip info structure without any device actually using it. This change prevents this condition by throwing an error during compilation. BUG=b:130342895 Change-Id: I7b8bb6b3228030a465976ca32ce8ef63f41365dd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-04-24mb/google/hatch/var/kohaku: Skip UART0 config in FSPFurquan Shaikh
Similar to hatch(CB:32278), this change sets SerialIo config for UART0 to PchSerialIoSkipInit to skip initialization in FSP. This change also adds a device to kohaku override tree to ensure that the settings in it take effect. BUG=b:130310626 Change-Id: Ia25b45811be26d55fc0019e4cd22eb7310b5a4c4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-24mb/google/arcada: Add settings for noise mitgationNathan_chen
Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. BUG=b:131144464 TEST=waveform test and hardware validation result pass. Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com> Change-Id: I37315ecfa245fce3085e62d1566ff037d8aa8ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32403 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mb/google/sarien: Disable POWER_OFF_ON_CR50_UPDATEKeith Short
Disable the POWER_OFF_ON_CR50_UPDATE option on sarien/arcada. This is needed so that platform properly boots after doing a Cr50 firmware update when running on battery. BUG=b:126632503 BRANCH=none TEST=Build coreboot on sarien/arcada. TEST=Perform Cr50 firmware update on Sarien, confirm the platform boots normally after sending TURN_UPDATE_ON to the Cr50. Change-Id: I0b687285eb95070eaffb68611a7d98eb8434ce2c Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-24security/tpm: Change POWER_OFF_ON_CR50_UPDATE so it can be disabledKeith Short
Modify the POWER_OFF_ON_CR50_UPDATE Kconfig option so that specific mainboard implementations can disable the option. BUG=b:126632503 BRANCH=none TEST=Build coreboot on sarien/arcada. TEST=Perform Cr50 firmware update on Sarien, confirm the platform boots normally after sending TURN_UPDATE_ON to the Cr50. Change-Id: I3beefaae21de61e53ae232dbdc8ea9dbb2c78cd5 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-24mb/google/sarien: Add power control for Sarien touchscreenEric Lai
This change will save touchscreen power leakage 2-3mW in S0iX and increase T2 display time delay to meet display panel requirement. BUG=b:129899315 TEST= Measure touchscreen power from Sarien during S0iX Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I48419132ba734f20ad5cf484c2dda609570a6dd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32330 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mb/google/sarien: Remove touch VPD support and Melfas HID touchEric Lai
Sarien will change Melfas from HID to I2C and change address from 0x10 to 0x34. So we don't need VPD to separate Elan and Melfas anymore. BUG=b:131194574 TEST=boot up and check no Melfas HID device exist Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic002f61b226743e1c18dbdbc51ce8b733916d8a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32437 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mb/google/sarien: Disable touch by strap pin GPP_B4Eric Lai
We want to disable touch for non-touch sku. We can use strap pin GPP_B4 to identify it is connected with touch or not. touch sku: GPP_B4 is low non-touch sku: GPP_B4 is high BUG=b:131132419 TEST=boot up and check no touch device exist Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If6681262c25e4b01e061a8520e38905d40345509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32438 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mediatek/mt8183: Set CPU frequency to 1989MHzTristan Shieh
Set CPU frequency from 1100MHz to 1989MHz to improve booting time. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: Id41c7ea8905c4db2537a5c32f96eb7c6b2c008ea Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32397 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mediatek/mt8183: Set processor voltage to 1.05vTristan Shieh
The maximum CPU frequency is 1417MHz with current processor voltage (0.8v). Set processor voltage to 1.05v for higher CPU frequency. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: I24ecdac2c85d3f012d9235449c0d727d727dc185 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-04-24payloads/seabios: Update the stable git hash of 1.12.1Martin Kepplinger
The Kconfig file has been updated to show 1.12.1 but this is only what gets displayed for the "stable" option. Fix this by updating the actual git hash for the SeaBIOS 1.12.1 release tag. Fixes: fb83ff1a8b ("Update stable from 1.12.0 to 1.12.1") Change-Id: I76dc0dc8b651df0c6ff6f3c02819a70bab8c04cd Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-243rdparty/opensbi: Add submodulezaolin
* Add opensbi for RISC-v Change-Id: I1a6baa6b6c05095ff5545492aabf7408a23af181 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-24mb/google/sarien: Toggle SSD reset pin on DVT2Lijian Zhao
SSD reset pin had been added on DVT2, the power sequnence requires toggle in boot stage. BUG=b:130741066 TEST=Boot up with simulated DVT2 platform and confirm SSD can be detected during warm reboot. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ie734875a49b8b61f8b813c473d30cbcaf4dd13d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32434 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mb/google/octopus: I2C clock tuning for bloogTony Huang
Tune I2C params for I2C buses 5, 6, and 7 to ensure that the frequency does not exceed 400KHz. BUG=b:131132499, b:128998988 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency under 400 KHz Change-Id: Ie8cfba72a0654402ccb0274c00b44fbfa2deea21 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23mb/google/octopus/variants/bloog: Add goodix touchscreen supportTony Huang
Add goodix touchscreen support BUG=b:131082228 BRANCH=octopus TEST=emerge-octopus coreboot and verify that touchscreen works on bloog. Change-Id: I0b3b481ca806b6452d67ace5dfe53f12a14ac3be Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-04-23soc/qualcomm/qcs405: add console.h includePatrick Georgi
Change-Id: I556d00e8b06f631a5ca51ae2b5ba646e5f536480 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32422 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23qcs405: Add support of GPIO IRQ APIsTaniya Das
Add support of GPIO IRQ APIs. Change-Id: I11715a93999012622a5e28455731cbe249ba8f2c Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23qcs405: clock: Update SPI APITaniya Das
Update SPI enable/disable and configure clock API for supporting all the blsp and qup for qcs405. Change-Id: I39622571cb671f62312283a010129ceecb654f61 Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23nb/intel/sandybridge: add pch.h includePatrick Georgi
Fixes src/northbridge/intel/sandybridge/raminit_mrc.c:286:3: error: implicit declaration of function 'enable_usb_bar' Change-Id: I48bf59c56b518477a3fc0d75902fc58df6b7def7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32400 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23soc/intel/cannonlake: add missing console.h includePatrick Georgi
Change-Id: Ic23eb57a4096d4301d7f9478d8e65aaeb233de7b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32399 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23cbfstool: Fix cbfs_file_next_attrPatrick Rudolph
The last attribute was never returned. Fix size compare to retrieve all attributes. Manually tested and seen all attributes, including the last one. Change-Id: I08df073158a0f285f96048c92aa8066fa4f57e6f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23lib/fmap: Add area read/write functionsT Michael Turney
Change-Id: I7669b8dc07b1aa5f00e7d8d0b1305b3de6c5949c Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-23linuxboot/Kconfig: Remove symbol name of a `choice`Nico Huber
Kconfig somehow adds spurious booleans for each alternative when the choice itself has a name. That's fixed simply by removing the name. Change-Id: Ic35f0697f1f7bb92c12414c17a8790464b376012 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23coreboot: Run mainboard specific code before Cr50 resetKeith Short
When coreboot checks the TPM and key-ladder state it issues a reboot of the Cr50 with a delay parameter. Older Cr50 code doesn't support the delay parameter and reboots immediately, which prevented coreboot from running the mainboard specific code needed for the AP to come back up. This change calls mainboard_prepare_cr50_reset() prior to sending the VENDOR_CC_IMMEDIATE_RESET command. This change also fixes a false error message from the coreboot log that indicated "Unexpected Cr50 TPM mode 3" when the Cr50 key ladder is disabled. BUG=b:130830178 BRANCH=none TEST=build coreboot on sarien and grunt platforms. TEST=Load Cr50 v3.15, run 'gsctool -a -m disable; reboot'. Verify corebot send the VENDOR_CC_IMMEDIATE_RESET command and that the AP boots normally. Verify event log shows "cr50 Reset Required" TEST=Force Cr50 automatic update. Verify event log shows "cr50 Update Reset". Change-Id: Ib05c9cfde8e87daffd4233114263de5b30822872 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23soc/intel/common/acpi: Add dynamic method around sleepLijian Zhao
Declare plaform level hook method before and after system sleep for possible power management related usage. BUG=N/A TEST=pass with make what-jenkins-does Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ie63711748b6dbb99d34910824f2059464543e162 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32366 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23cpu/intel/speedstep/acpi: Use get_ia32_fsb_x3() functionElyes HAOUAS
Change-Id: Ie8c5d5f7dd5b43becc144fd5e62d7de2f1ed3b80 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31432 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23configs: Add a target to buildtest the ivybridge mrc.bin bootpathArthur Heymans
Change-Id: Iff15e9586cd3e39850d986582b5943cbb8a184a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-23arch/x86/car.ld: Make the vboot tpm log symbols conditionalArthur Heymans
Without VBOOT_MEASURED_BOOT there is no need for these symbols. Change-Id: I96391b7817c79f760713c67bc469164b5514879e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23nb/intel/i945: Check if interleaved even if rank #4 size is zeroElyes HAOUAS
Tested config: Interleaved (config; status before, after): DIMM{0 + 2}: ok, ok DIMM{0 + 3}: Nok, ok DIMM{1 + 2}: ok, ok DIMM{1 + 3}: Nok, ok DIMM{1 + 2 + 3}: ok, ok DIMM{0 + 2 + 3}: ok, ok DIMM{0 + 1 + 2}: ok, ok DIMM{0 + 1 + 3}: Nok, ok Not Interleaved: DIMM{0 + 1 + 3}: Nok, Nok DIMM{0 + 1 + 2}: ok, ok (with single ranked) DIMM{0 + 1 + 2}: Nok, Nok (with only dual ranked) DIMM{0 + 2 + 3}: Nok, ok DIMM{1 + 2 + 3}: ok, ok Change-Id: Ibf130a3d4b6f8fa816f7a5f06822a9b8807be3d4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-23sb/intel/bd82x6x: fix linking for non-native raminit caseMatt DeVillier
Commit 45d4b17 [nb/intel/sandybridge: Move southbridge code to bd82x6x] moved early_pch_init() to the southbridge, but failed to include early_pch.c for the non-native raminit case, which now fails to link. As all boards default to native raminit, this was missed by the autobuilder. Adjust early_pch.c to be compiled regardles of ram init type used Test: build/boot google/stout with MRC ram init selected Change-Id: I50db30fda9a1099fb434c04ea97bcc38f8455233 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23ich7/i945: Use full_reset()Elyes HAOUAS
For full reset, use already defined full_reset() function. Change-Id: Iec7dcf285f3cb1cdc8f48d348ff8496879625db5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23sb/intel/lynxpoint: Enable LPC/SIO setup in bootblockArthur Heymans
This allows for serial console during the bootblock and enables console in general for the bootblock. Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30315 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23soc/amd/common: Remove AmdReadEventLog()Kyösti Mälkki
Parameter passing is incorrect here, it should pass complete StdHeader instead of attempting to fill in HeapStatus that should be treated as a field private to AGESA, based on where it is defined in the header files. Furthermore the while() loop did not evaluate the return value. Feature can be brought back at a later date after someone verifies it actually works correctly across different stages. Change-Id: Ib243b275f8700ecaeb330772c795d305c61899c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31484 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23soc/amd/common: Introduce agesa_execute_state()Kyösti Mälkki
Each entrypoint to AGESA goes through the same sequence and have same the function signature. To avoid introducing bunch of preprocessor magic, rename all the agesawrapper_amdXXX() functions that are actual entrypoints to AGESA API, make them static, and provide a single exposed entry function agesa_execute_state(). Change-Id: I96ae1874132da3843aa42c2f4e8a59ec771d3893 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31483 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23mb/google/sarein: Add power control for Arcada touchscreenRoy Mingi Park
This change will save touchscreen power leakage 2-3mW in S0iX and increase T2 display time delay to meet display panel requirement. BUG=b:129899315 TEST= Measure touchscreen power from Arcada during S0iX Change-Id: I4b8f3fdc0d107b080c5febe6fa5d29ea5d1ed0fc Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23smbios: Add memory type 9 system slot supportLijian Zhao
Add SMBIOS type 9 system slots into coreboot, the definiation is up to date with SMBIOS spec 3.2 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23soc/intel/cannonlake: Enable PlatformDebugConsent by KconfigKane Chen
This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_CANNONLAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details. BUG=b:130203864 TEST=boot ok and PlatformDebugConsent can be controlled by Kconfig Change-Id: Ib845b5e42bc78fb352a0c97c6301f2aeca522f29 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32297 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23soc/intel/common: Add SOC_INTEL_DEBUG_CONSENT to control debug interfaceKane Chen
SOC_INTEL_DEBUG_CONSENT config is generally to enable default debug interface of SoC. Ex: USB DBC, DCI debug interface on cnl, whl, cml. Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32337 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl codeFrans Hendriks
Linux remains using SPI1 and PWM ASL even if these devices are disabled. SPI1 and PWM are disabled by Intel FSP. Remove ASL code. BUG=N/A TEST=Boot Ubuntu on Intel CherryHill CRB Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-04-23ACPI: Clarify serial bus revision and specific revisionElyes HAOUAS
Serial bus revision [Byte 3] and serial bus specific revision [Byte 9] are not the same. Change-Id: I366f62e6aa0e9c0dfbc1ec17adeebc42a0e777eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23nb/intel/sandybridge: Drop pch.h from sandybridge.hPatrick Rudolph
Include pch.h in the source files instead in sandybridge.h. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23soc/intel/cannonlake: Add null reference check for Cnvi and XdciAamir Bohra
Change-Id: I2e1011d9ac93ed764b6c2aa425928a972ec2aa43 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32322 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23crossgcc: Update acpica to version 20190215Elyes HAOUAS
Support for ACPI specification version 6.3: Add PCC operation region support for the AML interpreter. This adds PCC operation region support in the AML interpreter and a default handler for acpiexec. The change also renames the PCC region address space keyword to PlatformCommChannel. Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG. These methods provide OSPM with health information and device boot status. PDTT: Add TriggerOrder to the PCC Identifier structure. The field value defines if the trigger needs to be invoked by OSPM before or at the end of kernel crash dump processing/handling operation. SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT is used for describing devices such as heterogeneous processors, accelerators, GPUs, and IO devices with integrated compute or DMA engines. MADT: Add support for statistical profiling in GICC. Statistical profiling extension (SPE) is an architecture-specific feature for ARM. MADT: Add online capable flag. If this bit is set, system hardware supports enabling this processor during OS runtime. New Error Disconnect Recover Notification value. There are a number of scenarios where system Firmware in collaboration with hardware may disconnect one or more devices from the rest of the system for purposes of error containment. Firmware can use this new notification value to alert OSPM of such a removal. PPTT: New additional fields in Processor Structure Flags. These flags provide more information about processor topology. NFIT/Disassembler: Change a field name from "Address Range" to "Region Type". HMAT updates: make several existing fields to be reserved as well as rename subtable 0 to "memory proximity domain attributes". GTDT: Add support for new GTDT Revision 3. This revision adds information for the EL2 timer. iASL: Update the HMAT example template for new fields. iASL: Add support for the new revision of the GTDT (Rev 3). More changes in this version at https://acpica.org/node/166 Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-23crossgcc: Update CMake to version 3.14.2Elyes HAOUAS
Release Note : https://cmake.org/cmake/help/v3.14/release/3.14.html "The FindFontconfig module added by 3.14.0 accidentally used uppercase FONTCONFIG_* variable names that do not match our conventions. 3.14.1 revises the module to use Fontconfig_* variable names. This is incompatible with 3.14.0 but since the module is new in the 3.14 series usage should not yet be widespread" Change-Id: Ief7f5e8309597093f061789926bd3bd2ed3aec2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23crossgcc: Upgrade GCC to version 8.3.0Elyes HAOUAS
Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-23sb/intel/i82801gx/lpc: Use {read,write}_pmbase32 and lpc_get_pmbaseElyes HAOUAS
Also use macros instead of magic numbers. Change-Id: I00bd687c487894c72d4e4363774dbcdfaf62dd54 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_configArthur Heymans
The pci_or_configx function makes the code shorter and more readable. Change-Id: Ic1ba250f8ac9fb75cf3252aec18af80842bda7dd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 04:55:24 +0000