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2014-06-21cpu/amd/agesa: Use acpi_is_wakeup()Kyösti Mälkki
Change test to return true on S2 wakeup too. In S2 CPU would have been powered down so MTRR recovery is required. Change-Id: I6ad5fb7e32c59be7d84f28461c238c3975e1e04e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6078 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21AMD cimx/sb800: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: If237c2fcd52f50d5fa0cad5a02a941386b085f2e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6077 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21northbridge/amd/agesa: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: Ia6f5b0454e7fbbf36baa2372dfeec51b5f5e8f67 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6076 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21PCI VGA ROM: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: I6f9c992f1a68025ed18de57c5856b3bf9a673bfb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6075 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21PC80 RTC: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: Idc4c47f3802019c2853ec71f8e9c057c3ab8d3ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6074 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21PS2 keyboard: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: I812cc40e50a1e7e13caed48a1693feb8658b645c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6073 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21Misc: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: I46906e6d68775edc5cfe199cfeb465db4da2691f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6072 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21intel boards: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6071 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21superio/smsc/fdc37n972: Trivial cleanup reorder headersEdward O'Callaghan
Alphabetise headers and a few trivial cleanups. Change-Id: Ib8c8362962297cb59671d8274df8e4945373f94b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6042 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-20superio/nuvoton: Add chip support for setting IRQs to edge/levelDave Frodin
Change-Id: I08b9eef9d6b0f120c17c3293f1f90b847742dc06 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/6064 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-20superio/nuvoton: Adds a function to route pins 41-48 to UARTDDave Frodin
Pins 41-48 default to being GPIs. This switches the internal mux to connect them to UARTD. Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/5963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20southbridge/intel/lynxpoint/me_9.x.c: Use IS_ENABLED macroEdward O'Callaghan
Silence unused function warnings, spotted by Clang. Change-Id: I5127893e9605ca490ff450faa92af5e9eafe8940 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6054 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-20superio/ite/it8772f: Remove prototypes for func with no bodyEdward O'Callaghan
Change-Id: Iaf5db7153b08ac81b233f967c7a604ed08af91ca Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6040 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-20src/mainboard/google/*/mainboard_smi.c: Remove #include .c'sEdward O'Callaghan
No need for these. Change-Id: I1df6e2ef06bd5546a66ee05a15fa2f7c3daf8853 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6039 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-20google/link, lenovo/x60: i915io.c: Use define `ARRAY_SIZE`Paul Menzel
Change-Id: I8ddd46a573b61eba685efcc15456f288645d214d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5936 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-20mainboard/jetway/nf81-t56n-lf: Port recent Persimmon changesEdward O'Callaghan
Port to recent reference board (AMD Persimmon) changes in commits: c93a75a AMD/CIMx: Add functions for AMD PCI IRQ routing Change-Id: I307709bfee554bc64788a973da6d9313ca7c0de2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5882 Tested-by: build bot (Jenkins) Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
2014-06-20ACPI: Add acpi_is_wakeup_s3()Kyösti Mälkki
Test explicitly for S3 resume. Also switch to use IS_ENABLED(). Change-Id: I17ea729f51f99ea8d6135f2c7a807623f1286238 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6070 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20sandy/ivy boards: Use acpi_s3_resume_allowed()Kyösti Mälkki
Change-Id: I8e0d43293e095c1c76c3cfef1f426737624ea37f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6063 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-20nehalem boards: Use acpi_s3_resume_allowed()Kyösti Mälkki
Also update packardbell/ms2290 to match lenovo/x201. Change-Id: I6bda740cadd81ebe47e57742c507bff322a9fb0e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6062 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-20intel/i945 gm45: Use acpi_s3_resume_allowed()Kyösti Mälkki
Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6061 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-20ACPI S3 support: Add acpi_s3_resume_allowed()Kyösti Mälkki
Add this to reduce the amount of preprocessor conditionals used in the source, compiler currently resolves this to a constant. Once we have gone through all #if CONFIG_HAVE_ACPI_RESUME cases, we may change the implementation to enable/disable S3 support runtime. Change-Id: I0e2d9f81e2ab87c2376a04fab38a7c951cac7a07 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6060 Tested-by: build bot (Jenkins)
2014-06-20util/cbmem: Workaround for IS_ENABLED()Kyösti Mälkki
Our include files reference CONFIG_xxx declarations, which we should ignore for utility build. We cannot include kconfig.h to get IS_ENABLED() as that file would require build/config.h and we do not want to enforce a build of the firmware to be able to build the utility. Since we do not include build/config.h each occurence of CONFIG_xxx in the included header files is undefined and will be treated as disabled. Change-Id: I74f1627fc3f294410db8ce486ab553dac9e967f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6066 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20src/lib/clog2.c: Fix style and clarity, remove some cruftEdward O'Callaghan
Change-Id: I6b37cf945db12d2cf8096c9f49fff9e0bec139d6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6058 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-20drivers/intel/gma: Equality comparison with extraneous parenthesesEdward O'Callaghan
Spotted by Clang. Change-Id: I3e612c0fa050a09fa7e5b1cb643935b84eb2b957 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6053 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-19supermicro/h8scm: Fix KconfigKyösti Mälkki
Change-Id: I0ecc3c5a26251f248234244bf305d3e13e41b9e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6069 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-18intel/bayleybay_fsp: Drop redundant EARLY_CBMEM_INITKyösti Mälkki
This is implied from DYNAMIC_CBMEM from soc/. Change-Id: I8cd8c2dff723950377998750377a3168f1f5fc5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6029 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-18fsp_baytrail: Add the default FSP locationMartin Roth
The default FSP location needs to be in the chipset, not the mainboard. This was removed from the Bayley Bay mainboard in patch 41ea7230f7 reviewed at http://review.coreboot.org/#/c/5982/ Change-Id: Ia26ed34e1401cbd2303166628e7a4e357d79c874 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5985 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
2014-06-18fsp_baytrail: Add Baytrail B0/B1 "Super SKU" microcodeMartin Roth
- Add the Bay Trail B0/B1 microcode. These versions of the SOC were released as a "Super SKU" which had features of all the different SKUS (M/D/T/I), and identified as a Bay Trail T as noted by the number 2 in the third character from the left in the microcode name. - Update the size of the microcode blob. We should be pushing a patch to eliminate the need for this shortly. Change-Id: I57ba51eabe9ea0609ab809f18b95e3bc9d5cb191 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5986 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-18mainboard: Clear up remaining SIO_PORT from KconfigEdward O'Callaghan
Push back any board specific values back into romstage.c #defines and drop any remaining fragments of CONFIG_SIO_PORT in-tree. Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6045 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-18mainboard/amd,lippert: Drop SIO_PORT from KconfigEdward O'Callaghan
CONFIG_SIO_PORT is not used anywhere and should not be here any way. Change-Id: I39eb2d668f1da9f89b7ff6eb219af1a48cb29232 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6044 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-18mainboard/jetway/nf81-t56n-lf: Drop SIO_PORT from KconfigEdward O'Callaghan
CONFIG_SIO_PORT is not used anywhere and should not be here any way. Change-Id: I2e7be4337f7f46298b9ca5bd613c58deec2cb01a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6043 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-18ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM. Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6032 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-18northbridge/intel: Drop use of set_top_of_ram()Kyösti Mälkki
We implement get_top_of_ram() on these chipset to resolve CBMEM location early in romstage. Call to set_top_ram() is not required. Change-Id: I492e436b0c32d2c24677265b35afd05f29dcd0f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6031 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-18intel/nehalem: Add get_top_top_ram() in ramstageKyösti Mälkki
Needed to resolve CBMEM location early in ramstage. With DYNAMIC_CBMEM set_top_of_ram() will no longer be available. Change-Id: If50f1c5455a587b096348ffedadbe1dd2350a714 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6030 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-06-18emulation/x86 : Drop HAVE_ACPI_RESUMEKyösti Mälkki
S3 resume detection not implemented in romstage.c. Change-Id: I98277cb483825af2e6c5c8eefa4598b117613478 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6028 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-18mainboard/supermicro/h8dme: Drop unused codeKyösti Mälkki
Clang complains about a unused debug function, so remove dead code. We have copy of dump_smbus_registers() in amdk8/debug.c. Change-Id: Ibf46deb1de1589d81760841b1d4ba319707915aa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5942 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-06-18lenovo/x60: Fix build issue with DO_NATIVE_VGA_INITKyösti Mälkki
Use the value from hardware for uma_memory_base. Change-Id: I70351166db6634ef3bca2bf12051ccc3730cab8e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5893 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-17intel/model_2065x: Add 20652 microcode.Vladimir Serbinenko
Change-Id: I2a46806a3f0a57497edebd49e69b97f90948adb9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5117 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-16Persimmon: Change MPTable to use mainboard IRQ routingMike Loptien
With the addition of the mainboard PCI IRQ routing tables for AMD Persimmon, the MPTables can be set to use this information to accurately reflect the real hardware settings of the system. Additionally, the IOAPIC gets defined before the MPTable gets generated so the settings can be read directly from the IOAPIC registers instead of 'guessing' at them as was done before. Change-Id: I96ec046a2208eddf4b5e442214ff43d2a349ca4d Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/5878 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-16MP Spec: Correct the Virtual Wire assignmentMike Loptien
Virtual Wire mode is set by writing 0 to the the MPTable Feature2 bit field 'IMCR'. The virtualwire variable was initially defined as writing a 1 to this bit field which would actually set PIC mode instead of Virtual Wire mode. However, nearly every mainboard called the MPTables with virtualwire = 0, which actually had the effect of setting Virtual Wire mode. I am correcting the definition but leaving the call to write the MPTables with virtualwire = 0, which is how most mainboards are already setting the tables up. See the MP Spec table 4-1 for more details: Bit 7: IMCRP. When the IMCR presence bit is set, the IMCR is present and PIC Mode is implemented; otherwise, Virtual Wire Mode is implemented. http://download.intel.com/design/archives/processors/pro/docs/24201606.pdf Change-Id: I039d88134aabd55166c2b68aa842bacbfcc0f42b Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/5977 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-16MP Spec: Add copyright headerMike Loptien
Adding the copyright header to the MP Spec files because they were not included before. Change-Id: Ifcd217a53bf8df19b28e251a7cac8b92be68d1fc Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/5981 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14amd/agesa,cimx: Rename ACPI OS detection methodsEdward O'Callaghan
Try to 'standardize' the otherwise peculiar method naming to be somewhat more in-line with other ACPI implementations. This makes it easier to compare with vendor DSDT dumps for example. Change-Id: I5ba54f7361796669ac0cab7ff91e7de43b22e846 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5888 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14amd/agesa/f15tn: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: I87bf101b15bac7c06afa9cec10e2bd4e0cdfd6c7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5941 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14mainboard/ibase/mb899: Break out superio hwm conf from mainboardEdward O'Callaghan
Break out the PNP Super I/O HWM configuration from mainboard.c Change-Id: Ib4c7f26c7fa2a9845250a61a23c75cb9e440ab93 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5797 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14amd/agesa/f14: Backport f15tn fixes from DDR3 in mtspd3.cEdward O'Callaghan
Change-Id: I710efc3171e1653241f2dba1217a9560d2d99a16 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5802 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14mainboard/amd: De-ASCIIartify reference boardsEdward O'Callaghan
For anyone who knows the difference between a header and a variable in C these depictions are rather useless. Thus, these lines wast essential screen real estate while working on coreboot. Change-Id: I7fe55d936c035ef83832716c45bfc57d73c0edc7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5979 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-13fsp_baytrail: remove version from default vbios pathMartin Roth
Intel requested that we remove the version number from the default vbios path. Change-Id: I2590fed0db157e3e430212336fc55eb099d28a72 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5984 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-13fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOTMartin Roth
While pushing the fsp_baytrail code, it was requested that we change CONFIG_ENABLE_FAST_BOOT to CONFIG_ENABLE_FSP_FAST_BOOT. These were missed in the change. Change-Id: If8af3f90b0f5cc9154ff1d3a387f442430f42dee Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5972 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-13mainboard.c: Fix typo in appro*p*riate in commentPaul Menzel
Use the following command to fix all occurences. $ git grep -l approriate | xargs sed -i 's/approriate/appropriate/g' Change-Id: I4cbba972bb445c2407ef2e63ffb3068fc948f1c6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5987 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-12southbridge/amd: Change #if defined to #if IS_ENABLEDDave Frodin
The IMC functions were being called and timing out when the CONFIG_SB800_IMC_FWM/CONFIG_HUDSON_IMC_FWM were defined as 0. Changing to a IS_ENABLED will keep the IMC handshake from occuring if the IMC firmware isn't running. Tested on a Persimmon platform which makes three calls to spi_claim_bus() with each call timing out after 500ms. Change-Id: I5d4bbcecf003b93704553b495a16bcd15f66763b Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/5974 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 22:03:28 +0000