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2016-01-13intel/northbridge/sandy: raminit code cleanupPatrick Rudolph
Remove redundant call to dram_mrscommands(). Change-Id: I157915b4432093c556b538433e3337db1e9c525f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12891 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13[WIP] mb/roda/rk9: Enable CONFIG_HAVE_ACPI_RESUMENico Huber
Change-Id: Ifa7dd593f70921a99d937104960e26100de28089 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12421 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13northbridge/intel/x4x: clean up includesMartin Roth
- Don't redefine D0F0_PCIEXBAR_LO, use the #define in x4x.h - Move TPMBASE and TPM32() definitions into iomap.h - Use "" style include for x4x.h in nortbridge files. - Move includes of .h files out of x4x.h and into the c files that need them. - Protect function definitions in bootblock. Change-Id: I3fdb579235c5446733a0ffba05fffe1a73381251 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13cbfstool: Remove duplicate code lineWerner Zeh
Remove duplicate line which sets baseaddress parameter. Change-Id: Idfbb0297e413344be892fa1ecc676a64d20352bf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/12904 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-12util/lint: Add lint script to run kconfig_lintMartin Roth
The lint target in the makefile relies there being a script using this particular naming format, so add a shell script front end to run the kconfig linter. Change-Id: I029c1cd3bbf3837c9f1d86c391ae5cabfa53685d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12903 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-12util/lint/kconfig_lint: Run through perltidy to fix whitespaceMartin Roth
Change-Id: I7f04156fff0b65ea262b12961ce76ef329d358ab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12902 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-12lint: rename lint-006-checkpatch because board name is lint-006Martin Roth
Checkpatch should be 007. Change-Id: Ib71c50ad1a63a3a743391cd8fea9f79cd08ef6f3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12901 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-12Makefile: Add toolchain version checkMartin Roth
This is an initial check for the coreboot toolchain versions. It currently checks binutils, gcc, clang, and iasl. The other components are slightly more difficult to test, but should follow on shortly. If the toolchain is not the correct version, make will halt with an error. Change-Id: I41daf6c4545c01dc21231d78fd081bbcf77c4726 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12846 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins)
2016-01-12amd/cimx/sb800/pci_devs.h: Update guard #define nameMartin Roth
Change-Id: Ieae41cab97293831a0c49c3b472b9e6c62ba36c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12899 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-01-12intel/skylake: Remove check for Microcode loaded by MEMartin Roth
This method of reporting has been removed from the current Skylake ME binaries so is no longer needed. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-12google/guado: initial upstream migrationMatt DeVillier
Migrate google/guado (Asus Chromebox CN62) from Chromium tree to upstream, using google/auron and google/panther as refs. TEST=built and booted guado with full functionality Change-Id: If7a500fb408197a61c9619b9d5ea1458d1f4d702 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12800 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-12Makefile: Correct spelling in help messageWerner Zeh
Correct wrong spelled "subnit" in help message. Change-Id: Iadbf483835ee4c1b6e3faa454d1cae2660b99c5e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/12905 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-12nb/intel/gm45: Convert gma.c to `if (IS_ENABLED(` styleNico Huber
Change-Id: Ifae3822b6c28832f6aa05a4ffd8f02067a923f2c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12883 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-11autoport: Add missing castsVladimir Serbinenko
Change-Id: I04abdd48f5e2440756f9b03041d46c773f200368 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/12890 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-10fsp1_1: Remove #if protection in header - It's not neededMartin Roth
There's nothing in these files that needs to be hidden if GOP support is disabled. Removing this allows skylake to build when GOP support is turned off. Change-Id: I2a4f47cd435f48668311719f388b502ae77eca99 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12859 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-01-10lenovo/x220: Enable USB 3 controllerMarian Tietz
Since only X220 with i7 have the USB3 controller this was probably overlooked. Before this patch lspci on Linux would not show the NEC USB 3 controller as well as the PCI bridge it is behind. After, both the bridge and the NEC controller can be found in the output: 05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 04) Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331 Signed-off-by: Marian Tietz <mtcoreboot@gmail.com> Reviewed-on: https://review.coreboot.org/12882 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-01-09buildgcc: Print out all missing tools then haltMartin Roth
Instead of printing out a single tool that needs to be installed each time buildgcc is run, print out the entire list of tools to be installed, then halt. Change-Id: I7761760eef3c45ba371f882a4f987408945bb3e5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12856 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-08vendorcode/amd/agesa/f15tn: Fix out of bounds read on on memory voltageMartin Roth
I think this has a fairly low likelyhood of happening, but if AGESA can't determine the voltage of the memory, it assignes a value of 255 to the variable that it later uses to read from an 3-value array. There is an assert, but that doesn't halt AGESA, so it would use some random value. If the voltage can't be determined, fall back to 1.5v as the default value. Fixes coverity warning 1294803 - Out-of-bounds read Change-Id: Ib9e568175edbdf55a7a4c35055da7169ea7f2ede Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12855 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-08fsp_baytrail: Add additional PCI space above 4GBMartin Roth
This just tells the OS that it can use the 16GB of address space at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit physical address space. This could be hardcoded into the UMEM definition, but doing it this way makes it more plain what it's doing, and allows for modification to put it just above the top of upper memory, similar to what is done with the standard PCI region above the top of low memory. Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12791 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-01-07intel/braswell: Disable IFD & ME by default so abuild can buildMartin Roth
The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so disable them by default for now. Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07mainboard: Drop abuild.disabled files for Braswell boardsStefan Reinauer
Make sure the latest & greatest Intel targets actually build in our build system. Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12463 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07buildgcc: Don't request that optional tools be installedMartin Roth
Previously, when we tested for g++ and two different versions of clang, if the earlier versions were not found, buildgcc would still request that they be installed. This obviously isn't needed, and isn't the desired outcome. Now, if one of the first tests fails, nothing gets printed. If all the tests fail, it tells you to install either g++ or clang. Change-Id: I71359f59c4c6bee3c3c55e4e6105f11e6ca51527 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12852 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07src/vendorcode/amd: correct spelling of MTRRPaul Menzel
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/4806 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-07f14: Increase AP stack to 8k on 64bitStefan Reinauer
This has been broken out from http://review.coreboot.org/#/c/10581/ Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://review.coreboot.org/11025 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07google/cyan, intel/strago Kconfig: Only ask to display SPD onceMartin Roth
Change-Id: Ic3df9bf7d7f3c4c39789f3f496bcb7fc2ee50931 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12827 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Quote variables to prevent globbing and splitting.Martin Roth
Quoting variables prevents word splitting and glob expansion, and prevents the script from breaking when input contains spaces, line feeds, glob characters and such. See shellcheck warning SC2086 Change-Id: Ib6ca46b64a621c4bea5c33ac312f2824b0386235 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12845 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Use local variables in the test functionsMartin Roth
Using the local variables instead of positional parameters helps readability. - Add and use the local variables in testcc. - Use the existing local variables in testld. Change-Id: Ice13288b830a7aa043b360eaee8e36f060589a18 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12844 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: use $() instead of backticksMartin Roth
While the backtick syntax isn't actually deprecated, the $() syntax is preferred. Since both styles were being used in this script, settle on the new standard for all cases. Change-Id: I33770d666781b4fa34c909411e0d220c2540dbb4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12843 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Only include arm64 erratum check in arm64 sectionMartin Roth
Clean up the output file a bit by only including the erratum for arm64 into the that architecture section instead of every architecture. Change-Id: Ib6276f12aee5deb92a03e1c4fa2ad57db46bdc8f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12842 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Put compiler variables outside of 'if' to allow checkingMartin Roth
In order to be able to check the compiler versions, we need to be able to access the compiler variables. Move the original assignments outside of the GCC check, and assign either the GCC or CLANG compiler to the actual CC_ environment variable later. This ends up with the same value set, while allowing the compiler versions to be checked. Change-Id: Iffad02d526420ebbdfb15ed45eb51187caaa94fb Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12841 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Separate flags from clang executableMartin Roth
We already have a CFLAGS variable - Use it for all of the flags. Change-Id: I22b4c5cf24b8743e85ffab29ddcccdc6c732ea3b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12840 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Add XGCCPATH to clang compilerMartin Roth
The XGCCPATH prefix is on all the other tools and compilers, so add it to clang as well, so it can be found correctly. Change-Id: Ibc250a81433f37bbb0555d32605aebe3a68aaf40 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12839 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Add separation for architectures to improve readabilityMartin Roth
- Add bar at the top of each architecture - Make the architecture name and the TARCH_SEARCH to two lines - Add a second line at the bottom of each architecture - Add a comment about the two blank lines so they don't get accidentally removed. Change-Id: Ib4326bd94fe39b979244816ce54b752d083f6b16 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12838 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Use tabs for indentationMartin Roth
Change-Id: I96a5048050f8016c3c569f20318b4d421a4470a7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12837 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07Makefile.inc: update location of dsdtMartin Roth
The dsdt file moved from the mainboard directory to the top level of the build directory. Remove it from the new location when cleaning. Change-Id: If9f72c78e5c03e0db384b3181c169aa2ecbb5c18 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-07intel/fsp1_1: Disable GOP support by defaultMartin Roth
Since the GOP drivers aren't published in the 3rdparty blobs repo yet, disable the GOP support for now so that abuild can build these platforms. Change-Id: Ic98671c163b433ebde89c8bf240ef4b2be393586 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12829 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07mainboard/asus/kgpe-d16: Enable romstage microcode spinlocksTimothy Pearson
Change-Id: I93687efc5405359286d3197f0e59ec3b118c5100 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12809 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failureTimothy Pearson
When microcode updates are enabled, this fixes an issue identical to that described in GIT hash 7b22d84d: * drivers/pc80: Add optional spinlock for nvram CBFS access Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12063 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07inteltool: add NetBSD compatibilityAndrey Korolyov
Tested on NetBSD-7.0/i386 Change-Id: I6a693633d3a80ea07ade233b1b4fd1c5a1412032 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/12835 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07viatool: add NetBSD supportAndrey Korolyov
Change-Id: I033044e4b781475d6d60a49a61313a720103ce38 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/12836 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-07Revert "util/crossgcc: Regenerate MPFR autotools files before build"Timothy Pearson
This reverts commit 68d0e4a5a1e7028227f6fbe086c891955cb7854e. Special handling of MPFR is no longer needed with the latest MPFR release. Change-Id: I96d9ea92cfb74eed6af2ba62254f0678081e2b4f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12833 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07util/crossgcc: Bump MPFR version to 3.1.3Timothy Pearson
The current MPFR version contains a stale config.guess file that requires special handling on ppc64el systems. Bump the MPFR version to the latest release. Change-Id: I5e86c732c09f8a6a43f9812452124d64d337ea3f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12832 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06viatool: Add VIA C3 MSRsAndrey Korolyov
Tested on C3/EPIA board and Linux x86 Change-Id: I8df551f4b385ee8702af78df00169bdc8e180925 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/12851 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-06cpu/amd/fam10h-15h: Add tsc_freq_mhz() functionTimothy Pearson
The AMD Family 10h/15h processors use a TSC that increments at the P0 core frequency. Allow coreboot to query the TSC frequency. Change-Id: I73ead4fd4af18991452d59985b667a54689778cd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12834 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-06cbfstool: correct add-master-header logic to match runtime expectationsAaron Durbin
The cbfs master header's offset and romsize fields are absolute values within the boot media proper. Therefore, when adding a master header provide the offset of the CBFS region one is operating on as well as the absolute end offset (romsize) to match expectations. Built with and without CBFS_SIZE != ROM_SIZE on x86 and ARM device. Manually inspected the master headers within the images to confirm proper caclulations. Change-Id: Id0623fd713ee7a481ce3326f4770c81beda20f64 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12825 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-06Revert "x86: Align CBFS on top of ROM"Aaron Durbin
This reverts commit 65e33c08a9a88c52baaadaf515b9591856115a77. This was the wrong logic to fix the master header. Change-Id: I4688034831f09ac69abfd0660c76112deabd62ec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12824 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-06intel/braswell: Build in both C0 and 'other' vbiosMartin Roth
The Braswell CPU seems to have two different Video BIOS roms, one for the C0 revision, and one for other revisions. Build them both into the coreboot image, and let coreboot sort out which one should be used at runtime. This should allow one rom to be used for all revisions. The initial reason for this patch was that the Kconfig symbol C0_DISP_SUPPORT didn't exist, and was causing issues. This seems like the best way to eliminate the need for that symbol. Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12826 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06Documentation: Add information about patches from other git reposMartin Roth
This is more tribal knowledge that I don't think I've seen written down anywhere else. It's not a huge issue, but when looking through the git log, it helps to be able to differentiate the information from the old gerrit with the information from the new one. Change-Id: I7993bda1e9aab79dc26940aaba9ddc52382ed0df Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12804 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06cbfstool: Add 'hashcbfs' command to compute hash of CBFS region.Aaron Durbin
For the purposes of maintaining integrity of a CBFS allow one to hash a CBFS over a given region. The hash consists of all file metadata and non-empty file data. The resulting digest is saved to the requested destination region. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Integrated with glados chrome os build. vboot verification works using the same code to generate the hash in the tooling as well as at runtime on the board in question. Change-Id: Ib0d6bf668ffd6618f5f73e1217bdef404074dbfc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12790 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-07 05:30:59 +0000