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2018-08-14ifdtool: port the feature to set AltMeDisable/HAP bit hereBill XIE
Port the newest feature of me_cleaner to ifdtool (https://github.com/corna/me_cleaner/ , Discussed in https://github.com/corna/me_cleaner/issues/53 ) to set AltMeDisable (or HAP for skylake/ME11) bit to the IFD to disable ME. In this commit I use (ifd_version >= IFD_VERSION_2) to judge whether HAP instead AltMeDisable should be set, since this condition is only fulfilled on skylake or newer platforms. This feature needs to guess ich revision, which needs guess_ich_chipset() from flashrom to be ported here. Routines to dump those bits are also added. Change-Id: I9a2ecc60cfbb9ee9d96f15be3d53226cb428729a Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-14sb/intel/i82801[ij]x: use (more) RCBA register names instead of magic numbersStefan Tauner
Change-Id: I909d7dd4968aa2f76df00c03e603e8e82a4824c0 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-14cbmem: rename vdat to chromeos_acpiJoel Kitching
There is a confusingly named section in cbmem called vdat. This section holds a data structure called chromeos_acpi_t, which exposes some system information to the Chrome OS userland utility crossystem. Within the chromeos_acpi_t structure, there is a member called vdat. This (currently) holds a VbSharedDataHeader. Rename the outer vdat to chromeos_acpi to make its purpose clear, and prevent the bizarreness of being able to access vdat->vdat. Additionally, disallow external references to the chromeos_acpi data structure in gnvs.c. BUG=b:112288216 TEST=emerge-eve coreboot, run on eve CQ-DEPEND=CL:1164722 Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/27888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-14mb/google/poppy/variants/nocturne: Update PL1/PL2 for AMLRoy Mingi Park
This patch updates Power Limit (PL) for AML. - PL1 as 5W TDP as POR - PL2 as 18W TDP as POR BUG=None BRANCH=None TEST=Build coreboot for Nocturne board and check default PL1/PL2 TDP. cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_0_power 5000000 (5W TDP) cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_1_power 18000000 (18W TDP) Change-Id: Icb02a8a7c5fcd5e6aee45f14eba540a6b3ed3d67 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/27427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-14mb/google/poppy/variant/nami: Add TSR2 on DPTFT.H. Lin
Add TSR2 DART/DTRT package BUG=b:110451144 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test image with dptf.dv Change-Id: I3328e17328415f5ebdcf84263e5456e11e55f769 Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-14mb/google/octopus/var/bobba: Update GPIO config for bobba bid >= 1Justin TerAvest
This change updates GPIO configuration for bobba boards with id >= 1 This follows the same model as fleex: a. Dynamically update touchscreen power enable GPIO in devicetree. b. Provide default and bid0 tables for GPIO configuration in ramstage. c. Configure WLAN enable GPIO differently in bootblock based on boardid. BUG=b:112354568 TEST=Built firmware for bobba Change-Id: Id4ee4a1815e16ddfe60ed268688a8aaf4fb75579 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/28071 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-14mb/intel/coffeelake: Enable 32MB rom compilation for Coffeelake UMaulik V Vaghela
Coffeelake U has 32MB flash chip support. Adding fmd file and enabling CFL U board's Kconfig to output 32MB rom file. Change-Id: I21431b7ac813781b12b95f80c6f8960a78caf4bc Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-08-14mb/intel/coffeelake_rvp: Add support for new board coffeelake RVPMaulik V Vaghela
Add support for new board coffeelake RVP. This patch is a copy patch and copies entire coffeelake_rvp folder from cannonlake_rvp. Changes done on top of copy: 1. Change copyright year from 2017 to 2018 2. Rename Cannonlake to Coffelake whenever applicable 3. Update entries in Kconfig and Kconfig.name 4. Rename variant directories to match coffeelake boards Change-Id: Id37bfeb0ae51fd630fec96273216dbb2900782c7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27904 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-14util/autoport: Adapt logmaker for newer ACPI versionsArthur Heymans
acpidump now creates dumps with 4 spaces instead of 2 in front of the hex dump, so be a bit smarter about the input with regexp. Tested with X220 autoport logs: Still creates the same coreboot code. Change-Id: I8d48c09cdff9432f394b350540ea9765fc942781 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-14xgcc: fix grouping of conditions in buildgcc for AdaStefan Tauner
No idea where the escaped parentheses come from but they are no good. Without this patch I see errors with bash and dash: ./buildgcc: line 1198: (: command not found ./buildgcc: line 1199: (: command not found The patch uses curly brackets for grouping since they don't launch a subshell - unlike using unescaped parentheses which would work too. shellcheck is happy with either variant (and the original one(!)). Change-Id: I44fbc659f5b54515e43e85680b1ab0a824b781a7 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/27771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-13util/lint: Set "acknowledgement" correctElyes HAOUAS
"acknowledgement" is not commonly used but correct. Change-Id: I0aa469d77904d65288f5b7133bec10be3688a596 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13driver/spi/stmicro: add 3.3V variant of N25Q032Stefan Tauner
Unfortunately stmicro.c does not distinguish the 1.8V version from the 3.3V versions (yet) although they have distinct RDIDs. I have at least ordered the ID macros accordingly and used a proper name in this patch. Change-Id: Id4fd8d46dcc9e51c1ae5504a32c2f8c5cfd863a1 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/27861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13Documentation/gfx: explain port mapping in libgfxinit's configStefan Tauner
Change-Id: Id24ded4ba641aade66468313e33ede1a82090f05 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/27854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13mb/google/kahlee: Remove unneeded blank linePaul Menzel
Change-Id: I189c981f3334836ab24bbc74491e9b58a2d403a4 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/27921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13mb/intel/cannonlake_rvp/Kconfig: Don't redefine firmware pathsArthur Heymans
The paths defined in southbridge/intel/common/firmware/Kconfig should work just fine. Change-Id: Iaa780d9b3080416c6b1a7f24d97ecb8214962405 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28012 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13soc/intel/broadwell/Kconfig: Clean up redefined config optionsArthur Heymans
All broadwell board set HAVE_IFD_BIN to default n, overloading the option in soc, therefore just use the defaults in sb/intel/common/firmware. Change-Id: I250dbbc9d61ecedc1a1eb48751ad966732604349 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28011 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13soc/intel/braswell/Kconfig: Clean up redefined config optionsArthur Heymans
There is no need to redefine option present in southbridge/intel/common/firmware/Kconfig. FAKE_IFD depends on out tree flashrom patches for which there are better alternatives available now, so don't build with FAKE_IFD by default. Change-Id: Icd41137a1bbfe519c89a71cc0c7c3755558bd834 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28010 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13sb/intel/lynxpoint: Don't build with FAKE_IFD by defaultArthur Heymans
FAKE_IFD depends on out tree flashrom patches for which there are better alternatives available now, so don't build with FAKE_IFD by default. Change-Id: I21bc5bdc8b733fbfdb1b2a4fbcb572c76701074a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28009 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/rambi: Don't set defaults for HAVE_IFD_BINArthur Heymans
There is no need set the default HAVE_IFD_BIN explicitly to n. Change-Id: I4a5fe45e7f8f6dd018937861b0fb92a8da49904e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28008 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13sb/intel/lynxpoint/Kconfig: Clean up redefined config optionsArthur Heymans
There is no need to redefine option present in southbridge/intel/common/firmware/Kconfig. Change-Id: I9999440031b07006e2df11e00dfb9f3dbe04f832 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28007 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13fsp_broadwell_de: Increase CONFIG_MAX_CPUS to 32Samuel Jimenez
Fix to accomodate for boards with more than 16 cores. Change-Id: I35b61d94491c21ef76717f761e566ca815880f27 Signed-off-by: Samuel Jimenez <aerojsam@gmail.com> Reviewed-on: https://review.coreboot.org/27847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13superio/winbond/w83627hf: Remove unused valueElyes HAOUAS
Change-Id: I90d1997254f6766f4c61ff55449109adbdd783e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13src: Get rid of non-local header treated as localElyes HAOUAS
Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13Documentation/Makefile.sphinx: Be cautious when running `rm -rf`Tristan Corrick
If BUILDDIR were an empty string, running `make clean` would result in running `rm -rf /*`. Omitting the trailing /* prevents this. With a valid BUILDDIR, the behaviour of `make clean` changes slightly in that BUILDDIR itself is removed. However, this is probably more in line with what one would expect from `make clean`. Change-Id: I51b52bb6e7fe73a07fed6291a4f1cc253f2bf319 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27775 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13src/mb: Remove some unneeded includesElyes HAOUAS
Change-Id: I3108193c0e0b644cecb74ae0c7a7b54e24a75b58 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13mb: Get rid of unneeded include <cbmem.h>Elyes HAOUAS
Change-Id: I80dd65484fd52e9048635091fb20a123e959e999 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27869 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13cpu/intel/car: Align the stack to 16 bytes before romstage_mainArthur Heymans
Change-Id: I1415c18779bc481fdec5f72f83c06a58ce6d5c39 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26797 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13google/bobba: Add Raydium touch screen supportPan Sheng-Liang
Current coreboot does not create ACPI device for OS to recognize Raydium touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=none BRANCH=master TEST=emerge-octopus coreboot Change-Id: Ic61a69e19e97520da0702dfe6cb7496563fc34f4 Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13util/lint: update checkpatch.pl to latest linux versionMartin Roth
Taken from Linux upstream commit ffe075132af8b7967089c361e506d4fa747efd14 Change-Id: I43d09a912fafe896c045df080c0f75fe6d908087 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28046 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13nb/intel/haswell: Always locate mrc.bin in the COREBOOT fmap regionArthur Heymans
This binary needs to be at a specific offset and will therefore always be located in the COREBOOT fmap region. This is needed when VBOOT_SEPARATE_VERSTAGE is selected. Change-Id: Ia73d468ab23932f92331ef40b8e8066cef55af2c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-13util/lint: Update spelling.txt to latest linux versionMartin Roth
Comment out 'sepc' and add a comment about it at the top so that it doesn't get added back in accidentally in a future update. Change-Id: Iaa909d97d0d97d7bf0799e48fc237a9673d549aa Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13mb/intel/dg43gt: Enable the GBEArthur Heymans
This was blindly copied from logs created under vendor BIOS in non-descriptor mode which apparently set LAND in BUC. Change-Id: I94c917600421ee742ece7f6f71309da80261da28 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-13arm64: mmu: Spot check security state for TTB mappingJulius Werner
Since commit 372d0ff1d1 (arch/arm64: mmu: Spot check TTB memory attributes), we already check the memory attributes that the TTB region is mapped with to avoid configuration mistakes that cause weird issues (because the MMU walks the page tables with different memory attributes than they were written with). Unfortunately, we only checked cachability, but the security state attribute is just as important for this (because it is part of the cache tag, meaning that a cache entry created by accessing the non-secure mapping won't be used when trying to read the same address through a secure mapping... and since AArch64 page table walks are cache snooping and we rely on that behavior, this can lead to the MMU not seeing the new page table entries we just wrote). This patch adds the check for security state and cleans up that code a little. Change-Id: I70cda4f76f201b03d69a9ece063a3830b15ac04b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13cpu/x86/smm/smm_module_loader.c: Avoid static analysis error "unused value"Richard Spiegel
In procedure smm_load_module, variables fxsave_size and fxsave_area are set to 0 and NULL, but if CONFIG_SSE is enabled, they are overwritten. Change the code setting the value to an "else" of the "if" testing CONFIG_SSE, thus avoiding static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I3042b037017a082378b53ee419c769c535632038 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13soc/intel/skylake: use unique _uidMatt Delco
There's two cases of 1 being used. This changes the eighth instance to use 8. Change-Id: I7057a4345dadcc6f8fb43093844d27007444f481 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13ec/google/chromeec: de-dup a _UIDMatt Delco
There's two instances od _UID 1 for PNP0C02. This change moves the more system-specific instance of the two to a higher number. I believe these are the 4 I'm seeing. soc/intel/skylake/acpi/systemagent.asl Device (PDRC) Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) soc/intel/skylake/acpi/lpc.asl Device (LDRC) Name (_HID, EISAID ("PNP0C02")) Name (_UID, 2) ec/google/chromeec/acpi/superio.asl Device (ECMM) { Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) ec/google/chromeec/acpi/superio.asl Device (ECUI) { Name (_HID, EISAID ("PNP0C02")) Name (_UID, 3) Change-Id: I2b0f1064726a1fa3940ccfb2a4627c79a26684e4 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13.checkpatch.conf: Ignore a few more warningsMartin Roth
- PRINTK_WITHOUT_KERN_LEVEL is a new warning that coreboot's printks don't follow. - UNDOCUMENTED_DT_STRING is ignored because we don't have any documentation for .dt files. - SPDX_LICENSE_TAG is another new warning. We can evaluate adding the spdx license tags to our files, but at this point they aren't there, so disable it for now. Change-Id: I4b7fcfc0339b358a48e77188d85b47c022c7eb49 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13mediatek: Map SRAM as secure and cached memoryTristan Shieh
This patch changes the mapping of SRAM from non-secure to secure. Without this patch, mmu_config_range() can not work when MMU is enabled. The new config is still in non-secure cache since TTB section is allocated in SRAM which is mapped as non-secure. BUG=b:80501386 TEST=Boots correctly on Kukui and Elm Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-13mb/google/poppy/variants/nocturne: remove icc_max overridesNick Vaccaro
Remove icc_max overrides to allow SoC code to set proper icc_max based on CPU SKU. BUG=b:78122599 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage', flash to nocturne, boot to kernel and verify device doesn't hang after a few minutes. Change-Id: I37c44e2428b802d754f2b12b8a57601d257e6582 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27996 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/poppy/variant/nocturne: update PL2 based on CPU skuNick Vaccaro
This patch adds a function to overwrite PL2 setting based on CPU sku. From doc #594883, PL2 is 18W for AML-Y. BUG=b:110890675 BRANCH=None TEST=emerge-nocturne coreboot chromeos-bootimage & test with AML-Y and KBL-Y skus. Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27997 Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/poppy/variant/atlas: Update PL2 based on CPU skuGaggery Tsai
This patch adds a function to overwrite PL2 setting based on CPU sku. From doc #594883, PL2 is 18W for AML-Y. BUG=b:110890675 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage & test with AML-Y and KBL-Y skus. Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27765 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13intel/apollolake: Fix typo in dptf.aslChris Zhou
Fix define typo in dptf.asl BUG=none TEST=emerge-octopus coreboot PASS Change-Id: I1c3bd55d1507e6fffe638bba38c99a9851b8a96a Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-13mb/google/octopus/variants/fleex: Set up DPTF tableJohn Su
Follow thermal table (b:112274477 comment#1) for first tunning. BUG=b:112274477 TEST=Match the result from DPTF UI. Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-13utils: spkmodem: suggest to use parec instead of parecordDenis 'GNUtoo' Carikli
Using recent versions of parecord produces the following: Failed to open audio file. According to the manual: -r | --record Capture audio data and write it to the specified file or to STDOUT if none is specified. If the tool is called under the name parec this is the default. so we suggest parec instead. Change-Id: I8b821df67b10e9d6533c4cbe19c646c84d436c27 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/23863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
2018-08-13utils: spkmodem: Add Makefile and gitignoreDenis 'GNUtoo' Carikli
Change-Id: Ie3a6a777f5b667e881a4462bdd44a34dbace5520 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/23862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13mediatek/mt8183: Add DRAM resource in ramstageTristan Shieh
Add DRAM resource in ramstage to load payload. BUG=b:80501386 TEST=Load bl31 and depthcharge correctly on Kukui with more patches applied. Change-Id: Ie793b403bbbdb3c231dfa2caef29dcbb596b1a61 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27971 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13security/vboot/Makefile: Use shell cat instead of make file commandRaul E Rangel
The make `file` command is apparently a v4.2 feature only. Replace it with a shell cat. BUG=none TEST=verified fwid.region was created correctly Change-Id: I5e32a521ad3e6759853f0cde2e4c4db6e564d3be Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-13soc/broadcom/cygnus: Increase romstage SRAM size in memlayoutPhilipp Deppenwiese
* Needed for additional code in later patches. * SOC is obsolete anyway. Change-Id: I5bbdf19cc886103e9e7a6b75219d6881cfe9c757 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23764 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/octopus: Enable SAR config for Intel 9560 moduleJohn Zhao
Enable the GEO SAR feature for Octopus. Program wifi_sar VPD key. coreboot reads the VPD and creates the ACPI table as per the WGDS spec. BUG=b:112288077 TEST=Program VPD key, extract acpi table ssdt and valiate WGDS entry. Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12mb/google/octopus: Do not configure IOStandby for WLAN_PE_RSTFurquan Shaikh
PERST signal is asserted/deasserted by ACPI routines during suspend/resume. Configuring IOStandby for WLAN_PE_RST can result in failure to resume from suspend state with wake-over-WLAN. This change removes the IOStandby configuration for WLAN_PE_RST. BUG=b:112371978 Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 17:08:46 +0000