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2015-12-02drivers/intel/fsp1_1: Don't hide build related options behind HAVE_FSP_BINStefan Reinauer
The right thing to do is to hide them behind PLATFORM_USES_FSP1_1. The only things that should depend on HAVE_FSP_BIN is the code that actually adds the file to CBFS, and the path to the file in Kconfig. Removing the HAVE_FSP_BIN check requires some default values for two Kconfig variables. Change-Id: I9b6c3ed0cdfb0e02421d7b98c488a66e39add947 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12465 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02util/nvramtool: Use correct virtual address when mapping tablesTimothy Pearson
The existing code used a stale pointer from a previously unmapped region of memory when parsing the coreboot tables. Use the correct pointer from the currently mapped memory region when parsing. Change-Id: Id9a1c70655fe25bc079e5bee55f15adf674694f8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12619 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: Emit some build output while adding files to CBFSPatrick Georgi
Change-Id: I167f570957ca7eaf71fc31e1bd84b9bbad0683eb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12551 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: drop one level of indirectionPatrick Georgi
coreboot.pre1 was generated then copied into coreboot.pre, now without any additional manipulation. Get rid of that extra step. Change-Id: I138567cadbc2fa1a6b6c988e34bdaae0e92d5554 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12550 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: Add more files through cbfs-files instead of manual rulesPatrick Georgi
verstage, romstage, and payload can be added through infrastructure now. Change-Id: Ib9e612ae35fb8c0230175f5b8bca1b129f366f4b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12549 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: make cbfs-files mechanism spaces-safePatrick Georgi
Space is commonly used as separator in make variables, so escape them as * (which should be reasonably uncommon in file names and cbfstool options alike to not be a problem). Change-Id: Ia77b5559841b5eae3aa1c0c0027f2e7fb882ea2f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: Allow giving additional cbfstool options to cbfs-files-yPatrick Georgi
This enables adding romstage, verstage, and payload, that may need additional options (eg. for XIP or for linux initrd arguments) to be added with the build system infrastructure instead of manual rules. Change-Id: Ifde4ec3ca4ab436aca9b51a3c2cc478ed493fbfb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12547 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02lippert/frontronner-af & toucan-af: Fix IASL warningsMartin Roth
Not all the paths through the _OSC method returned a value. According to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized GUID. Fixes warnings for both platforms: dsdt.aml 1143: Method(_OSC,4) Warning 3115 - ^ Not all control paths return a value (_OSC) dsdt.aml 1143: Method(_OSC,4) Warning 3107 - ^ Reserved method must return a value (Buffer required for _OSC) Change-Id: Ibaf27c5244b1242b4fc1de474c371f54f930dcb6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12530 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02kconfig_lint: Fix check_is_enabled for 2 symbols on the same lineMartin Roth
The previous code would miss the first of two IS_ENABLED(CONFIG_symbol) sequences on a line. This patch saves the rest of the line and loops to check any other entries on the same line of text. Change-Id: If4e66d5b393cc5703a502887e18f0ac11adff012 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02kconfig_lint: Change from '$file at line $line' to $file:$lineMartin Roth
Combine the file and line number into a combination that editors understand when opening files. This makes it easier to edit the errors. Change-Id: Id2fae6a0a2ca8d726b95e252d80ac918f4edbe23 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12561 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02kconfig_lint: Separate errors from warningsMartin Roth
- Create subroutines for printing warnings and errors - Change all the existing warning and error routines to use subroutines - Add new command line options to suppress errors and to print notes Change-Id: I04893faffca21c5bb7b51be920cca4620dc283c3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12555 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02coreinfo: use coreboot crosscompilerMartin Roth
Set up coreinfo makefile to use .xcompile and the coreboot 32-bit cross compiler toolchain. Restrict to x86_32 gcc compiler. Tested in QEMU Change-Id: I1cc180a5eeaf6cb9a36fdcef70a9819d0f459168 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12454 Tested-by: build bot (Jenkins) Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: replace files on UPDATE_IMAGEPatrick Georgi
So far the build system only added files starting with CBFS_PREFIX/ in the UPDATE_IMAGE configuration, but there are a number of files that exist in the global namespace (eg. config, revision, but also cmos_layout.bin). Now, existing files are removed if necessary. Change-Id: I977ff85fe18115c84268103be72e91ca854e62a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12581 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de>
2015-12-02toolchain.inc: Add IASL test as part of coreboot toolchainMartin Roth
Even though coreboot has IASL as part of its toolchain, it was not being picked up when testing to make sure coreboot is being compiled with the coreboot toolchain. This patch adds an iasl test when testing coreboot toolchain. Change-Id: I5b989869417c3f60057a91842b911855d9528f1b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12543 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-02toolchain.inc: Improve help messages for coreboot toolchainMartin Roth
Show better help text on how to compile the coreboot toolchain or use an unsupported toolchain. Change-Id: I64a2159d324d673784669b2464c1a2769b048678 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12557 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-02mainboard/intel/d510mo: Add Intel D510MO mainboardDamien Zammit
Board uses Pineview native raminit Board boots from grub to linux kernel VGA needs work, currently headless machine Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/10074 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02x86/smm: Initialize SMM on some CPUs one-by-oneDamien Zammit
We currently race in SMM init on Atom 230 (and potentially other CPUs). At least on the 230, this leads to a hang on RSM, likely because both hyperthreads mess around with SMBASE and other SMM state variables in parallel without coordination. The same behaviour occurs with Atom D5xx. Change it so first APs are spun up and sent to sleep, then BSP initializes SMM, then every CPU, one after another. Only do this when SERIALIZE_SMM_INITIALIZATION is set. Set the flag for Atom CPUs. Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/6311 Tested-by: build bot (Jenkins) Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-02northbridge/intel/pineview: Add native raminitDamien Zammit
Does native ram init for Intel Atom D5xx 8086:a000 northbridge Tested on Intel D510MO mainboard, board boots linux kernel - Works fully with both dimms populated (2x2GB), memtest passes 100% - Almost boots with only one dimm in one of the slots (suspect bad memory map with one dimm?) - Reads garbage with only one dimm in other slot Change-Id: Ibd22be2a959045e0a83aae2a3a0e877013f80711 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-02northbridge/intel/pineview: Add remaining boilerplate code for northbridgeDamien Zammit
This patch does *not* include native raminit Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12430 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-12-01southbridge/amd/sb700: Fix boot hang when AHCI mode disabledTimothy Pearson
Existence of requested PCI device was not checked when enabling IDE mode on the SP5100. Fix incorrect PCI device ID and check for device existence before attempting setup. Change-Id: I726c355571b5c67c9a13995be2352601c03ab1e4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12572 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01cpu/amd/fam10h-15h: Enable DFE on Family 15h HT3 linksTimothy Pearson
Decision Feedback Equalization (DFE) is a form of dynamic link training used to lower the overall error rate within the coherent fabric. Enable it on all capable HT links. Change-Id: I5e719984ddd723f9e375ff1a9d4fa1ef042cf3eb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12072 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-01cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setupTimothy Pearson
The existing code did not properly detect various link attributes on Family 10h/15h processors. With the addition of new HT3- and IOMMU-specific code, proper detection has become critical to avoid system deadlocks. Fix and streamline link attribute detection. Change-Id: If63dd97f070df4aab25a1e1a34df4b1112fff4b1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01nb/amd/amdht: Fix XCS buffer count setup on AMD Family 15h CPUsTimothy Pearson
The existing code re-used the Family 10h XCS buffer setup on Family 15h CPUs, which set incorrect values leading to random system lockups. Use the Family 15h XCS buffer setup shown in the BKDG. Change-Id: Ie4bc8b3ea6b110bc507beda025de53d828118f55 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0Timothy Pearson
Minor change to be more explicit about the binary state of the iolink detect variable. Change-Id: Ifd8f5f1ab28588d100e9e4b1fb0ec2525ad2f552 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12069 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-12-01nb/amd/amdfam10: Fix incorrect channel buffer count configurationTimothy Pearson
The secondary bus number set code incorrectly overwrote the link buffer settings in F0x[F4,D4,B4,94]. Constrain the secondary bus number set to the appropriate bits of the registers. Change-Id: If70825449f298aa66f7f8b76dbd7367455a6deb1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12068 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01mainboard/asus/kgpe-d16: Enable GART by defaultTimothy Pearson
Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12067 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-01nb/amd/mct_ddr3: Add Family 15h tristate enable codesTimothy Pearson
The Family 15h DRAM initialization did not set up the various tristate enable codes in the MCT. Add Family 15h tristate enable setup. This fixes multiple DIMMs on a single channel. Change-Id: I0278656e98461882d0a64519dfde54a6cf28ab0f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12060 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-01amd/pi/00630F01: Drop HT3_SUPPORTMartin Roth
The Kconfig symbol CONFIG_HT3_SUPPORT is not implemented. This mirrors commit c5163ed8 (AMD binaryPI: Drop HT3_SUPPORT) Change-Id: I2682d3b620e2cee613c7421622a8c79db5ba3a86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12556 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-01Makefile.inc: make sure .xcompile is removed when building toolsMartin Roth
Most of the toolchain build targets already ran clean-for-update, but there were a few that didn't. Add the clean to those targets. Change-Id: I7faad32ac8bb1815e0c58e7d142ca2dbfc877896 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12571 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-01build system: strip quotes from CONFIG_CBFS_PREFIX in a single locationPatrick Georgi
Instead of having to remember to strip the quotes everywhere so that string comparisons (of which there are a few) match up, do it right at the beginning. Fixes building the image with a .config where CONFIG_CBFS_PREFIX contains quotes. Change-Id: I4d63341cd9f0bc5e313883ef7b5ca6486190c124 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12578 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-11-30fsp_baytrail: Remove use of BAYTRAIL_SMM Kconfig symbolMartin Roth
The symbol BAYTRAIL_SMM was never valid (there's no config statment initializing the symbol), but it was being selected and used in the code. Now that SMM is supported in fsp_baytrail, the code it was trying to switch can be removed, and just set up for SMM. Change-Id: I0fd4865a951734e728500e7baf593ff7eb556f73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12553 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-11-30build system: add dependencies for SeaBIOS outputPatrick Georgi
Change-Id: I7b9f1574f6d487c0a6e5c9095c25ee973a96fa89 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12577 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-11-30nb/amd/amdmct/mct_ddr3: Use StopOnError to decrease training timeTimothy Pearson
There is no need to continue testing a DCT configuration after data errors have already been detected; this just wastes time during boot. Change-Id: I979e27c32a3e0b101590fba0de3d7a25d6fc44d2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12066 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30mainboard/intel: Add Little PlainsMarcin Wojciechowski
This adds a new mainboard: Little Plains for Intel's atom c2000 It was based on Mohon Peak board with some minor changes This board is not available as standalone product It is a managment board for Intel Ethernet Multi-host Controller FM10000 Series The FSP package is available from Intel: https://www.intel.com/fsp Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350 Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com> Reviewed-on: https://review.coreboot.org/12503 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHzTimothy Pearson
The CPU <--> CPU HT wiring on this board has only been validated to 2.6GHz. While higher frequencies appear to function initially, and in fact function when only one CPU package is installed, dual CPU package systems will lock up after around 6 - 12 hours of uptime due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks. If applications are not being used that stress the coherent fabric, then the uptime before hang may be much longer. Users attempting to overclock the HT links are advised to "burn in test" the HT links by running memtester locked to a node with no local memory installed. Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12064 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-30cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixesTimothy Pearson
Change-Id: I132874fe5b5a8b9a87422e2f07bff03bc5863ca4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12065 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins)
2015-11-30nb/amd/mct_ddr3: Use antiphase to better center DQS windowTimothy Pearson
The BKDG recommends the use of an antiphase window detection algorithm to ensure that the DQS data eye is properly centered. TEST: Booted both with DIMMs known to move the data eye into the prior clock phase and DIMMs known to keep the data eye in the current clock phase. Change-Id: I1d85fddd45197ca82dcaa46fe863e64589712d1f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12059 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30bachmann/ot200: Remove DRIVERS_I2C_IDREG Kconfig symbolMartin Roth
As far as I can tell the Kconfig symbol DRIVERS_I2C_IDREG never actually existed in the coreboot codebase. I didn't see anything that it might have been a typo of. Change-Id: Ib17de670e38e07ab4a4745143c42fa85da1754e1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12563 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2015-11-29nb/amd/mct_ddr3: Fix odd rank data corruptionTimothy Pearson
The odd rank of each DIMM could experience data corruption due to incorrect DQS training. Fix the DQS training algorithm by executing the relevant portions of the training algorithm on the odd ranks. Change-Id: Ibc51f5052d5189e45b3d9aa98ca8febbfe13f178 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12058 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29nb/amd/amdmct/mct_ddr3: Fix a minor RDIMM CS select errorTimothy Pearson
Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12057 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29nb/amd/amdmct/mct_ddr3: Ensure channel clock skew is properly setTimothy Pearson
Also fix incorrect Trfc[0-3] value on Family 15h. Change-Id: Iafc233984ae1d44fe6a1cb5b109d36397cbd991a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12055 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29x86/smm: don't hide harmless declarationsPatrick Georgi
Hiding them requires #if CONFIG_HAVE_SMI_HANDLER instead of if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) Change-Id: Ib874cd98e195ad7437d05be1696004b29bf97a66 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/12565 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29build system: move defconfig creation into a cbfs-files filterPatrick Georgi
That allows this special case to become a normal cbfs-files instance, too. Change-Id: I896ffebe4cec64c9c11605b4f09c7790e5419928 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12539 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29build system: break overly long lines into logical unitsPatrick Georgi
Change-Id: I37b716acb305a79614cea184f57b8488111eab7a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12540 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29build system: Move manual cbfstool add* invocations to cbfs-filesPatrick Georgi
Use cbfs-files-y to deal with some of the manually added cbfs files, providing more structure to that part of the build. Change-Id: Iee1b8fec81dfa5e5f0e55637a62e5f69bd0257ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12538 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29build system: don't try to add cbfs-files with no backing filePatrick Georgi
Change-Id: Idd05a552762be92d0d93b357b96442b25a614757 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12537 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29build system: establish priority levels for CBFS file additionsPatrick Georgi
Add files with fixed positions, then files with alignment requirements and finally those that can reside everywhere to prevent the most obvious collisions. This isn't perfect yet (the "aligned" group may need some additional sorting), but should avoid the worst instances ("free floating" files allocating space required by fixed location files, for example). Change-Id: I871e1a92ad90e63fc4e299fe1b228b4b00a35930 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12536 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-28nb/amd/amdfam10: Work around sporadic lockups when CC6 enabledTimothy Pearson
The silicon in control of CC6 appears to contain minor bugs and / or deviations from the BKDG; through trial and error it was found that these issues can be worked around by reserving the entire possible CC6 save region, regardless of currently installed node count. Change-Id: If31140651f25f9c524a824b2da552ce3690eae18 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12054 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-28libpayload: Remove redundant 8250 MMIO32 UART driverAlexandru Gagniuc
The more generic 8250 driver can handle both port-mapped and memory- mapped 8250-compatible UARTs, with different register sizes. Thus, a separate driver for MMIO32 is not needed. The generic 8250 driver was tested to work for both output and input, on Apollolake SoC, which only presents an MMIO32 UART. Change-Id: Idab766588ddd097649a37de92394b0078ecc660a Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/12524 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-28baytrail: fix missing brackets around ir_base to fix IRQ routingAlexander Couzens
The missing brackets caused other registers, including the IO APIC enable bit (EAN in OIC) to be overwritten. Bug introduced by bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer) Change-Id: I1d5aa2af6d74405a1a125af6221ac0e635a6b693 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/12525 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>