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2015-04-13elog: Fix regression that caused elog to omit "System boot" eventJulius Werner
CL:243671 moved the initialization of elog_initialized around, which is now unfortunately so late that the ELOG_TYPE_BOOT event gets omitted because the code believes the log to be broken at that time. Good thing we now have a FAFT test for these things that I had of course been too lazy to run. -.- The real reason for moving that line was to put it after any point in elog_init() that could still error out. The problem is that we might add the "cleared" event before we try to shrink (which can fail and cause an error)... but those two things cannot happen at the same time, so it should be okay to flip them around and mark the elog as initialized in between. BRANCH=none BUG=chrome-os-partner:35940 TEST=Ran firmware_EventLog on a Pinky, manually confirmed that I once again get "System boot" events. Change-Id: I12dcf4a8e47d302f6cd317194912c31db502bbaf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4a1c0b861017ca25229b1042c4b37dda33e869f9 Original-Change-Id: I4103779790e1a8a53ecabffd4316724035928ce6 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246715 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9503 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13elog: Correct behavior when FMAP section doesn't exist on ChromeOSJulius Werner
The elog driver has a really stupid bug that checks a result which is stored in an unsigned variable for < 0. Surprisingly GCC does not catch this nonsense right now, and I spent an hour trying out different warning options without finding one that doesn't also bring a load of stupid and unavoidable false positives (the biggest offender being -Wtype-limits, which does exactly what we'd want except for flagging things like if ((u8)var >= CONFIG_VAR_MIN) where the VAR_MIN Kconfig may or may not be 0). So, the only thing we can do is fix this one and wait for the next time something like that blows up. -.- Also change some more code to make the behavior more explicit (the old code already intended to work this way since flash_base is statically initialized to 0, never assigned in the error path and checked later in elog_init()... but there was an error message that incorrectly claimed a different fallback behavior, and explicitly assigning the values makes this easier to see). Finally, add another state to the elog_initialized variable to avoid trying to reinitialize a broken eventlog on every event (if it doesn't work the first time, chances are that it won't work later on during the same boot either). BRANCH=None BUG=chrome-os-partner:35940 TEST=Flashed Jerry with RO 6588.4 and RW 6588.23, observed how it now cleanly enters recovery mode without blowing its bootblock away with stray eventlog entries. Change-Id: I0e5348ba961ce4835c30f7108a2453522095f2ee Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f9798dbf0c2b2e337062ecd84d0f45434343c0d9 Original-Change-Id: I4d93f48d2d01d75a04550d419e023aa42ca95a7a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243671 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9557 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13urara: add support for DMA coherent memory areaIonela Voinescu
The information about the DMA memory area is further passed through the coreboot table to the payload. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA; DMA memory area was used to test the functionality of the DWC2 USB controller driver; behavior was as expected. BRANCH=none Change-Id: I658e32352bd5fab493ffe15ad9340e19d02fd133 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 0debc105b072a37e2a8ae4098a9634d841191d0a Original-Change-Id: Icf69835dc6a385a59d30092be4ac69bc80245336 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/235910 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9593 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13t132: add RAM repair to cluster 1Yen Lin
RAM repair has to be performed to cluster 1 also. BRANCH=none BUG=none TEST=Test on Rush and make sure RAM repair completes Change-Id: I0daf969a995a2be152270bc06501eaf086a13a97 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6b07894cc737cb192f68e254d522b55d8ca3b2f3 Original-Change-Id: I458e0a66d76318c6a4aa82547c9037c7b969f1e1 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/239360 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9592 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13vboot1: Fix compilation error with CONFIG_ARCH_ROMSTAGE_ARM64 enabledYidi Lin
make: *** No rule to make target `build/lib/memset.rmodules.o', needed by `build/vendorcode/google/chromeos/vboot1/vbootstub.elf'. Stop. Fix the error by refering to ./src/arch/arm64/Makefile.inc: rmodules_arm64-y += ../../lib/memset.c rmodules_arm64-y += ../../lib/memcpy.c BRANCH=none BUG=none TEST=build pass on our own MT8173 board Change-Id: Ic870136db1ec9405e3d30caf6085f056bc46a5c2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d317dbe8732abbf7e785466e7d1e07425aac326f Original-Change-Id: I69a7db83154a23f7878e9c604c9b541fb6fa308d Original-Reviewed-on: https://chromium-review.googlesource.com/237974 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: http://review.coreboot.org/9591 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13broadwell: Enable double self refresh by defaultDuncan Laurie
Rather than enable this in every mainboard just enable it by default for all broadwell devices and let a specific mainboard disable it if needed. BUG=chrome-os-partner:34420 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I6e47c20abf29abfbd1f4b7905914b4c9fadb0ae7 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 25d3a685893e1c85f7b78e302da3187947a1f84f Original-Change-Id: I26d9f2e2a12d3f2f888ecb5af0d949eec5928f57 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238400 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9590 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13pistachio: increase the size of romstage to 36KIonela Voinescu
This is necessary for the subsequent changes that will add to the size of romstage. BUG=chrome-os-partner:31438 TEST=coreboot builds successfully;tested on Pistachio FPGA BRANCH=none Change-Id: I132215bd44708913d878bbd8b6147bef535b52df Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 00f73f9d80a36fc43735f093365564b9d74ed7f7 Original-Change-Id: Ie858416a1c9ab63cfe85eea40a76a093cbd2c79c Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233871 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9589 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13vboot2: use offset to vboot2 work buffer instead of absolute addressDaisuke Nojiri
this change makes vb2_working_data struct point to the vboot work buffer by the offset instead of by the absolute address, which can be different depending on the context (e.g. subprocessor v.s. main cpu). BUG=none BRANCH=tot TEST=booted veyron pinky Change-Id: I2191ca756c4f49441b3a357338f9c84564b58918 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 93f8b1da2b2c81aa3a33892987a71e9e1e7a8eff Original-Change-Id: I4e4c12613304586b7395c5173cf08b8093f59521 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236583 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13arch: armv7: Fix cache sync instructions.Deepa Dinamani
When the i-cache is on and the d-cache is off, the L1 i-cache is still fetching information through L2 cache. Since L2 cache is never invalidated, it has stale information. BRANCH=storm BUG=none TEST=Resolves the invalidate data fetch from i-cache while jumping from bootblock to romstage. Change-Id: Ibaca1219be2e40ce5bbbd1c124863d0ea71d0466 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a13e20f9b242d8193dcb314a2bdc708c6bdfea51 Original-Change-Id: I252682d372bd505f525f075461b327e4bcf70a1a Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236422 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9587 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-11hp/pavilion_m6_1035dx/cmos.layout: Remove unused optionsAlexandru Gagniuc
Some of the options in cmos.layout date back to the K8 days, and have not been used anywhere else, but K8. This makes nvramtool expose a very confusing set of options, most of which have no effect. Clean up the layout before it gets forked again. TEST: Booted linux, and checked 'nvramtool -a' output. Change-Id: I1c5f83790ec89ced4dcf954e4949f8554aef6087 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8378 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-10fmap: allocate memory as much as discovered fmap sizeDaisuke Nojiri
fmap_find used to read 4096 bytes from the fmap offset blindly. instead, we read the fmap header first to calcurate the size of the fmap. Then, we read flash again exactly as much as the discovered fmap. BUG=none BRANCH=ToT TEST=Booted Storm and Peppy. Built all current boards. Change-Id: Iaa50c1bc3401c77b433af11406d4b9d2e4e722e8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 755ff66ab0a4d05e6d5410c11a6badb9fcb77a0d Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ie5058d181e6565acb70bf108464682dd0e6c1f64 Original-Reviewed-on: https://chromium-review.googlesource.com/231685 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9556 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10rk3288: reset edp after edp clock source selecthuang lin
edp must reset when device power up, otherwise the edp register maybe uncertain, now the edp source clock default select 27M, and in pinky and jerry board we use 24M as edp sourec clock, if we want to reset edp, we must after the clock source select 24M. BUG=chrome-os-partner:34023 TEST=Booted Veyron jerry and read edid normal BRANCH=None Change-Id: I4b03dbabe5d3d595d2d56efb0cd82f510f8d2e1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2292da77cc2322b85c4b4f4f20e4ebcc4c4d060d Original-Change-Id: Ica031d2d52deb539c1a0a56968786d6952b3d0e8 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231336 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: http://review.coreboot.org/9555 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10Add google/veyron_mighty boardKatie Roberts-Hoffman
Essentially a copy of veyron_jerry for now. BUG=chrome-os-partner:33269 TEST=build Change-Id: Ie2d115d57fe4b6359fa6bb16a2e85e88ec99e991 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9ec25b9cf2985786e55f0b85c3849ccbd42bddd4 Original-Change-Id: Icc45c8f8bf9f6916ba7187dde277d15cc60df8a2 Original-Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230961 Original-Commit-Id: 407b8b74a068220d8051dd0d85d9c4ec3ea14d51 Original-Change-Id: I546dbc41ccd191159e96b851424fcb37902a57ec Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231691 Reviewed-on: http://review.coreboot.org/9554 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10rockchip: support displayhuang lin
Implement VOP and eDP drivers, vop and edp clock configuration, framebuffer allocation and display configuration logic. The eDP driver reads panel EDID to determine panel dimensions and the pixel clock used by the VOP. The pixel clock is generating using the NPLL. BUG=chrome-os-partner:31897 TEST=Booted Veyron Pinky and display normal BRANCH=None Change-Id: I01b5c347a3433a108806aec61aa3a875cab8c129 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e4f863b0b57f2f5293ea8015db86cf7f8acc5853 Original-Change-Id: I61214f55e96bc1dcda9b0f700e5db11e49e5e533 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219050 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9553 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: select VIRTUAL_DEV_SWITCHDavid Hendricks
Like most newer Chromebooks, Pinky and Jerry do not have physical dev switches. BUG=chrome-os-partner:33395 BRANCH=none TEST=built and booted on Pinky, crossystem prints a valid value for devsw_cur instead of an error. Change-Id: If97ffa6f99eb31c05915f3ee82aaf6bd252d29e4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db302d7286d3e7df9442928dac1d611a2c103163 Original-Change-Id: I186518a59699d293c7938221b3ae45b27361c255 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229680 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9552 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Adapt to new board revisionsJulius Werner
This patch adds support for Pinky rev3 (board ID 2) and Jerry rev2: the power button GPIO changed polarity to low, the 5V_DRV pin for USB power was moved to the AP again (welcome back!), and the EMMC_RST_L is now finally on a port with the right IO voltage so we don't need any weird pull-up tricks anymore. Since there are very few Jerry rev1s around, we'll just move it over to the new code directly without introducing board ID differences (also, because I have no idea how they stuffed it this time... is this one actually called rev2?). BRANCH=None BUG=None TEST=Still boots on my Pinky rev2, though that doesn't say much. Change-Id: Id11044cedcaac5a4ae07e696893823925107a6db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 55344a9518ff04edcef01bcd40817e9e4b613717 Original-Change-Id: Iddee360fbda357ecde4ae5fbb5c3a01fe0c22474 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229010 Original-Reviewed-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9551 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron_jerry: Port CPU overshoot preventionJulius Werner
This patch ports commit 567f616f (rk3288: slowly raise to max cpu voltage to prevent overshoot) to Veyron_Jerry. It also fixes include ordering and some comment grammar in the affected code. BRANCH=None BUG=chrome-os-partner:32716 TEST=None Change-Id: I4ac14a38e4b3acc4926d4f51f409ff12d9c841cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 679014bc843788e8d4d5f5c7470ae76f8be5e942 Original-Change-Id: I9c0aba40ddd8a0852391df184034baa740d063df Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228938 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9550 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: sdram_get_ram_code() -> ram_code()David Hendricks
This enables RAM_CODE_SUPPORT for veyron* platforms and uses the generic gpio_get_binaries() function to read RAM_ID GPIOs. BUG=chrome-os-partner:31728 BRANCH=none TEST=built and booted on pinky Change-Id: I7a03e42a270bec7036004375d36734bfdfe6e528 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a325b204ff88131dfb0bdd3dfedb3c007cd98010 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ibc4c61687f1c59311cbf6b48371f9a9125dbe115 Original-Reviewed-on: https://chromium-review.googlesource.com/227249 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9549 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: use gpio_base2_value() in board_id()David Hendricks
This makes board_id() use the generic gpio_base2_value() function to obtain the value of the board ID straps. BUG=none BRANCH=none TEST=tested on pinky Change-Id: I15c1310889b989c34638fd342011aef5fe7bcec1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fcbb8a6998a66531326afe16b232395d49fee64d Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I5847bf1c5b26bcaf7d36103f31bb255b31ff8185 Original-Reviewed-on: https://chromium-review.googlesource.com/228370 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Change VCC10_LCD_PWREN_H to allowed maximum of 2.5VJulius Werner
LDO7 (VCC10_LCD_PWREN_H) is essentially just a glorified GPIO that turns the real VCC10 regulator on or off. We tried setting it to 3.3V since it matches the VCC33_SYS voltage on the input of that regulator. However, we didn't notice that the LDO only supports going up to 2.5V. This patch changes the voltage to the allowed maximum, which should still work fine as an enable line (and is the same value used by the kernel). This removes an assertion error in the ramstage. Also change the PMIC driver to assert maximum VSEL values based on the LDO, because the lower-voltage ones support one more setting. (LDO3 is actually listed to only go up to 0b1111 in the manual, and has a weird jump from 0b1101 -> 2.2V (skipping over 0b1110) to 0b1111 -> 2.5V. I don't know if that's a documentation error or what they were smoking when they designed that, but we don't need to care for now.) BRANCH=None BUG=None TEST=Booted on Pinky, no more ASSERTION FAILED. Change-Id: I38bf99e38822fd0883fd4d0bd9a1b01143545a95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 70f3149efbc3aa9a03ab3fd5be99d17d9c5e1c87 Original-Change-Id: I68a3bb882cf25d98aca8922ede2a17e1ef6524de Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228292 Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: Jerry Parson <jwp@chromium.org> Reviewed-on: http://review.coreboot.org/9547 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron_jerry: Remove board ID based assumptionsJulius Werner
The veyron_jerry board code was just copied over from veyron_pinky 1-to-1. The Jerry board IDs start at 1, but there has never been a Jerry rev0 so we can remove the code for board ID 0 from it. BRANCH=none BUG=None TEST=Booted Jerry image on a Pinky rev2, worked fine. Change-Id: I0f2ffdc577934c1695e8d2dcf71512696ac1d5a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aa36da69ac584b845e15282dae100eec27fc7f12 Original-Change-Id: I45a18b288c8d8b1399ceedf582addcce1c7e857d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228254 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9546 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Change eMMC enable pin to be pulled (not driven) highDoug Anderson
The eMMC enable pin is in a 3.3V IO domain. Unfortunately the eMMC expects this pin to be 1.8V. The way we were driving this pin would cause the eMMC to pull power through this pin and that was causing current leaks. In future revisions of hardware we should move this pin somewhere more legit. However, in the current hardware we can get things working pretty well by using a pullup to "drive" this pin. This will work in conjunction with the external 100K pullup to give a somewhat reasonable voltage. The eMMC will also not be able to pull much current through this pin, so it can't leak too badly. BRANCH=none BUG=chrome-os-partner:33319 TEST=Boot a kernel that doesn't touch the mux/pulls and see no leak: dut-control --port=${SERVO} vcc_flash_ma -t 5 Change-Id: Ibc25cd090d826c8215be24a0b5c11d97b5281700 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 26e7a9d7e067ed4dd859387ee63bf654ab9dc529 Original-Change-Id: Iadfc1477cd478773cc9d159e3fbc22b66b8f0f78 Original-Signed-off-by: Doug Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226039 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9545 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10Add google/veyron_jerry boardKatie Roberts-Hoffman
This is essentially a copy of veyron_pinky for now. BUG=chrome-os-partner:33269 TEST=build and boot Change-Id: I151c82f54ece4620953d0db5aedf027a3293926f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 267611f2354be4384de3f05d2459a4e421ee6b4f Original-Change-Id: I0d473361e0850ee3b11da5a809f8396826ccdad6 Original-Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225301 Reviewed-on: http://review.coreboot.org/9544 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10storm: copy WiFi calibration data in the CBMEMVadim Bendebury
Invoke the function which copies WiFi calibration data in a CBMEM table. BRANCH=storm BUG=chrome-os-partner:32611 TEST=verified that the WIFI entry is added to CBMEM when the calibration data is present in the VPD. Change-Id: Icab0a2343e88e1d44575eeb608fdf6588aff255b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 68b96f158633cb3a1f157b5a19da39fa7e78f975 Original-Change-Id: I5fa77da98e37b88da01fb7884e713535fc178006 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225272 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9543 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: psci: add cpu_on/off supportJoseph Lo
The CPU on/off functions are the method for the Kernel to support CPU hot-plug function in PSCI. To support this, we still need flow controller support to capture the WFI from the CPU and inform PMC to power gate the CPU core. On the other path, we turn on the CPU by toggling the PMC and use flow controller to let go when the power is steady. BUG=chrome-os-partner:32136 BRANCH=None TEST=built the kernel with PSCI enabled, check both of the CPUs are coming up, test the CPU hot-plug is working on Ryu Change-Id: If2c529b6719c5747d5aea95fb5049b2d7353ff17 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f078e89daad1c4d8b342a395f36b3e922af66f5 Original-Change-Id: Ie49940adb2966dcc9967d2fcc9b1e0dcd6d98743 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231267 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9542 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: No need of invalidating cache line for secondary CPU stackFurquan Shaikh
With support for initializing registers based on values saved by primary CPU, we no longer need to invalidate secondary CPU stack cache lines. Before jumping to C environment, we enable caching and update the required registers. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots both CPU0 and CPU1 on ryu. Change-Id: Ifee36302b5de25b909b4570a30ada8ecd742ab82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a0403d06b89dae30b7520747501b0521d16a6db Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I738250f948e912725264cba3e389602af7510e3e Original-Reviewed-on: https://chromium-review.googlesource.com/231563 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9541 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add support for save/restore registers for CPU startup.Furquan Shaikh
startup.c provides function to enable CPU in any stage to save register data that can be used by secondary CPU (for normal boot) or any CPU (for resume boot). stage_entry.S defines space for saving arm64_startup_data. This can be filled by: 1) Primary CPU before bringing up secondary CPUs so that the secondary can use register values to initialize MMU-related and other required registers to appropriate values. 2) CPU suspend path to ensure that on resume the values which were saved are restored appropriately. stage_entry.S provides a common path for both normal and resume boot to initialize saved registers. For resume path, it is important to set the secondary entry point for startup since x26 needs to be 1 for enabling MMU and cache. This also ensures that we do not fall into false memory cache errors which caused CPU to fail during normal / resume boot. Thus, we can get rid of the stack cache invalidate for secondary CPUs. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots both CPU0 and CPU1 on ryu without mmu_enable and stack cache invalidate for CPU1. Change-Id: Ia4ca0e7d35c0738dbbaa926cce4268143c6f9de3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f5e78469313ddd144ad7cf5abc3e07cb712183a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I527a95779cf3fed37392b6605b096f54f8286d64 Original-Reviewed-on: https://chromium-review.googlesource.com/231561 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9540 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add macro to invalidate stage 1 TLB entries at current ELFurquan Shaikh
BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles successfully for ryu. Change-Id: Ia4941a864dd3394689121a8c9ddfaaf6f5c150a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1e43a081f7394b2014d89e723f816f1eca83ef49 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I60d77456573a2a1e854d9f3ca730237acfb77728 Original-Reviewed-on: https://chromium-review.googlesource.com/231698 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9539 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add conditional read/write from/to EL3 assembly macros.Furquan Shaikh
Some registers are available only at EL3. Add conditional read/write functions that perform operations only if currently we are in EL3. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: Ic95838d10e18f58867b6b77aee937bdacae50597 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 62a0e324a00248dba92cb3e2ac2f4072d0e4e2a7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: Ia170d94adb9ecc141ff86e4a3041ddbf9045bc89 Original-Reviewed-on: https://chromium-review.googlesource.com/231549 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9538 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add function for reading TCR register at current ELFurquan Shaikh
TCR at EL1 is 64-bit whereas at EL2 and EL3 it is 32-bit. Thus, use 64-bit variables to read / write TCR at current EL. raw_read_tcr_elx will handle it automatically by accepting / returning 32-bit / 64-bit values. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: I96312e62a67f482f4233c524ea4e22cbbb60941a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae71f87143f899383d8311a4ef908908116340d7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I459914808b69318157113504a3ee7cf6c5f4d8d1 Original-Reviewed-on: https://chromium-review.googlesource.com/231548 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9537 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Make non-vboot2 memlayout more usefulFurquan Shaikh
Update non-vboot2 memlayout: 1) Add timestamp region 2) Increase ramstage size 3) Change name from memlayout_vboot.ld to memlayout.ld so that any non-vboot upstream board can also use this layout. BUG=None BRANCH=None TEST=Compiles and boots to kernel prompt on ryu with vboot selected instead of vboot2. Change-Id: Idced98f9df7cdbab5f62cd1e382c6046ade1d867 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20fffa282b20fb32ce2ff687f4479be630f90fcf Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I91accd54efc53ab563a2063b9c6e9390f5dd527f Original-Reviewed-on: https://chromium-review.googlesource.com/231547 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9536 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Change memlayout to have PRERAM and POSTRAM CBFS CacheFurquan Shaikh
Instead of having unified CBFS_CACHE and limiting the POSTRAM Cache size, split them into PRERAM and POSTRAM CBFS_CACHE. BUG=None BRANCH=None TEST=Compiles successfully for both rush and ryu. Boots to kernel prompt on ryu. Change-Id: I2a70df22fe5bae23e05cdf1b8a300369c7ccf87d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b93bc06de76cab0a1ec9a56e12c9a6942a430893 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: Iab21ff5c7ca880b6bd18846e5d8d71c26dff56cf Original-Reviewed-on: https://chromium-review.googlesource.com/231546 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9535 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Bump up ramstage to 256KFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Change-Id: Ia4875948e0be5e084f54f1acb1c5acf5cdabad94 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038e9abe2c6e1813cad50bb768e1f66cdd056ccd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: If5df6e0dbf85c837f9ada6a967fd3d01b5230307 Original-Reviewed-on: https://chromium-review.googlesource.com/232002 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9533 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Add speaker amp config for AD4567 on P0/P1Tom Warren
A couple of regs need to be poked to allow audio output from this part on Ryu P0/P1. It will be replaced by two non-configurable amps on P3. BUG=none BRANCH=none TEST=Build/flashed on Ryu P1, dumped AD4567 (I2C6 dev 0x34) regs and confirmed settings. Change-Id: Ie602b056fb1488546ab233f8f81cfacb96624ebb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 75dabe378b561e939381e2ef5113a2b28bfcedf8 Original-Change-Id: I8999843646927dbd07a179ede973ba5f1eb97167 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9532 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: prepare cpu startup in psciAaron Durbin
In order to start CPUs while in secmon/psci one needs to set up the proper SoC state. Therefore, refactor the current CPU startup API to allow for this by adding cpu_prepare_startup() and start_cpu_silent(). BUG=chrome-os-partner:32136 BRANCH=None TEST=Built and booted kernel. Change-Id: I1424500f6c9398f7d44350949c25bb3d4832cec7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 70f9cf67085b345b529b41dd6554e37d38a5b350 Original-Change-Id: I842a391d3e27ddbfcdef1a2d60e3c66e60f99c77 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231936 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9531 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: psci: actually inform SoC layer of CPU_ON entryAaron Durbin
psci_soc_init() was added to allow SoC PSCI initialization. However, actually calling said function was omitted accidentally. BUG=chrome-os-partner:32136 BRANCH=None TEST=Built and noted correct on entry point was used. Change-Id: I84a397e2dabf149fe8f252ef69d0a7362fa1f194 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2a0e6ad41f049bbab483423231db59390894e9b2 Original-Change-Id: I1a4e25fde64ecdc98fa9231f7d9cafc21119630d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231935 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9530 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Remove long delay when turning on AVDD_DSI_CSIJimmy Zhang
Based on TPS65913, the max LDO turn on time is 500us. Since it is requested the default delay of 500us when calling function pmic_write_reg(), it is safe to remove this 100ms delay. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I2cfda38728db223c26f9122b70d37e828921459a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 271b7e95f66f4b8611a0d408e59f428c315074f3 Original-Change-Id: I53aecc273484edfa502231b44f6bcd7f5d8f9331 Original-Reviewed-on: https://chromium-review.googlesource.com/231170 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: http://review.coreboot.org/9529 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Increase size of bootblock due to overflowTom Warren
The bootblock on Rush had bumped up into the verstage allocation, causing the build to break. Reduced verstage from 60K to 58K and increased bootblock from 20K to 22K. Rush and Ryu both build fine now. BUG=none BRANCH=none TEST=Built both Rush and Ryu OK. Verifed verstage size using cbfstool and it's around 55K, so plenty of room. Change-Id: Iaa3a5838c5235ec78c740a977bc032d8b5e270ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 928a4d2d1efabe1e1d6a7fadc22ee0ac4269190e Original-Change-Id: I7018f027d72d5e8aeb894857a5ac6a0bdc1de388 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/230824 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: ensure secondary CPU's stack tops are not in the cacheAaron Durbin
Secondary CPUs were intermittently not coming online as expected. Upon investigation it was found that a cache line needed to be invalidated that corresponded to the top of the stack for the failing CPU. Currently the secondary CPUs come online with caching disabled. However, the code paths are using C and thus the stack it is assigned. The MMU is enabled in C after it's pushed its return path onto the stack that went directly to ram. When the cache line corresponding to its stack is valid in the cache it will hit once the MMU is enabled. That hit will have invalid data w.r.t. the return addresses pushed directly into ram. This is not the best solution as the only way to guarantee we don't hit such a situation is to tightly manage resource usage up until the point of MMU enablement. That can be done in a followup patch. BUG=chrome-os-partner:33962 BRANCH=None TEST=On ryu where secondary CPUs weren't coming online consistently, they now come up. Change-Id: I03237656da180d1f74df3a8e00029ba8d778bca8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 06ab6afc996cf92c45d4cd6850e31167c2946a95 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Change-Id: I32de749ea48c19e23442e6dc5678c5369ac3b2b6 Original-Reviewed-on: https://chromium-review.googlesource.com/231219 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9527 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: add timeout waiting for CPUs to come onlineAaron Durbin
The initial MP code assumed all CPUs would come online. That's not very defensive, and it is a bad assumption. Provide a timeout mechanism for bring CPUs online. BUG=chrome-os-partner:33962 BRANCH=None TEST=Multiple times with CPUs working and not working. Boot to kernel. Change-Id: Ib0aef31f5c732816d65c2e4b3c6a89e159974fdc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9cf5bc2844c8f4ad987cfcb69ef33c73551f0083 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Change-Id: Ifb3b72e3f122b79e9def554c037c9b3d6049a151 Original-Reviewed-on: https://chromium-review.googlesource.com/231070 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9526 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: always bring up PLLDAaron Durbin
The kernel does not correctly function without PLLD being enabled. Additionally, PLLD can be the source for other clocks in the system. Therefore, initialize PLLD to 300MHz unconditionally at BS_DEV_INIT time in ramstage. BUG=chrome-os-partner:33825 BRANCH=None TEST=Built and booted ryu with display coming up both in dev mode as well as normal mode. Change-Id: Ib2a60bb9aafc03dc23aa932a480184d87f677c65 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c49f964b55c3c33d03b95363277b262b679e740 Original-Change-Id: Ic5905e25051a042cea5010b8c6d61b1fb89a0a81 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230774 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://review.coreboot.org/9525 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: rename clock_display() to clock_configure_plld()Aaron Durbin
Provide an explicit name for configuring PLLD. The new name, clock_configure_plld(), provides an explicit semantic to what it is doing. Also, provide the printk() about actual frequency vs requested frequency as most of the callers were doing this themselves. BUG=chrome-os-partner:33825 BRANCH=None TEST=Built and booted on ryu. Change-Id: I1880f0f305e69674922b070d282aac3acdc86aad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c51d5b0864d8bd0db5927380803cec46ccd74d48 Original-Change-Id: If744332b466d9486f83b08d0ab4e9006fadfecdd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230773 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://review.coreboot.org/9524 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: audio: Setup clocks for AHUB, I2S1, codec, etc.Tom Warren
The Ryu RT5677 audio codec uses EXTPERIPH1 clock (12MHz) for MCLK1, I2S1 for input. AHUB needs all of its child peripherals taken out of reset and enabled, too. This just sets up the audio clocks. More work still to be done in the codec driver, and some kind of stub needs to be created/hacked to set up the AD4567 speaker amp regs for mono output on P1. BUG=chrome-os-partner:32582 BRANCH=none TEST=Dumped clock regs and saw correct values Change-Id: Ifb6551f1e09b38f440f3bb7c759b5e6c0b9e4e44 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 48f989a0291044f5fb4340cc89546325d819d82f Original-Change-Id: I6c9e760ac39def92a6054d673f781facdbfd70a2 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229993 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9523 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Set dc to resize the difference between framebuffer and panelJimmy Zhang
Scale framebuffer resolution to panel resolution. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: Idb19f5871605e878ea380cc8f701a377350681fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2f08a704fe3a7be1e0448e4ed864c69b50d6838 Original-Change-Id: I5ac01539da3712cd6afdb8d08513da399ace0f92 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229494 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9522 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: devicetree: Add framebuffer resolution settingsJimmy Zhang
When displaying a 800x600 bitmap on 2560x1800 panel, the image is shown very small. So, set the fb to 1280x800 (based on tegra dsi driver default mode setting), a 800x600 image can be shown relatively proportional to panel size. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I1e360aeaec97b9df5d86e46951ab1326610260d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67c2a381322721a24b1b7f9ac366073b7e3c490c Original-Change-Id: I62cbe9de1d1002293df20f8b1d752905c6ef33aa Original-Reviewed-on: https://chromium-review.googlesource.com/229912 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9521 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add framebuffer parametersJimmy Zhang
Framebuffer line size and number of lines can have different values than panel's resolution. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I228f1dd7fafc6577a8e8a987ff31ba73f7a655ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a4929dc5831076f2f2a5dd2e13f24b3477e197b Original-Change-Id: Iedeef796f02286bb03920413420f8952cf34334a Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229915 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9520 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Pass panel spec to lib_sysinfoJimmy Zhang
panel spec such as resoultion, bits per pixel are needed to pass to depthcharge/payload for displaying bitmap onto panel. Enable display code only if mainboard selects MAINBOARD_DO_NATIVE_VGA_INIT. Otherwise build breaks for boards that do not support display init yet. BRANCH=none BUG=chrome-os-partner:31936 TEST=Compiles for both rush and ryu. Display comes up for ryu in both normal and dev mode. Change-Id: I81b4d289699e7b0c2758ea1a009cbabaf8a2ce28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b9b42486f203d332f6068ccd6f4a1a982d327a6b Original-Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Id: ce2883b21d3fbfd54eac3a355fb34ec70e9f31ad Original-Change-Id: Ib4a3c32f1ebf5c6ed71c96a24893dcdee7488b16 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/9519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Expand ramstage size to 208k (from 192k)Jimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: Ief81194381193ef9acc7c1786915945d66f2efdb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 826ce3730f6d26c9f7a8c3f0429ab14a213172e8 Original-Change-Id: Icc62c776db6f8d8b27615c467518e9753627e72c Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229914 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9518 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add dsi driverJimmy Zhang
Add dsi and related dc, panel configuration functions. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I8440b6dfccc7ed7cd280a0df3a98cbc7b7d66070 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb08563f67daf9a616b60609c4523b823d34f8e3 Original-Change-Id: I87b8047e23ebe114af353fcce5924a46621d16d2 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227202 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9517 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: devicetree: Add dsi panel mode settingsJimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I2bd1b2c2b1bfe75702a12129ca57b3afa6542575 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6aac5ecb014ab213f465b9aa78f587994c6b3624 Original-Change-Id: I64f2df49a258b4dd024305a9757704a823265e99 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229911 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9516 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 06:32:24 +0000