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2015-06-30cbfstool: Handle elf with different virtual and physical addressFurquan Shaikh
Adds support in cbfstool to adjust the entry field based on the virtual and physical address in program header. BUG=chrome-os-partner:40713 BRANCH=None TEST=Verified correct entry point address. Trusty loads and boots correctly. Change-Id: I215b0bea689626deec65e15fb3280e369d816406 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 32a740f0b628c124d3251cc416e2fc133bb15c57 Original-Change-Id: Ia999b5c55887c86ef1e43794ceaef2d867957f4d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/274087 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10690 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30libpayload: add UDC driver for Designware controllerhuang lin
Found in rockchips rk3288 as used in google/veyron. BUG=None TEST=None BRANCH=None Change-Id: I2f2c36c5bea3986a8a37f84c75608b838a8782ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 59a0bcd97e8d0f5ce5ac1301910e11b01e2d24b1 Original-Change-Id: Ic89ed54c48d6f9ce125a93caf96471abc6e8cd9d Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272108 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/10689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30EC: Add new EC host event for FASTBOOT_MODE requestFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Change-Id: Id24b87e03097eb93c0b4316c853575629e5502aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf80de709d2bf310a3a37b9897063d2d833933b9 Original-Change-Id: Ia5d42efd81b59c1b99d3be5be6d0c770ad602429 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280879 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30UDC: Correct cleaning out memory for string descriptorsFurquan Shaikh
BUG=chrome-os-partner:41687 BRANCH=None TEST=Compiles successfully and fastboot devices reports correct serial number even after re-connection. Change-Id: I4741a5d6333523eb47c27b4a20c4ef3f1e853d76 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6249b1e35391550d788f56a7b3e7a49ae19f0c93 Original-Change-Id: I1348c33f354d11e3c29ccd9da9948cfbeb60aa9e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281192 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10687 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30udc/chipidea: Allow force_shutdown of connectionFurquan Shaikh
Allow force shutdown operation of the connection in case where the cable is disconnected and reconnected back. BUG=chrome-os-partner:41687 BRANCH=None TEST=Compiles successfully and fastboot works fine even with reconnection of cable Change-Id: I8eb1217b4a9ad6ce8a2a40db329eca1930eda089 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3d7ab65c459caa4ec526b99a1aee1a31e9cb80da Original-Change-Id: I354c44e0ed2211cb2c4c1ae653d201b7d15ea932 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281066 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10686 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30veyron_danger: Update SDMMC power on/off code for v2David Hendricks
This re-factors SDMMC power on/off to make corrections and take differences between board versions into account. To avoid similar- but-different case switch statements in romstage.c and mainboard.c, power on/off functions for SDMMC are split into their own .c file. BUG=none BRANCH=none TEST=built and booted of micro-SD card on Danger v2 Change-Id: Ib3069c35ceff1ff98b49579a6298681c1390beee Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eecfee4a5dd39073b5f966a25991a594b3c4b519 Original-Change-Id: Id86ae7f40687e843ffc4e7769309d4678ad54f49 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280853 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10685 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30veyron_danger: Add basic HDMI supportDavid Hendricks
This adds a configure_hdmi() function that drives the HDMI enable output high and configures the iomux. We'll add EDP/HDMI auto-detection in an upcoming patch. BUG=none BRANCH=none TEST=set vop_mode to 1 in Danger's devicetree.cb and saw dev mode screen output to HDMI display. Change-Id: I2a208059fee74d436b5a5bedbc677bc59525f935 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 721f326319f727afcf73a0c21d20d26cb463ad71 Original-Change-Id: I139d39749963d4121aaeec0c3da37d825ffa94ac Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280849 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10684 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-29vboot2: Enable VBOOT_DYNAMIC_WORK_BUFFER on x86Stefan Reinauer
Change-Id: Iaadbd52d948000d1ed46865b83bdb0f4926ca429 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-29vboot2: consolidate vboot2 buffer initializationPatrick Georgi
Instead of calling the init function to clear out vboot2 data structures in multiple places, move the function and call close to verstage_main(). Change-Id: If42e18a8e4581f22f7a7aced70ccbe3188bb0cd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10701 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-29mainboard/msi/ms7135: DSDT: fix PCI and AGR interruptsJonathan A. Kollasch
Tested with interrupting AGP card in AGR slot. PCI slots tested with 3-function OHCI/EHCI USB 2.0 card, covering the INTA-INTC lines in each. Change-Id: I0f8aeba90890a76a7cf9cbee9be7bcf919d1e39a Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10644 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-29mainboard/msi/ms7135: only #include necessary headers in acpi_tables.cJonathan A. Kollasch
Change-Id: I0837a2d1e0d8e233f6ef7d7212ce76f2223d19b9 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10641 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-28intel raminit: check correct registers in channel_testPatrick Rudolph
Found while doing code review. No actual problem was observed. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Verify byte-lane error count registers 0 to 7 instead of verifying byte-lane error count register 0 eight times in a row. Change-Id: Ife6ac6558b2f65ad947870cde5f15d90560ce6d9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10664 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-28intel raminit: properly handle DDR3 DIMMs with address mirroringPatrick Rudolph
Issue observed: DDR3 DIMM with address mirroring enabled doesn't work when placed in slot 1 and slot 0 is empty. It does work when placed in slot 0 and slot 1 is empty. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H * Kingston KVR1066D3N7/4G (address mirroring enabled DIMM) Problem description: The address mirror enable bit is slot-swapped in the DIMM mapping code, but none of the remaining code is aware of DIMM mapping. Removing the code, that is swapping the mirror enable bit, results in the correct behaviour. The DIMM is now working in every slot. Change-Id: I7a51bbc8d156209449fd67c954930835814a40ee Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10652 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-27mainboard/asus/kfsn4-dre: Enable VGA supportTimothy Pearson
The ASUS KFSN4-DRE has full native VGA support, enable support for the VGA device by default in the Kconfig file. Change-Id: I09fc8845a30f26ca49f3547812f9784621ff4b5e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10673 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-06-27lenovo/g505s: Add System Board ID to fix ACPI warningMartin Roth
Add the System Board Hardware ID to fix the warning: dsdt.aml 88: Device (MB) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) Change-Id: Ie97b1e6792c8d4c8db2500cef6a79881b7ff94c8 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10669 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-27google/parrot: Add System Board ID to fix ACPI warningMartin Roth
Add the System Board Hardware ID to fix the warning: dsdt.aml 88: Device (MB) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) Change-Id: I063580142ae8053fdc05e165c01e86b8b7cd5ca6 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10668 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-27Kconfig: Remove unnecessary and incorrect MRC_CACHE symbolsMartin Roth
Because of a misunderstanding of how Kconfig files are parsed, the OVERRIDE_MRC_CACHE_LOC symbol was added to make sure that the value was correctly set. This is not needed unless for some reason the Kconfig parser is suddenly rewritten to parse everything differently. At some point, the value in the FSP's Kconfig file was updated to OVERRIDE_CACHE_CACHE_LOC, while the entries in the mainboard Kconfig files were not updated. This resulted in the default values not getting set correctly by default on the FSP Bay Trail boards. This removes the whole bunch of incorrect and unnecessary symbols and just sets the default for the MRC cache location directly. Change-Id: I1cec758576866b7e0677272b8309bfde8d4a1ee4 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10611 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-27amd/inagua: broadcom driver 64bit fixStefan Reinauer
Change-Id: I357f11fa74bac5f9e1ecfc91a91f06127334752d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10596 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-26rockchip/rk3288: complete vboot configuration and move to SoCPatrick Georgi
Where vboot verification can start, and how the code flow looks like is more a property of the SoC (and its properties, like amount of SRAM) rather than the board. Change-Id: I610153ea4ceddc226d8cc3e17a515e41fc0479cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10662 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26google/chromeos: always enable VBOOT_VERIFY_FIRMWARE with CHROMEOSPatrick Georgi
Change-Id: Icc3cf64f259d4ebd7900ad91163276774e5422ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10661 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26vboot: Init vb2 work memory area before calling verstagePatrick Georgi
Otherwise it'll determine some offsets from uninitialized data and hilarity ensues. Change-Id: I6a671987857cfd3f3cd6078aebd13dd09fc79020 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10660 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26google/veyron_speedy: Add chromeos.c to romstagePatrick Georgi
vboot requires it. Change-Id: Iae2310c9b9c311c3f64b8417295685261ba404b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10659 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26x86: Move architecture selection from linker script to Makefile.incStefan Reinauer
Change-Id: I5efd3cb3e6970b5740f740507244a1ab823e0bb6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10590 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-26prog_loader: Play nice with gc-sectionsStefan Reinauer
With an x86_64-elf toolchain, this code that is unused outside of ramstage, is causing undefined references. Help the compiler along a little bit by conditionally compiling the code in ramstage only. Change-Id: I75518149b53c24eda4b985b0fef856447e196dec Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10585 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-26soc/intel/common: Restrict common romstage/ramstage code to FSPLee Leahy
Restrict the use of the common romstage/ramstage code to FSP 1.1 BRANCH=none BUG=None TEST=Build and run on cyan/sklrvp Change-Id: Ifbdb6b4c201560a97617e83d69bf9974f9411994 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10653 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25Braswell: Remove copyright addressLee Leahy
Remove the copyright address from all of the files. BRANCH=none BUG=None TEST=None Change-Id: I7190e34e165e5652d33902440fa08253b77f4af2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10337 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25Braswell: Add Braswell SOC supportLee Leahy
Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25soc/intel/common/Kconfig: Fix warning & whitespaceMartin Roth
Because of a missing close quote, we have the warning: src/soc/intel/common/Kconfig:52:warning:multi-line strings not supported This was added in commit 0946ec37 -Intel Common SOC:Add romstage support The whitespace issue - using spaces instead of a leading tab was added in the same commit. Change-Id: I429c66afb5a7e10ca0e0ef619ac46722c63fb376 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10654 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-06-25amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0zbao
Besides the first five DWORDs, the offsets 0x40 & 0x41 are used to save SPI settings. They should only be 0xFF for being written. Other parts in ROMSIG are also changed to 0xFF for potential requirement. Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/10651 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-25Intel FSP 1.1: Move Kconfig comment inside 'if' blockMartin Roth
- Move the 'Intel FSP' Kconfig comment inside the 'if' block so that it doesn't show up on platforms that aren't using it. - Update the comment to reflect that this is version 1.1 of the FSP interface. Change-Id: I7182c5b07332c4f95620f7374526ab1de0484d01 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10650 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-06-24Intel/common: Remove copyright addressLee Leahy
Remove the copyright address from the remaining files. BRANCH=none BUG=None TEST=None Change-Id: I026a0ff2bcb6c9580b45700edab446b787223007 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-24Intel Common SOC: Add romstage supportLee Leahy
Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-24FSP 1.1: Bring source up-to-dateLee Leahy
Use 3rdparty/blobs subdirectory for binary files Display the MTRRs after TempRamExit and before the MTRR setup Clear all of the variable MTRRs before the MTRR setup Define the FSP attributes location and bits Properly display the FSP_RESERVED_MEMORY_RESOURCE_HOB and the FSP_BOOTLOADER_TOLUM_HOB. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I788a5f1e7676b1a06c1bcd66ddbd0a2249cad47c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24cpu/x86: Add more MTRR symbolsLee Leahy
BRANCH=none BUG=None TEST=Build and run on strago Change-Id: Ia3740353eb16f2a2192cad8c45645f845bf39475 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10588 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24Intel vendorcode: Add FSP_SMBIOS_MEMORY_INFO_GUIDLee Leahy
Add new GUID for FSP. BRANCH=none BUG=None TEST=Build and run on strago Change-Id: I539a59b513f67535436f581e0a79ab53f05682ca Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10587 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24pcengines/apu1: Remove unused ide.aslTobias Diedrich
The APU1 board has no IDE port, remove ide.asl. Change-Id: I76b926969748de79ac1281ed50b37e9ade1a6771 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10622 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-24Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: Icf83d5e2a3daea385af3572e9eac6b2431652c28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10640 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-24crossgcc/Makefile: Allow making toolchains using multiple coresMartin Roth
I looked for a way to pass the 'make crossgcc -j8' on to buildgcc, but didn't find a way to get that value directly. MAKEFLAGS turns -j8 into a jobserver variable. Instead, this patch allows the number of CPUs to be set on the command line through a variable instead. Example: 'make crossgcc BUILDJOBS=8' Change-Id: I37608cdb4549226cb7ff8c3ff6d9f4773acf6b0b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10620 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24crossgcc/Makefile: clean more, add distclean targetMartin Roth
Update the clean target to remove the intermediate files. These should get removed automatically, but if the build stops in the middle, or if the -t command is used for buildgcc, they can be left in the directory. Add a distclean target that removes the downloaded tarballs as well as everything else. Change-Id: I6ea19e7a499b0c313c1d2eff7e36386204ec834e Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10621 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-24Kconfig: Get rid of obsolete symbolsMartin Roth
CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION ALT_CBFS_LOAD_PAYLOAD was removed in commit: cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD MARK_GRAPHICS_MEM_WRCOMB was removed in commit: 30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB. EXTERNAL_MRC_BLOB was removed in commit: 0aede118 - Drop unused EXTERNAL_MRC_BLOB CACHE_ROM is only in Google's codebase. LID_SWITCH is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used. HUDSON_NOT_LEGACY_FREE never existed as far as I can tell. MAINBOARD_DO_EDID never existed as far as I can tell. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10616 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-24autoport: Include 'default_irq_route.asl' into DSDTStefan Reinauer
After commit with Change-Id Ia1839ed3 (sandy/ivy: Include IRQ routes from platform), update autoport to include that file into the DSDT. Change-Id: I14534438d0b433895f384539c8b413eaa53d943a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10612 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-24sandy/ivy: Include IRQ routes from platformKyösti Mälkki
The default route does work for all Chromebooks and is replaced with platform-specific one in follow-up. Change-Id: Ia1839ed38dacf44a89dc757394d054e17666f193 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10442 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-23msi/ms7135: move power_on_after_fail out of RTC century byteJonathan A. Kollasch
Change-Id: I0796b6e7adad0151c5aa6271d62a2cf4abeedb1e Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10643 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23nvidia/tegra: expose more registersTom Warren
This is in preparation for t210 Change-Id: I3e640b1f7fc583518361527dec4c3c1072c80251 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e762d4bde1a18691257453e4b87a0bb42a0a2d7c Original-Change-Id: Ida096106bb0137c07ad62d2df06628e37f0d884c Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272754 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10632 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-06-23tegra: Move pinmux enum constants from tegra/pinmux.h to soc-specific pinmux.hFurquan Shaikh
Since pinmux register format has changed completely for t210, move the constants to pinmux.h in soc-specific folders. BUG=chrome-os-partner:37546 BRANCH=None TEST=Compiles successfully for ryu and foster. Change-Id: Ic1680ac50fc2619657d0c610a5dfc3fb51df7286 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7844c941a6187f884b31a8f7cc52e64268d2c732 Original-Change-Id: Icd3b2a72f3698e0772e888d9209e1fcd5d10e77d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/260900 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10631 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-06-23southbridge/intel: Create common IFD Kconfig and MakefileMartin Roth
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC. This is the start of creating a common interface for all of them. This also allows us to reduce the chipset dependencies for CBFS_SIZE. Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10613 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-23vendorcode: Use cross archiver for libagesa.a on AMD f14Stefan Reinauer
Change-Id: I61a9f65a1ac4c95096d0ff071a95984cf219caa8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10593 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-06-23arm-trusted-firmware: update markerStefan Reinauer
Change-Id: I8dddeead3c23a03803e7d8d5b2bfb8a15c5c2807 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10645 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-23lippert/frontrunner-af: 64bit fixesStefan Reinauer
Change-Id: Ia764798c8b58497e2b453bd000dd06816c28f98f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10600 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23lippert/toucan-af: 64bit fixesStefan Reinauer
Change-Id: I9e7f78587b9d6e87cf77757654da9145d4187625 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10599 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 01:40:52 +0000