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2014-04-15mainboard/jetway/nf81-t56n-lf: Documentation cosmeticsEdward O'Callaghan
Keep under 80 colums and Doxygen'ify inline documentation somewhat. Strip some whitespace bulk while here and refactor a little as to line wrap. Additionally, following the reasoning of: 0b2fa34 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables remove some fluff from buildOpts.c Change-Id: Icb38f087724d3e3511df1d554a620eb637ce286a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5481 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-04-15superio/ite/it8728f: Fix headers and prototype locationEdward O'Callaghan
Try to conform to some kind of standard/consensus for prototype location. Correct headers while here. Change-Id: Ie99b1801fa42ddefb9f25d54f326ba7131bd7089 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5499 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-15southbridge/amd/agesa/hudson: Clean up AGESA #includesAlexandru Gagniuc
Just like in commit * 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes Include AGESA headers specifying the path relative to AGESA_ROOT. The path is specified relative to AGESA_ROOT as opposed to src/ since this code may include headers from different AGESA families, depending on the board. Change-Id: Ide38cc34e207a8b617d1d319fd9c17a785f55833 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5423 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-15vendorcode/amd/agesa/fam15tn: Build as a static libraryAlexandru Gagniuc
Up until now, we were building AGESA by specifying each AGESA source file and adding it to the list of romstage and ramstage source files. As a result, we were compiling each AGESA source twice, despite the fact that it does not depend on the stage we're in. Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. We still keep the practice of specifying every single AGESA directory as an include dir and adding the AGESA CFLAGS to our global CFLAGS; this is needed due to the way AGESA builds. Change-Id: I9b23264129d1c08cb67cabc31d15a68d43ed7624 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5430 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-14hp/pavilion_m6_1035dx: Fix GPIO map and add WLAN pinAlexandru Gagniuc
Change-Id: I07725b71508c8b08451022307ae934c1b227f7f9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5491 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-14jetway/nf81-t56n-lf: Use hexdump() for dumping ACPI tablesEdward O'Callaghan
Use hexdump() instead of a local implementation for dumping ACPI_TABLES. Change-Id: I20354a4f9dff4105de5af696bb9da4a4f6cca788 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5466 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-04-13hudson boards: Don't require ide.asl file on boards without IDEAlexandru Gagniuc
Not all boards which use the AMD Hudson southbridge have IDE. However, the southbridge's asl included an 'ide.asl' file which had to be present in $(mainboard_dir)/acpi. Address this issue by removing the inclusion of 'ide.asl' from the southbridge 'fch.asl' and remove 'ide.asl' from Hudson boards, none of which have IDE. If future hudosn board will come with IDE, the device can be declared in the PCIO scope of dsdt.asl, right below the inclusion of 'fch.asl'. Change-Id: Ie2efb7ebf8f5b527e26d7aaaeafbd3053a9a6b28 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5459 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13cimx/sb800/cfg.c: Cut out purposeless ROM reading noise.Edward O'Callaghan
Follow along hudson, cut out "SLP_TYP type was 0" excessively filling the buffer. We could make this conditional on non-zero? Change-Id: Iffd4c146b2ac4f57dbc3a011a683c92b6e132e39 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5495 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-13hp/pavilion_m6_1035dx: Add basic EC initializationAlexandru Gagniuc
The EC is now set to ACPI mode, and properly generates SCIs on external events. This fixes the issue where battery notifications were not working. The keyboard matrix type is also explicitly set up. Change-Id: Ib6f0d23984d4ed1320340282469b8325c83547d1 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5471 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-13cimx/sb800 boards: Don't require ide.asl on boards without IDEEdward O'Callaghan
Not all boards which use the AMD cimx/sb800 southbridge have IDE. However, the southbridge's asl included an 'ide.asl' file which had to be present in $(mainboard_dir)/acpi. Address this issue by including ide.asl only in boards which have IDE, and remove it from all other cimx/sb800 boards. Change-Id: I57fcb4db9f85234b05ae1705ef81a576c478cee6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5460 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13mainboard/*/acpi/ide.asl: Serialize ACPI methods to avoid races.Edward O'Callaghan
Serialize methods against the construction of same (named) objects by competing threads. See ACPICA BZ 909 for further details. This change fixes issues that show up with the Ubuntu firmware test suite (fwts) ACPI table sanity checker. Change-Id: I49e3050a2a5aece6f031122b0211c056938d1a89 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5458 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13cpu/amd/agesa/s3_resume.c: Specify include paths from AGESA_ROOTAlexandru Gagniuc
Following the same reasoning as in commit * 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes include AGESA files with a path relative to AGESA_ROOT. We cannot with more than one generation of AGESA, hence the path being relative to AGESA_ROOT. Change-Id: If15c4cbfd42e0264264fdb3e8c426a47609ad41f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5426 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13jetway/nf81-t56n-lf: Replace AGESA types with stdint typesEdward O'Callaghan
Try to use void and uint*_t type specifiers in place of VOID and UINT* respectively. Use const in place of CONST type modifier. Remove some useless type casts. A few unneeded comments containing the AGESA redefenied types are also removed. Change-Id: I4bff96a222507fc35333488331c3f35ef1158132 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5486 Tested-by: build bot (Jenkins)
2014-04-13jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESAEdward O'Callaghan
Replace usage of AGESA poor reinvention of memset/memcpy functions with the usual standard ones. Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5484 Tested-by: build bot (Jenkins)
2014-04-12hp/pavilion_m6_1035dx: Add ACPI support for lid switchAlexandru Gagniuc
This is sufficient to at least allow linux to recognize the lid switch and read its state correctly. Change-Id: Id5bd92466c72559f263c7ca8d23cbc741377a762 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5464 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-12hp/pavilion_m6_1035dx: Declare GPIO control block in ACPIAlexandru Gagniuc
Only the WLAN control pin and the lid switch input are declared, as those are the only pins whose function is known and tested. Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5463 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-12hp/pavilion_m6_1035dx: Add ACPI support for reading battery levelAlexandru Gagniuc
Hook in the EC ASL code. This provides just enough information for the OS to be able to read the battery information. EC notifications (_Qxx) do not yet work, and it is unclear if the issue is in the ACPI code, or if the EC is not set up properly. Thus, the OS must boot with the battery inserted in order to be able to read its status. The _L03 ACPI method is also removed, as the EC SCI uses this event. Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5445 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-12ec/compal/ene932/acpi: Let mainboard define the ACPI lid objectAlexandru Gagniuc
The GP15 ACPI object was used to get the state of the lid. However GP15 is specific to certain Intel chipsets, and will not always be in the ACPI namespace. Instead of hardcoding this object, let the mainboard define it. Also, document the ACPI interface for the EC. Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5444 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-12agesa: Always include family* KconfigPatrick Georgi
Otherwise we generate a recursive dependency because CPU_AMD_AGESA depends on the per-family configurations while those only exist if CPU_AMD_AGESA is selected. Change-Id: Ic08d517ff4ca8bb76afc1574b55c54b28ec3f1b0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5490 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-11Add the Rangeley FSP include & srx directoriesMartin Roth
These are the .h and .c files from Intel that support interaction with the FSP. These have been modified from the FSP distribution only to strip trailing whitespace. Intel® Firmware Support Package for Intel® Atom™ Processor C2000 Product Family (Formerly Rangeley) "Intel® Firmware Support Package (Intel® FSP) provides key programming information for initializing Intel® silicon and can be easily integrated into a boot loader of the developer’s choice. It is easy to adopt, scalable to design, reduces time-to-market, and is economical to build." http://www.intel.com/fsp Change-Id: I9ed94cb92909c3681cc88bf10b85a9ba25e8fc55 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/5457 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-04-11Add the Bay Trail FSP include & srx directoriesMartin Roth
These are the .h and .c files from Intel that support interaction with the FSP. These have been modified from the FSP distribution only to strip trailing whitespace. Intel® Atom™ processor E3800 product family (formerly Bay Trail) "Intel® Firmware Support Package (Intel® FSP) provides key programming information for initializing Intel® silicon and can be easily integrated into a boot loader of the developer’s choice. It is easy to adopt, scalable to design, reduces time-to-market, and is economical to build." http://www.intel.com/fsp Change-Id: I0fa64dbaf640493cdb5e670e8d213a49d9e7dcfb Signed-off-by: Martin Roth <martin.roth@se-eng.com> Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/5456 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-11Add the ivybridge i89xx FSP include & srx directoriesMartin Roth
These are the .h and .c files from Intel that support interaction with the FSP. These have been modified from the FSP distribution only to strip trailing whitespace. Intel® Firmware Support Package for Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for Communications Infrastructure with Intel® Communications Chipset 89xx Series Platform Controller Hub (formerly Crystal Forest Refresh: Ivy Bridge Gladden and Cave Creek "Intel® Firmware Support Package (Intel® FSP) provides key programming information for initializing Intel® silicon and can be easily integrated into a boot loader of the developer’s choice. It is easy to adopt, scalable to design, reduces time-to-market, and is economical to build." http://www.intel.com/fsp Change-Id: Ib76e89b2d2f6407cf55a5a664da989c7a7e0eb23 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/5455 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-11Update vendorcode/intel/makefile for coming FSPsMartin Roth
Other FSPs have more than just the initial fsphob.c source file. Add any .c files in the srx directory to the ramstage build. Change-Id: I5118bdcca44935b579809c4fc9566ab7914a6e4b Signed-off-by: Martin Roth <martin.roth@se-eng.com> Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/5454 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-11intel/*bd82x6x/acpi/pch.asl: Correct name of field unit to GP03Paul Menzel
GP0e does not fit into the naming scheme of the field units surrounding this field unit definition. Also the keys for e and 3 are close to each other supporting the theory that this is indeed a typo. Change-Id: I43cf288fe1e0240b33971073c1aa8a1db5762e31 Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5483 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-09vendorcode/amd/agesa: Do not hardcode ROM base addressAlexandru Gagniuc
The ROM address range is set up in the LPC PCI device, register 0x6c. Coreboot already sets that up correctly in the bootblock, however AGESA overrides that to 0xffffff00, which will always map the ROM from 0xff000000. This may conflict with other devices which are assigned address space in that range. If a device is assigned a range between 0xff000000 and the real ROM base, accesses to that device will be diverted to the system ROM, regardless of how other BARs are set up. Since we already need to set up the ROM address range in the bootblock, before calling AGESA, just remove the override from AGESA. Note that not all AGESA versions override this mapping. Change-Id: I592e5d087ed830c9604a04a356912c7654ce56d2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5467 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09supermicro/h8qgi/dsdt: Use PIC as default interrupt modelKonstantin Aladyshev
According ACPI specification: """ The \_PIC optional method is used to report to the BIOS the current interrupt model used by the OS. The argument passed into the method signifies the interrupt model OSPM has chosen, PIC mode, APIC mode, or SAPIC mode. Notice that calling this method is optional for OSPM. If the method is never called, the BIOS must assume PIC mode. Arguments: (1) Arg0 – An Integer containing a code for the current interrupt model: 0 –PIC mode 1 –APIC mode 2 –SAPIC mode """ In current configuration with default value of interrupt model PMOD equal 1 (APIC mode), Linux can't boot with "noapic" option. Kernel never call _PIC method and PMOD stays equal 1, indicatind that APIC routing objects should be evaluated. This mix of PIC and APIC leads to boot fail. Change default value of interrupt model PMOD to 0, for correct "noapic" boot. Change-Id: I7fa6f0c24802751202ed2e7f13411001a600e772 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/5473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09mainboard/lenovo: [2/2] implement initial T530 supportEdward O'Callaghan
Step 2: change the Lenovo X230 code to adapt it to the new board's hardware with the great guidance from Vladimir (phcoder) to find the correct GPIO's. The machine has: - Chipset: Intel QM77 - GPU's: Intel Integrated HD Graphics : Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology Change-Id: Iee12c3edc22df4a7935b7fb7ff4a320c21c4239b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5391 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09mainboard/lenovo: [1/2] fork X230 to T530Edward O'Callaghan
Step 1: copy all files unmodified from Lenovo X230. This makes it much easier later to see how the two boards actually and deliberately differ when porting bugfixes from one to the other. Change-Id: I3151c7848440ea6c240b959379a8eb369d35f3de Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5390 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-04-09asus/f2a85-m: conditionally show POST codesIdwer Vollering
Change-Id: I61e55601676c0825815d6520a874ccade8942379 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/5362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09lynxpoint: Fix SerialIO ACPI compile issue with recent IASLDuncan Laurie
The SerialIO DwordIo() definition is fixed up before returning it in the serialio device _CRS method, so the values that are set in the raw ASL are not actually used. However modern versions of IASL do not like that the RangeLength is set to zero and will fail to compile. Set this value to 1 to make IASL stop complaining, but the real value is still fixed up in _CRS so this has no real effect on the end result. Change-Id: Iceb888e54dd4d627c12d078915108a11f45b1a2d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5182 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-09sb/amd/amd8111/acpi.c: Remove set but unused variable `dword`Paul Menzel
Removing `-Wno-unused-but-set-variable` from `CFLAGS` results in the error below, when building for example the HP DL145 GL1. CC southbridge/amd/amd8111/acpi.ramstage.o src/southbridge/amd/amd8111/acpi.c: In function 'acpi_init': src/southbridge/amd/amd8111/acpi.c:100:11: error: variable 'dword' set but not used [-Werror=unused-but-set-variable] Removing the variable `dword` fixes this error. The read is left in the code, as I do not know if it has an effect or not. Change-Id: I9957cef3a996c5974c275423c9de63ccf230974e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5315 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Refactor uart8250/NE2KKyösti Mälkki
Do this for symmetry with romstage_console.c. Change-Id: If17acfc3da07b1dbefa87162c3c7168deb7b354a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5330 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Remove old fix for DEBUG_SMIKyösti Mälkki
No longer needed as wrap_putchar() survives SMM relocation to TSEG. Change-Id: I6143844b0b9902ef63baf3e5781a5dc4f54234be Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5335 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Simplify vtxprintfKyösti Mälkki
We do not need ROMCC support here and using wrappers for console_tx_byte we can simplify this code. Change-Id: I7f3b5acdfd0bde1d832b16418339dd5e232627e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5334 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Move newline translation outside console_tx_byteKyösti Mälkki
This gives us completely transparent low-level function to transmit data. Change-Id: I706791ff43d80a36a7252a4da0e6f3af92520db7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5336 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Add printk helper for ChromeOSKyösti Mälkki
Do not expose console_tx_flush() to ChromeOS as that function is part of lower-level implementation. Change-Id: I1e31662da88a60e83f8e5d307a4b53441c130aab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5347 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Hide global console_loglevelKyösti Mälkki
Change-Id: I7bdc468bc3f74516abb2c583bdb5b6d7555d987c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5333 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Unify do_printk()Kyösti Mälkki
Change-Id: I6c50e47d9d2d0d1f42beee477e49b2a0054d1786 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5332 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Split console_init()Kyösti Mälkki
Splitting the version prompt satisfies some requirements ROMCC sets for the order in which we include source files. Also GDB stub will need console hardware before entering main(). Change-Id: Ibb445a2f8cfb440d9dd69cade5f0ea41fb606f50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5331 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09OxPCIe uart: Move under drivers/uartKyösti Mälkki
This driver is only a thin shell for uart8250mem and we could extend it with further compatible PCI IDs from other vendors/brands. Change-Id: Ic115b1baa0be0dbaa81e4a17a2e466019d3f4a67 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09OxPCIe uart: Split PCI bridge controlKyösti Mälkki
None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5237 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09uart: Redefine Kconfig optionsKyösti Mälkki
Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5311 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09console uart: Fill coreboot table entriesKyösti Mälkki
Also fixes the reported baudrate to take get_option() into account. Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5310 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09uart: Prepare to support multiple base addressesKyösti Mälkki
Prepare low-level register access to take UART base address as a parameter. This is done to support a list of base addresses defined in the platform. Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5309 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09cpu/amd/car: Use define MSR_MCFG_BASE rather than hardcoded valuePatrick Georgi
Change-Id: I0b40c9811115b204f1cae70546d236049c1b3d30 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5431 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09jetway/nf81-t56n-lf: Simplify agesawrapper_amdinitcpuio()Edward O'Callaghan
Follow same reasoning as: 12fd779 hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio() Use coreboot variants for PCI and MSR access over AGESA's. Change-Id: Ic0d8bbd0faf6423605567564ad216b79e1331cc9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5472 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09ec/compal/ene932/ec.h: Include stdint.h for definition of 'u8'Alexandru Gagniuc
Change-Id: I7ffa8e8f807e7d8a778eb80c12a0dc984bdb3f8b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5470 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-04-09hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tablesAlexandru Gagniuc
Change-Id: I181da410490a92760ae1328a4286e805f5388886 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5462 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09supermicro/h8qgi/dsdt: Move _PIC method to root scopeKonstantin Aladyshev
_PIC method should be declared under root scope (\_PIC), otherwise Linux kernel doesn't use it. Change-Id: I29b6ca60191507ac8edf99fdf173617bd6446934 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/5478 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio()Alexandru Gagniuc
TRIVIAL. Rather than using the AGESA functions for PCI and MSR access, use the coreboot variants, which are cleaner and more readable. Change-Id: I4f24820606900e16f0d159df019f4560f1592489 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5468 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 00:32:02 +0000