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2015-01-13cbfstool: Remove arch check for different stagesFurquan Shaikh
Remove the arch check for each stage as the arch for different stages can be different based on the SoC. e.g.: Rush has arm32-based romstage whereas arm64-based ramstage BUG=None BRANCH=None TEST=Compiles successfully for nyan, link and rush Original-Change-Id: I561dab5a5d87c6b93b8d667857d5e181ff72e35d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205761 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 6a6a87b65fcab5a7e8163258c7e8d704fa8d97c3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic412d60d8a72dac4f9807cae5d8c89499a157f96 Reviewed-on: http://review.coreboot.org/8179 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-13vendorcode/intel: remove DebugDeadLoop() from fsptypes.hMartin Roth
When included for the CAR transition, this was causing the error: error: invalid storage class for function 'DebugDeadLoop' Change-Id: Idf37a8104b4468b40c29c8cbe9a40f7a357a4f17 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8193 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-13soc/intel/fsp_baytrail/gpio.c: Silence unused variable warningEdward O'Callaghan
Put functions in appropriate pre-processor sections to avoid false-positive 'unused function' compiler warnings. Change-Id: Ia83d721827ad9924807c0ca5ebd681060af49a82 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8203 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-01-13mainboard/lenovo/x220/gpio.c: Remove unused structEdward O'Callaghan
Change-Id: I25bdee38cedbe38cd447483d3e8b3bdc3f646a62 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8201 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-12src/device: Doxygen fixesMartin Roth
- Add missing parameters - add missing @param commands Change-Id: I029b5dafde94bd250800b06c0e9bd2118f10ef48 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8173 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-12southbridge/intel/lynxpoint/me_9.x.c: Avoid unused func warnEdward O'Callaghan
Put functions in appropriate pre-processor sections to avoid false-positive 'unused function' compiler warnings. Change-Id: Ie4955ee9df6904c38848f46226b53be37d9fa239 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8157 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-01-12soc/intel/broadwell/me.c: Prevent unused function warningEdward O'Callaghan
Put function under same guard as its call site so that the compiler does not emit a warn about unused functions upon a false branch of the guard. Change-Id: I899d539ec5fbb87e7469415cc8d15837ba8e63f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8156 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-01-12soc/intel/broadwell/spi_loading.c: Remove dead codeEdward O'Callaghan
I would appear from commit a6354a1 that this is now dead code. Change-Id: I0f74183c9a5d8cc6ff5a11409d487cc45d9ed2df Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8168 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-12mainboard/lenovo/?/Kconfig: select NO_UART_ON_SUPERIOEdward O'Callaghan
These boards don't have Super I/O's, rather they use Embedded Controllers instead. No need to confuse with Super I/O related stuff showing up in menuconfig. Change-Id: I4922319daf7920bf5331b5bce05ded0d9a31a69b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7986 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-01-12libpayload: Let GDB stub read/write memory with aligned MMIO wordsJulius Werner
Looks like we got our first SoC that actually insists on using word-sized accesses for its MMIO registers with the Rk3288. This patch changes the GDB command handler for reading and writing memory to always perform word-sized accesses. This isn't really perfect since the remote GDB interface is just not really meant to interact with MMIO (e.g. you shouldn't use this on something with read side effects), but for most of our purposes it should be good enough. BUG=chrome-os-partner:18390 TEST=Remote GDB works on Veyron even when writing MMIO registers. Original-Change-Id: I2ae52636593499f70701582811f1b692c1ea8fcc Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208554 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 028940934e6b45a02122b61bb859588bf8671938) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4185a6efe9a5211525781acd0a167b821e854211 Reviewed-on: http://review.coreboot.org/8130 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-12libpayload: Expand setbits_le32() and fix readl() const-nessJulius Werner
setbits_le32() is not really arch-specific... the arch-specific part of accessing memory is wrapped by readl() and writel(), and the endianness can be accounted for with the right macros. Generalize the definitions, add a be32 version and move them to endian.h so that all platforms can use them. Also include endian.h from libpayload.h so we won't update any payload's old use of the macros (endianness is something useful enough to always have avalable anyway, and shouldn't clash with other things). This also fixes a bug where these macros would only be available if libpayload-config.h had been independently included before. Also fix a bug with readl() macros on all archs where they refused to work on const pointers (which they should). CQ-DEPEND=CL:208712 BUG=None TEST=Stuff still compiles. Built and booted on Storm. Original-Change-Id: I01a7fbadbb5d740675657d95c1e969027562ba8c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208713 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 951f8a6d77bc21bd793bf4f228a0965ade586f00) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I51c25f01b200b91abbe32c879905349bb05dc9c8 Reviewed-on: http://review.coreboot.org/8129 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-12libpayload: improve us timer accuracyVadim Bendebury
In cases where timer clock frequency is not an integer number of megahertz, the calculations in timer_us() lack accuracy. This patch modifies calculations to reduce the error. The maximum interval this calculation would support decreases, but it still is in excess of 1844674 seconds for a timer clocked by 10 MHz, which is more than enough. BUG=none TEST=manual . verified timer accuracy using a depthcharge CLI command Original-Change-Id: Iffb323db10e74b0ce3b4d59a56983bfee12e6805 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207358 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e1abf87d438de1a04714482d5b610671e8cc0663) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia892726187ab040dd235f493c92856c15951cc06 Reviewed-on: http://review.coreboot.org/8128 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-12libpayload: Add Rock Chip drivershuang lin
Add support: 1)Support driver rktimer 2)Support driver rkserial BUG=chrome-os-partner:29778 TEST=emerge-veyron libpayload Original-Change-Id: I2cccedf3b62883dd372842a7972e93f2ebbfb282 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206184 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> (cherry picked from commit 387450d7c36b201bd177d46eb9f1d280fc043aab) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia6b7a8ee2439a6f2bf7577df822d3f4f3a1e441c Reviewed-on: http://review.coreboot.org/8127 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-01-11mainboard/lenovo/x201/romstage.c: Remove unused functionEdward O'Callaghan
Function was orginally used for reverse engineering. Change-Id: I646dddd39e61b59358b29a49239c0a1de77c7e55 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8158 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2015-01-10ACPI: Add acpi_is_wakeup_s3() for romstageKyösti Mälkki
This replaces acpi_is_wakeup_early(). Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8187 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10AMD binaryPI: Drop ramtop via nvramKyösti Mälkki
If HAVE_ACPI_RESUME gets implemented, EARLY_CBMEM_INIT is required too. Change-Id: I8c7932297e0938eff629d1e46081ccf3e7690aea Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8185 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10ACPI: Prepare for HAVE_ACPI_RESUME changesKyösti Mälkki
Change-Id: I71d522b135dff8b3c287699cc649caece9e4342c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8186 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10Fix mainboard names for daisy and peach_pitDavid Hendricks
This just fixes name members of mainboard_ops for daisy and peach_pit, which were never officially supported but used for development and proof-of-concept. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ia1f9b62bc9d91ed634ec1eaa7f907e8aed977f96 Reviewed-on: http://review.coreboot.org/8184 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-10haswell: Fix MRC cache to use CBFSKyösti Mälkki
Place the mrc.cache file at top of CBFS. There is no real requirement for it to have a fixed location though. Change-Id: Ibebe848a573b41788c9d84388be8ced68957f367 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7962 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-10macbook21: Add CST entriesAxel Holewa
Due to the CST entries the machine uses less power running GNU/Linux-libre. This can be seen by monitoring CPU temperature and time left the machine can run on battery. CPU temperature measurements have been done with lm_sensors, battery querying with acpi. Tests have been done before applying this patch and after. In both cases the battery was fully loaded and the machine powered up on battery, without AC. In both tests the machine was idleing for more than 1 hour. Without this patch battery was predicted to last 01:52:30 hours, CPU temperature first measurement showed 38 degrees. After 15 min idle, temperature has reached its maximum value in this test of 61 and 62 degrees (Core 0 and 1). Fan speed begins to increase shortly after 15 min. From its minimal value 1800 rpm it reaches 3100 rpm after 40 min. CPU temperature did not increase any further. After 60 min idle, the battery was predicted to still last 57 min. With this patch battery was predicted to last 02:22:40 hours. That is plus 30 min. CPU temperature begins at 35 degrees. After 15 min temperature has reached 45 degrees; after 30 min it has reached the maximal temperature during this test of about 50 degrees. That is 10 degrees improvement. The fan stayed at minimal speed. After 60 min idle, the battery was predicted to still last 01:22:48 hours; a 25 minute improvement. Change-Id: I6b2173df1dc09300329b61b51b79f4b9f4a8fb13 Signed-off-by: Axel Holewa <mono@posteo.de> Reviewed-on: http://review.coreboot.org/7923 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09Primitive memory testDavid Hendricks
This adds a generic primitive memory test. We should look into using tests in src/lib/ramtest.c, but they seem to rely too heavily on x86 asm and this test has been useful on multiple ARM platforms. BUG=none BRANCH=none TEST=builds and runs on nyan Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ia0fb4e12bc59bf708be13faf63c346b531eb3aed Original-Reviewed-on: https://chromium-review.googlesource.com/186309 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e7625c15415eaf6053ce32b67d9d6ab18d776f5f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: src/lib/Makefile.inc Change-Id: I34e7aedfd167199fd5db4cd4a766b2b80ddda79b Reviewed-on: http://review.coreboot.org/8150 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09nyan*: I2C: Fix bus clear BC_TERMINATE naming.Tom Warren
In the original fix for the 'Lost arb' we were seeing on Nyan* during reboot stress testing, I had the name of BC_TERMINATE's bit setting wrong. Fix this to use the IMMEDIATE (1) setting. The setting didn't change, just the name. According to Julius this is the optimal setting for bus clear in this instance. Also widened the SCLK_THRESHOLD mask to 8 bits as per spec. BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Tested on nyan. Built for nyan and nyan_big. Original-Change-Id: I19588690924b83431d9f4d3d2eb64f4947849a33 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206409 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 76e08d0cb0fb87e2c75d3086930f272b645ecf4e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If187ddf53660feaceab96efe44a3aadad60c43ff Reviewed-on: http://review.coreboot.org/8152 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-01-09tegra124: fix and fine tune the warm boot codeJoseph Lo
We assume that the clock rate of SCLK/HCLK/PCLK was 408MHz which was same as PLLP. But that is incorrect, BootROM had switched it to pllp_out2 with the rate 204MHz. So actually the warm boot procedure was running at the condition of SCLK=HCLK=PCLK=pllp_out2 with the rate 204MHz. And the CPU complex power on sequences were different with what we used in kernel and Coreboot. Fix up the sequence as below. * enable CPU clk * power on CPU complex * remove I/O clamps * remove CPU reset Update the time of the CPU complex power on function for record. * power_on_partition(PARTID_CRAIL): 528 uSec * power_on_partition(PARTID_CONC): 0 uSec * power_on_partition(PARTID_CE0): 4 uSec Finally, removing the redundant routine of a flow controller event with (20 | MSEC_EVENT | MODE_STOP). BUG=chrome-os-partner:29394 BRANCH=none TEST=manually test LP0 with lid switch quickly and make sure the last write to restore register successfully Original-Change-Id: Ifb99ed239eb5572351b8d896535a7c451c17b8f8 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205901 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> (cherry picked from commit 4194a9af3999da4b061584cda9649944ec0fdfb1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If21d17dc888b2c289970163e4f695423173ca03d Reviewed-on: http://review.coreboot.org/8151 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-01-09AMD binaryPI 00730F01: Switch to per-device ACPIKyösti Mälkki
Change-Id: Iad31ae3e511c8ebacc973b2d8a8e3bfca719ee7c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7583 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09cpu/amd/pi: Use acpi_is_wakeup()Kyösti Mälkki
Propagate commit 9107e53 from amd/agesa and fix some related #includes under cpu/amd/pi. Change test to return true on S2 wakeup too. In S2 CPU would have been powered down so MTRR recovery is required. Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8171 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09amd/agesa/family12/northbridge.c: Indent (tab) fixEdward O'Callaghan
Trivial; Use tab over space for indent. Change-Id: Iba0e006197a020157b11746dd4999d87a8ca8d97 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8015 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09tegra: i2c: re-init i2c controller after resetJimmy Zhang
This serves as supplemental patch to CL:197732. After clearing bus, we should also redo controller init (because controller has been reset before bus clear). On the upper layer, upon receiving error return status, it should just retry instead of simply call cpu_reset(). BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Built and tested on nyan and nyan_big. Original-Change-Id: Ib526bc730cb73ffef8696fc2a6a2769d6e71eb9e Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/202784 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 06f8917c70ddca88c847d0f15ebe7f286a3f6338) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1d8bc43d730b53fe7f2dad8713831311e96e3984 Reviewed-on: http://review.coreboot.org/8145 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-09cbfstool: Fix help display messageFurquan Shaikh
For arm64, the machine type is arm64 in cbfstool, however it was displayed as aarch64 in help message. This patch corrects it. BUG=None BRANCH=None TEST=None Original-Change-Id: I0319907d6c9d136707ed35d6e9686ba67da7dfb2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204379 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 1f5f4c853efac5d842147ca0373cf9b5dd9f0ad0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I00f51f1d4a9e336367f0619910fd8eb965b69bab Reviewed-on: http://review.coreboot.org/8144 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09Set custom AR_ for each classDaisuke Nojiri
TEST=Booted Nyan Blaze BUG=none BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I7e822e16117240f732ac55bb2c3816486a3e10cc Original-Reviewed-on: https://chromium-review.googlesource.com/204870 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 967455d6fed014f82198de4987ec103bb7c33d25) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I88025887fb0134f1e75028e0a4ed0c78af281c96 Reviewed-on: http://review.coreboot.org/8143 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09elog: Add ELOG_TYPE_BOOT event using fake boot count if necessaryDavid Hendricks
This makes it so that we always log the generic "system boot" event. If boot count support has not been implemented, fake it. BUG=chrome-os-partner:28772 BRANCH=nyan TEST=booted on Big, ran "mosys eventlog list" and saw "System boot" event logged with boot count == 0 Original-Change-Id: I729e28feb94546acf6173e7b67990f5b29d02fc7 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204525 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 2598dc63ddc0d76bcdf9814cadd4c75653fd9832) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieb4e2e36870e97d9c5f88f0190291863a65a6351 Reviewed-on: http://review.coreboot.org/8142 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09samus: Updates from P2 buildDuncan Laurie
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be swapped with GPIO69 - Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD - Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround - In order to support both P2A and P2B with one firmware image we need to read the EC board version and use the right SPD GPIO for bit3 - Touchpad I2C address changed to 0x4a/0x26 BUG=chrome-os-partner:29502 BRANCH=None TEST=boot on P2A and P2B boards Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204818 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d Reviewed-on: http://review.coreboot.org/8135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09x86: Initialize drivers in SMM context if neededDavid Hendricks
This adds a block in the SMI handler to call init functions for drivers which may be used in SMM. A static variable is used to ensure the init functions are only called once. BUG=chrome-os-partner:29580 BRANCH=mccloud TEST=Built and booted on mccloud, system no longer hangs when pressing power button at the dev mode screen. Also tested on parrot. Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I225f572f7b3072bec2bc06aac3fb50d90a2e30ee Original-Reviewed-on: https://chromium-review.googlesource.com/204764 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9315c485deb5f24df753e2d69f4819b2cb6accc2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8d2b21765c35c7ac7746986d5334dca17dcd6861 Reviewed-on: http://review.coreboot.org/8134 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09samus: Enable EC ALS deviceDuncan Laurie
Enable the ACPI Device for the EC ALS. BUG=chrome-os-partner:24208 BRANCH=None TEST=build and boot on samus, add acpi-als driver to the kernel and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw Original-Change-Id: I9e957464f835d5bd96d4806f896ac60db9dea5dc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a4f78b0b78c53bc0397d9a21dd8f3fa040f41616) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib83d6211d323770c9498180a7721d45e4aefca9d Reviewed-on: http://review.coreboot.org/8133 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09chrome ec: Add ACPI Device for ALS if enabledDuncan Laurie
The EC can export ALS information if the sensor is attached to it directly rather than to the host. This adds a basic ACPI ALS device and implements the required information. The kernel does not use the _ALR tuple set but it is required by the ACPI spec so this just adds the sample two point response curve defined in ACPI 5.0 section 9.2.5. The EC does not currently send events for lux value changes so a polling interval of 1 second is defined. BUG=chrome-os-partner:24208 BRANCH=None TEST=build and boot on samus, add acpi-als driver to the kernel and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw Original-Change-Id: Id29b72a68aa21c1a7c71d5f87223ac010cef0377 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 81f44b33b87a6ee3079b8ef6efffacd0eeb0283f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5a0ccd30e8b453675beaf7d0363dbfa162bd5b3f Reviewed-on: http://review.coreboot.org/8132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09samus: Updates for P2 boardDuncan Laurie
- RAM ID3 moved to GPIO65 to avoid Top Block Swap strap on GPIO66 - LTE_POWER_ON connection removed BUG=chrome-os-partner:29502 BRANCH=None TEST=none yet, preparing for new board Original-Change-Id: I521fe963cbed57ef5f56cfb0e89aec50bfc48b21 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203186 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1eb65e058307a172f0af9c27d2d2d87d1b78c514) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibf16dcfd83242c487232f34a310c9f6b2cb69314 Reviewed-on: http://review.coreboot.org/8131 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload: Reorder default memcpy, speed up memset and memcmpJulius Werner
The current default memcpy first copies single bytes to align the amount, then copies the rest as full words. In practice, the start of a buffer is much more likely to be word-aligned then the end, and aligned word access are usually more efficient. This patch reorders those accesses to first copy as many full words as possible and then finish the rest with byte accesses to optimize this common case. This fixes a data abort when using USB on ARM without CONFIG_GPL. Due to some limitations of how DMA memory is set up in coreboot on ARM, it currently does not support unaligned accesses. (This could be fixed with a more complicated patch, but it's usually not an issue... unless, of course, your memcpy happens to be braindead). Also add word-aligned accesses to memset and memcmp while I'm at it, and make memcmp's return value standard's compliant. BUG=chrome-os-partner:24957 TEST=Manual Original-Change-Id: I2a7bcb35626a05a9a43fcfd99eb958b485d7622a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203547 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 05a64d2e107e1675cc3442e6dabe14a341e55673) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0030ca8a203c97587b0da31a0a5e9e11b0be050f Reviewed-on: http://review.coreboot.org/8126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload arm64: Add gdb stub for arm64Furquan Shaikh
Add stub implementation for gdb arm64 support. Currently all functions are kept empty to enable proper compilation of depthcharge and libpayload. As we get more clear about context management and stuff, we can add details for gdb as well. BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I0a8729671ab0764d424c0e3d50af86433d05b1e8 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204877 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit d24e5c26b56a9882b3450b1e4988b56c3d73efd1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9b7d3d7060dd827ef4a46865e0f9a2b4e063d07d Reviewed-on: http://review.coreboot.org/8125 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload arm64: Add selfboot.c required by depthchargeFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I2569cadf2d34f7211892f100ba715486d824b921 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204611 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit dd9e06e41da043a48b469a011c010a10a1a3b25a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I37fbc8cfea0870e7167ffa47dd63fc548e18c82e Reviewed-on: http://review.coreboot.org/8124 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload: Fix baseaddr access in serial/tegra.cFurquan Shaikh
Fix baseaddr typecast to allow use in 32- and 64-bit systems BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ie5ded744d75a0ae4d1428d04ff2478bdfe54d146 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204424 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit b56814fe5fc7d3a2fdfb324d4baafb27a9d3ffd6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icedc1c819e39b92a0dd92e98f848e15b3039dfbe Reviewed-on: http://review.coreboot.org/8123 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload arm64: Correct function names for tlb invalidationFurquan Shaikh
Correct function names to make them consistent with depthcharge calling convention BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I0fd8f7f929c3fe268710362d1fc19f9e15c4a23b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204423 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 36008e728b840d85bb98225c7bb1420b993181de) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4b446da8f2c273385ee885c4870966e18ba2a7a6 Reviewed-on: http://review.coreboot.org/8122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload arm64: Add dummy_media fileFurquan Shaikh
This is required for proper compilation of libpayload and depthcharge BUG=None BRANCH=None TEST=libpayload compiles successfully for rush Original-Change-Id: I305b58b978fd335e20abd7664c3ee2a6c1ea8384 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204422 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit eef115c2371c6f7259bf808e0448f24a5b3491ab) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icd6a5b8a0bdb125de4913fc82be8cb2a5aef5dc9 Reviewed-on: http://review.coreboot.org/8120 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload: Add remote GDB supportJulius Werner
This patch adds the ability to attach a GDB host through the UART to a running payload. Libpayload implements a small stub that can parse and respond to the GDB remote protocol and provide the required primitives (reading/writing registers/memory, etc.) to allow GDB to control execution. The goal of this implementation is to be as small and uninvasive as possible. It implements only the minimum amount of primitives required, and relies on GDB's impressive workaround capabilities (such as emulating breakpoints by temporarily replacing instructions) for the more complicated features. This way, a relatively tiny amount of code on the firmware side opens a vast range of capabilities to the user, not just in debugging but also in remote-controlling the firmware to change its behavior (e.g. through GDBs ability to modify variables and call functions). By default, a system with the REMOTEGDB Kconfig will only trap into GDB when executing halt() (including the calls from die_if(), assert(), and exception handlers). In addition, payloads can manually call gdb_enter() if desired. It will print a final "Ready for GDB connection." on the serial, detach the normal serial output driver and wait for the commands that GDB starts sending on attach. Based on original implementation by Gabe Black <gabeblack@chromium.org>. BUG=chrome-os-partner:18390 TEST=Boot a GDB enabled image in recovery mode (or get it to hit a halt()), close your terminal, execute '<toolchain>-gdb --symbols /build/<board>/firmware/depthcharge_gdb/depthcharge.elf --directory ~/trunk/src/third_party/coreboot/payloads/libpayload --directory ~/trunk/src/platform/depthcharge --directory ~/trunk/src/platform/vboot_reference --ex "target remote <cpu_uart_pty>"' and behold the magic. (You can also SIGSTOP your terminal's parent shell and the terminal itself, and SIGCONT them in reverse order after GDB exits. More convenient wrapper tools to do all this automatically coming soon.) Original-Change-Id: Ib440d1804126cdfdac4a8801f5015b4487e25269 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202563 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 9c4a642c7be2faf122fef39bdfaddd64aec68b77) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9238b4eb19d3ab2c98e4e1c5946cd7d252ca3c3b Reviewed-on: http://review.coreboot.org/8119 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload: Introduce new Kconfig to explicitly allow GPL codeJulius Werner
There have been leaks of GPL code into libpayload for a while now, for new features or improvements that require third party code with no adequate alternative among BSD-licensed software. It seems silly and counter-productive to keep holding back features and performance improvements from libpayload for a use-case (proprietary payloads) that doesn't even seem to be implemented anywhere to date. Open-source payloads should not need to suffer to appease commercial ones. Instead, this patch introduces a new Kconfig option to explicitly allow inclusion of GPL code. It will use Kconfig dependencies and/or Makefile rules to ensure that no GPL code can end up in the final payload if that option is unset, allowing proprietary payloads to keep working with the existing BSD-licensed feature set. New features and patches (that are sufficiently separate and self-contained to allow guarding through this config option) can choose whether to import GPL code, and need to depend on this option if they do. Also clean up all (known) existing uses of GPL code to depend on the new option, add some recent third-party imports to the LICENSES file, and relicense the selfboot.c files to BSD with permission of the author. BUG=chrome-os-partner:24957 TEST=Compiled Falco and Nyan_Big both with and without the new option, disassembled output binaries to ensure that memcpy() looks as expected. Original-Change-Id: I6e3a75b1a8e46291c75a876844c7a01f7d3f2a0e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203513 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit d8e5a9fdf583b5ac861f34baea6a16c4d8536512) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I446fef028264c793b946dd9f765e446bf708b4db Reviewed-on: http://review.coreboot.org/8118 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09libpayload: Rework exception hook interfaceJulius Werner
This patch makes some slight changes to the exception hook interface. The old code provides a different handler hook for every exception type... however, in practice all those hook functions often need to look very similar, so this creates more boilerplate than it removes. The new interface just allows for a single hook with the exception type passed as an argument, and the consumer can signal whether the exception was handled through the return value. (Right now this still only supports one consumer, but it could easily be extended to walk through a list of hooks if the need arises.) Also move the excepton state from an argument to a global. This avoids a lot of boilerplate since some consumers need to change the state from many places, so they would have to pass the same pointer around many times. It also removes the false suggestion that the exception state was not global and you could have multiple copies of it (which the exception core doesn't support for any architecture). On the ARM side, the exception state is separated from the exception stack for easier access. (This requires some assembly changes, and I threw in a few comments and corrected the immediate sigils from '$' to the official '#' while I'm there.) Since the exception state is now both stored and loaded through an indirection pointer, this allows for some very limited reentrance (you could point it to a different struct while handling an exception, and while you still won't be able to return to the outer-level exception from there, you could at least swap out the pointer and return back to System Mode in one go). BUG=chrome-os-partner:18390 TEST=Made sure normal exceptions still get dumped correctly on both archs. Original-Change-Id: I5d9a934fab7c14ccb2c9d7ee4b3465c825521fa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202562 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 97542110f0b385b9b8d89675866e65db8ca32aeb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> *** Squashed to prevent build failures. *** libpayload: align arm64 with new exception handling model The exception handling was previously updated, however the arm64 changes raced with hat one. Make the arm64 align with the new model. Without these changes compilation will fail. BUG=None BRANCH=None TEST=Can build libpayload for rush. Original-Change-Id: I320b39a57b985d1f87446ea7757955664f8dba8f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204402 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0080df41b311ef20f9214b386fa4e38ee54aa1a1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9a0bb3848cf5286f9f4bb08172a9f4a15278348e Reviewed-on: http://review.coreboot.org/8117 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload: Add ability to unregister output driverJulius Werner
This patch adds a console_kill_output_driver() function, which can remove a previously registered output driver. This is mostly useful when you overlay some output channel over another, such as when the GDB stub takes direct control of the UART (and thus has to get rid of the existing serial output driver). BUG=chrome-os-partner:18390 TEST=None Original-Change-Id: I6fce95c22fd15cd321ca6b2d6fbc4e3902b1eac3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202561 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 87680a246429d24e99b7b477b743c357f73b752c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I50001cee4582c962ceedc215d59238867a6ae95a Reviewed-on: http://review.coreboot.org/8116 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload: Add support for arm64 in libpayloadFurquan Shaikh
Basic support for arm64 is enabled in libpayload. Features added: 1) mem* operations in assembly. 2) Basic exception handling and support for testing exceptions. 3) Caching support. Tested with arm64-generic board compilation. BUG=None BRANCH=None TEST=Compilation successful Original-Change-Id: I4e86301f9c6383abc078e2b70071fb84bd6e4741 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/187067 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit a70d13f3d225535843ab352290eab2e1ec7a9b4b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie3affe6a2bdd4fed3058de739d4c6aa573e5b251 Reviewed-on: http://review.coreboot.org/8063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-01-09storm: Reserve memory from 0x4000_0000-0x414f_ffffDavid Hendricks
This marks the bottom chunk of memory, which is used by various IP blocks, as reserved so that Depthcharge does not attempt to wipe it. BUG=chrome-os-partner:30067 BRANCH=storm TEST=Built and booted for storm, depthcharge shows: Wipe memory regions: [0x00000041500000, 0x00000051000000) [0x000000510006a0, 0x00000053000000) [0x00000054141260, 0x0000007fffd000) Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I8f782f16d13620b705e1b3fbeca21dc8705b7e77 Original-Reviewed-on: https://chromium-review.googlesource.com/206516 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit f66f553f1594c481a74b7f40b4b1088600b1a70a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I82d118abc86052f5e32f6195a4efd04fe315be5a Reviewed-on: http://review.coreboot.org/8149 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09storm: Increase DRAM size to 1024MBDavid Hendricks
BUG=chrome-os-partner:29871 BRANCH=storm TEST=builds and boots (sort of) Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I82e1792152d17d689e129c9941e8972221bde366 Original-Reviewed-on: https://chromium-review.googlesource.com/206011 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 8995fde9bdfb8af8fb86525fd67a61614881f78e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ice4a5382903b0ab6e085c39d05c46601373080eb Reviewed-on: http://review.coreboot.org/8148 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09storm: USB fixes for proto0Vadim Bendebury
The actual storm device has a single USB interface, which needs to be explicitly turned on using GPIO51. BUG=chrome-os-partner:29871 TEST=verified that depthcharge finds and boots a kernel from USB stick Original-Change-Id: Iaf868812c96e1e3289b9403855c4cc8f87c1e368 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205329 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> (cherry picked from commit aa22376ffac22309a298dfa844e7f61c97d57d3e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic0f34622e61a65a0540c0f3fca26fb057fa85fb7 Reviewed-on: http://review.coreboot.org/8147 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-09spi: Add Spansion flash S25FL128PVadim Bendebury
Storm devices use more recent Spansion flash, add its description to the table of supported devices. BUG=chrome-os-partner:29871 TEST=the updated firmware boots all the way to depthcharge Original-Change-Id: I81661c01ae679d49918e40d940b8d348f3081f9a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205182 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit ea7bb1cf65b7130164b869fef09c55138100206b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1e0136a5c575951b4e464aab0f380f19e886a84f Reviewed-on: http://review.coreboot.org/8146 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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