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2013-03-14lynxpoint: Add new GPIO interface for Lynxpoint-LPDuncan Laurie
The low power variant of the chipset introduces a completely new interface to the GPIOs. This is a 1KB region and so needs to be moved as well so it does not conflict with other IO regions. Also expose the gpio_get functions to ramstage and move the prototypes to pch.h so they can be used for both GPIO interfaces. Change-Id: I20bc18669525af16de8cdf99f0ccfa9612be63ad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2648 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-14haswell: Add ULT CPUID and updated microcodeDuncan Laurie
This adds microcode ffff000a and the CPUIDs for ULT. Change-Id: I341c1148a355d8373b31032b9f209232bd03230a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2647 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-14haswell: Add ULT device IDsDuncan Laurie
Device IDs for northbridge and GPU. Also mask off the lock bit in the memory map registers. Change-Id: I9a4955d4541b938285712e82dd0b1696fa272b63 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2646 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-14lynxpoint: Add Kconfig entry for Low Power chipsetDuncan Laurie
There are enough subtle differences that it is useful to have a Kconfig entry to differentiate the ULT/LP chipet from the desktop/mobile versions. Change-Id: I04ca1bc6f90bcf9e6994ea7125c98347e8def898 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2645 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-14lynxpoint: ME to BIOS Payload UpdatesAaron Durbin
This commit contains a bevy of updates: - PCI device id is updated to match Lynx Point EDS in the ME driver. - Allocate the memory to store the consumption of the MBP. - me_bios_payload structure is now a structure of pointers that point into the allocated memory. - The ICC profile structure was updated to correctly reflect the documentation. Verfied that output of MBP reading can handle unknown items. Change-Id: I43cc45e6b797444c105e7c842eb5684e9c104687 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2641 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14lynx point: add new ME status informationAaron Durbin
According to the 0.8.0 ME BWG this is a new state. It's not very clear what exactly it entails, but the Basking Ridge CRB was tripping it when MRC_DEBUG was enabled (presumably because of a DID timeout). Instead of 0x17 one can now see the proper message for this state. Change-Id: I5bda1de7d3d957d38a4760a02dcd170ec48782e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2640 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14graysreef: update platform informationAaron Durbin
Some of the Lynx Point ids were off. Correct those and make the pei data BAR fields consistent with the others. Change-Id: I4102439588362cdb94643bd1ce69c9fa4278329e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2622 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14OT200: reset MFGTP7 (backlight pwm)Christian Gmeiner
The CS5536 companion device has three different power domains. * working domain * standby domain * RTC domain When the system is "off" only the standby domain is powered. MFGPT[7:6] are member of the standby power domain. MFGPT7 is used to control the backlight of the device and so the timer gets used and configured during system boot. If the system does a reboot the timer stays configured and the Linux driver can not use it: "ot200-backlight: ot200-backlight.0: MFGPT 7 not availale" The cs5535-mfgpt has a function to hard-reset all MFGPTs but the system hangs after the first access to a MFGPT register - cause unknown. /* * This is a sledgehammer that resets all MFGPT timers. This is required by * some broken BIOSes which leave the system in an unstable state * (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to * whether or not this secret MSR can be used to release individual timers. * Jordan tells me that he and Mitch once played w/ it, but it's unclear * what the results of that were (and they experienced some instability). */ static void reset_all_timers(void) { uint32_t val, dummy; /* The following undocumented bit resets the MFGPT timers */ val = 0xFF; dummy = 0; wrmsr(MSR_MFGPT_SETUP, val, dummy); } After playing around with this undocumented MSR it looks like I only need to set bit 7 to free the MFGPT7. BTW, all MFGPT[0:5] will be reset during pll_reset(). Change-Id: I54a8d479ce495b0fc2f54db766a8d793bbb5d704 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/2527 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-14haswell: remove GPIO60 memory reset gate on S3 transitionDuncan Laurie
This is no longer tied to a GPIO but has a proper chipset pin. Change-Id: Iba70338e8c67e3c3c1cb32e69bfea1282fda8cb5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2643 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: remove explicit pcie config accessesAaron Durbin
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2618 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14lynxpoint: PMIR register renameAaron Durbin
The register that controls global reset is named the Power Mangement Initialization Regiser (PMIR). Update the defines to reflect the documentation. Additionally, there is no core well reset control according to the EDS. There is, however, a CF9 lock field to lock this register down. Change-Id: I773c33bec63a06cdb869eb9f94553d476e492798 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2619 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14lynxpoint: Management Engine UpdatesAaron Durbin
The ME9 requirements have added some registers and changed some of the MBP state machine. Implement the changes found so far in the ME9 BWG. There were a couple of reigster renames, but the majority of th churn in the me.h header file is just introducing the data structures in the same order as the ME9 BWG. Change-Id: I51b0bb6620eff4979674ea99992ddab65a8abc18 Signed-Off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2620 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: Properly Guard Engergy Policy by CPUIDAaron Durbin
The IA32_ENERGY_PERFORMANCE_BIAS MSR can only be read or written to if the CPU supports it. The support is indicated by ECX[3] for cpuid(6). Without this guard, some Haswell parts would GP# fault in this routine. No more GP# while running on haswell CRBs. Change-Id: If41e1e133e5faebb3ed578cba60743ce7e1c196f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2639 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-14haswell: add PCI id supportAaron Durbin
In order for coreboot to assign resources properly the pci drivers need to have th proper device ids. Add the host controller and the LPC device ids for Lynx Point. Resource assignment works correctly now w/o odd behavior because of conflicts. Change-Id: Id33b3676616fb0c428d84e5fe5c6b8a7cc5fbb62 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2638 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-14haswell: Remove logic to send dram init done to MEAaron Durbin
The reference code sends the dram init done command to the ME. Therefore, there is no need for coreboot to do this. Change-Id: I6837d6c50bbb7db991f9d21fc9cdba76252c1b7b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2633 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14basking ridge: update gpio, spd addresses, and OCAaron Durbin
Even though this is under the graysreef board it really applies to the Basking Ridge board. A subsequent patch will rename graysreef to baskingridge. The GPIO pins were updated to reflect the Basking Ridge schematics as well as the DIMM spd addresses and USB over current pins. Change-Id: Ice4e05f5203de3024cd463dfccf0bcfec1e247c1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2632 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: notes and updates.Aaron Durbin
Add a FIXME about checking a MCHBAR register that isn't setup yet. Also, remove revision updating because I can't find anything in the docs that suggest this is required for haswell. Change-Id: Ia8a6e08f82e18789e31c6c2ec2c1d63740c18dc4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2631 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: align pei_data structure with intel-frameworkAaron Durbin
The intel-framework code has an updated pei_data structure. Use the new structure and revision. Also, remove the scrambler seed saving in CMOS since that appears to be handled in the saved data from the reference code. Change-Id: Ie09a0a00646ab040e8ceff922048981d055d5cd2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2630 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: use #defines for constants in udelay.cAaron Durbin
Change the hard coded values in udelay.c to use the #defines for MSRs and BCLK. Change-Id: I2bbeb0b478d2e3ca155e8f82006df86c29a4f018 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2629 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14Mainboard: Add support for Grays ReefAaron Durbin
Grays Reef is one of Intel's CRBs for the Haswell processor. The platform is named Shark Bay. GPIOs were the main focus so IRQ routing and ACPI still needs to be further looked at. Change-Id: Ie94b7af66f772714992a92612c76ca93b9b27088 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2621 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: Add LPT LP device IDs to platform reportDuncan Laurie
Boot haswell ULT and see LPT reported properly. Change-Id: I48344a8dde6adbbf331c91231342de45b1b6c32a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2697 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: Update GPU power management setupDuncan Laurie
This is the steps outlined in the BWG. It seems this is a lot simpler now (so far) which is good. To test, boot to chromeos with 3.7 kernel + i915.preliminary_hw_support=1 and see that the i915 driver complains a lot less than before and that a splashscreen is displayed. Change-Id: I722c90ecd351860949cedab24533f6c10e5b90e5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2696 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14lynxpoint: Update IOBP programming methodDuncan Laurie
This follows the new method outlined in the LPT BWG. It is also very pedantic about its operation so it is easier to read and compare against the docs and the reference code implementation. Change-Id: I235d634cded0c75ec0e9f53488f5b366107a18fa Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2694 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14x86: SMM Module SupportAaron Durbin
Add support for SMM modules by leveraging the RMODULE lib. This allows for easier dynamic SMM handler placement. The SMM module support consists of a common stub which puts the executing CPU into protected mode and calls into a pre-defined handler. This stub can then be used for SMM relocation as well as the real SMM handler. For the relocation one can call back into coreboot ramstage code to perform relocation in C code. The handler is essentially a copy of smihandler.c, but it drops the TSEG differences. It also doesn't rely on the SMM revision as the cpu code should know what processor it is supported. Ideally the CONFIG_SMM_TSEG option could be removed once the existing users of that option transitioned away from tseg_relocate() and smi_get_tseg_base(). The generic SMI callbacks are now not marked as weak in the declaration so that there aren't unlinked references. The handler has default implementations of the generic SMI callbacks which are marked as weak. If an external compilation module has a strong symbol the linker will use that instead of the link one. Additionally, the parameters to the generic callbacks are dropped as they don't seem to be used directly. The SMM runtime can provide the necessary support if needed. Change-Id: I1e2fed71a40b2eb03197697d29e9c4b246e3b25e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2693 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14libpayload: add support for vboot_handoffAaron Durbin
The vboot_handoff structure needs to be parsed from the coreboot tables. Add a placeholder in sysinfo as well as the ability to parse the coreboot table entry concering the vboot_handoff structure. Built with unified boot loader and ebuild changes. Can find and use the VbInitParams for doing kernel selection. Change-Id: If40a863b4a445fa5f7814325add03355fd0ac647 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2720 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14libpayload: Turn the endian conversion macros into functions.Gabe Black
In their current macro form, any arguments that are expressions will be evaluated multiple times. That can cause problems if they have side effects, and might not even compile if the overall expression is ambiguous, for instance if you pass in foo++. Built with code that previously wouldn't compile because the macros expanded to ambiguous expressions. Change-Id: I378c04d7aff5b4ad40581930ce90e49ba7df1d3e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2719 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14Support ITE IT8518 embedded controller running Quanta's firmwareStefan Reinauer
Change-Id: Ib406b9d5005243d79eea5d2c0c6c86b5aa949891 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2721 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14libpayload: Generalize and redistribute timekeeping codeGabe Black
The timekeeping code in libpayload was dependent on rdtsc, and when it was split up by arch, that code was duplicated even though it was mostly the same. This change factors out actually reading the count from the timer and the speed of the timer and puts the definitions of ndelay, udelay, mdelay and delay into generic code. Then, in x86, the timer_hz and timer_get_raw_value functions which used to be in depthcharge were moved over to libpayload's arch/x86/timer.c. In ARM where there isn't a single, canonical timer, those functions are omitted with the intention that they'll be implemented by a specific timer driver chosen elsewhere. Change-Id: I9c919bed712ace941f417c1d58679d667b2d8269 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2717 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14libpayload: Put dump_td/dump_ed in ohci.c behind #ifdef USB_DEBUGGabe Black
This function is static and not used in that file. To avoid the compiler complaining about that fact, put the two functions and the call to dump_ed (currently #if 0) behind #ifdef USB_DEBUG Change-Id: Ic373313b5fff81f09800f286b32238350ab699c6 Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2716 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: always use MMIO PCI config accessesAaron Durbin
Add a bootblock.c file for the northbridge and setup the PCIEXBAR as the first thing using IO PCI config acceses. After that all PCI config accesses can use MMIO. Change-Id: I51d229c626c45705dda1757c2f14265cbc0e6183 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2617 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: Add initial support for Haswell platformsAaron Durbin
The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore, the southbridge support is included as well. The basis for this code is the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires more attention, but this is a good starting point. This code partially gets up through the romstage just before training memory on a Haswell reference board. Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2616 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14libpayload: Don't declare the loop counter within the for loopGabe Black
'for' loop initial declarations are only allowed in C99 mode I didn't realize we don't enable 14 year old features when building libpayload, and I must have accidentally not rebuilt everything when making my final tweaks to my earlier change. Change-Id: I6caeeffad177b6d61fa30175f767e85084c061f4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2718 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-03-14exynos5250: add RAM resource beginning at physical addressDavid Hendricks
The original code attempted to reserve a space in RAM for coreboot to remain resident. This turns out not to be needed, and breaks things for the kernel since the exynos5250-smdk5250 kernel device tree starts RAM at 0x40000000. (This patch was originally by Gabe, I'm just uploading it) Change-Id: I4536edaf8785d81a3ea008216a2d57549ce5edfb Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2698 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-03-13Eagleheights DSDT: Grant OS control through OSCMike Loptien
Change the OSC method to actually grant control of PCIe capabilities to the OS instead of granting no control. I believe the logic was backwards in the original commit. Bits should be set when granting control and cleared when not granting control. By setting the return value to 0x00, we effectively tell the OS that it cannot control any PCIe capability. See section 6.2.9 of the ACPI spec version 3.0 for more information. This edit is a duplication of the OSC method that is in the src/southbridge/intel/bd82x6x/pch.asl file. Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2714 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Don't do unaligned accesses during LZMA decompressionGabe Black
Use memcpy to access a uint32_t that's inherently unaligned due to the layout of the LZMA header format. Built and booted on Daisy and saw a data abort go away. Built and booted into developer mode on Link and verified that bitmaps were decompressed/displayed correctly. Change-Id: Id3ae746c04d23bcb0345cb71797bfa219479cc8f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2670 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Add size_t and ssize_t types for ARM and x86Gabe Black
Some new TPM drivers in depthcharge require that type. I added it to arch/types.h which seemed appropriate, but I'm not sure that's exactly the right header to use, or in other words if you'd get that type from libpayload the same way you'd get it if you were building a standard Linux program. Also, I attempted to determine what underlying types gcc would use, and while I think I picked the right ones I'm not 100% certain of that either. Change-Id: Ic5c0b4173c8565ede3bfce8870976d596d69e51d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2669 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Move over to the payload's stack during startupGabe Black
Don't keep using the coreboot stack on ARMv7. Change-Id: I734c5d77f8584e30ee0c720d41e21e3040f56db4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2668 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13exynos5250/snow: enable branch predictionDavid Hendricks
This enables branch prediction. We can probably find a better place to do this, but for now we'll do it in snow's romstage main(). Change-Id: I86c7b6bc9e897a7a432c490fb96a126e81b8ce72 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2701 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: ARCH-$(CONFIG_ARCH_ARMV7) was defined twice, make one POWERPCGabe Black
Change-Id: Ia85a7cd6a0b85119cce6b2f9c42a7fc31ffd9f97 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2654 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Add usb_generic_(create|remove) functions for unrecognized devicesGabe Black
It might be useful to provide a USB driver in the payload itself instead of in libpayload. For example there are multiple payloads being built and linked against the same libpayload, and they might not need or even want to have the same set of drivers installed. This change adds two new functions, usb_generic_create and usb_generic_remove, which behave like the usbdisk_create and usbdisk_remove functions which are defined for USB mass storage devices. If a USB device isn't recognized and claimed by one of the built in USB class drivers (currently hub, hid, and msc) and the create function is defined, then it will be called to give the payload a chance to use the device. Once it's removed, if usb_generic_remove is defined it will be called, effectively giving the payload notice. Built and booted depthcharge on Link. Built depthcharge for Daisy. Built a netbooting payload, called usb_poll() with those functions implemented, and verified that they were called and that the devices they were told about were reasonable and the same as what was reported by lsusb in the booted system. Change-Id: Ief7c0a513b60849fbf2986ef4ae5c9e7825fef16 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2666 Tested-by: build bot (Jenkins) Reviewed-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Split EHCI bulk transfers on packet boundaries over qTDsJulius Werner
EHCI controllers see transfers as a queue of transfer descriptors (qTDs), each of which can represent an aligned area of up to 20KB. Each qTD is processed separately, which means that a single USB packet cannot span multiple qTDs. While this should not be a problem according to the specification, some USB storage devices seem to get confused when a packet in the middle of a transfer is smaller than the maximum packet size (512 bytes) due to falling on a qTD boundary. This patch aligns the total transfer length per qTD to 512 bytes to avoid that problem (any excess bytes will simply roll over to the next qTD). Change-Id: I0b5db07507699a3861b30c1a5ee774c45dda7fdd Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/2651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: add support for 64-bit EHCI controllersVincent Palatin
Initialize the high part of the address and use 64-bit compatible descriptors. (waste a few bytes on 32-bit but should be harmless) Read USB stick on a SandyBridge system which has 64-bit EHCI. Change-Id: I59cc842459acecdde8f8bdd4795ebfeccb842c8f Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Stub out time keeping functions for ARM as wellGabe Black
These were currently stubbed out for PowerPC but not for ARM. Change-Id: I08f45174877bf5751d972078b8c53d82898b7f2b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2655 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: If no video drivers initialize in video_init, return 1.Gabe Black
Change-Id: I56f810dfa6654ac1e9d1696ad15e7f1b8bfe59bd Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-13libpayload: If there's no IO address space, don't try to use it for serialGabe Black
Change-Id: I01b1fa42139af925716cd5d57f96dc24da6df5a7 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2660 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: If there's no IO space, complain if the serial claims to use itGabe Black
Change-Id: I36c750d520ff034c9ca9b9af46bd99bd49af7355 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2659 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Consolidate io vs. mem mapped serial into accessor functionsGabe Black
This way we won't have two copies of the hardware init function, and three copies of the putchar, havechar, and getchar functions. Change-Id: Ifda7fec5d582244b0e163ee93ffeedeb28ce48da Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2657 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Make whether or not there's an IO address space configurableGabe Black
Default it to no to be consistent with the other architecture wide options (endianness), and turn it on explicitly for x86 and PowerPC. Change-Id: Idda26d580156bbbf08ea11b28abe75cfa6b594b2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2658 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13Update 3rdparty mark to latest repositoryStefan Reinauer
For google/stout binaries Change-Id: I4ef3f9cc35dfb6d27e1c9f074759f0e3ddee73c4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2635 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Start using only internal and compiler headers.Ronald G. Minnich
When building other payloads with lpgcc the -nostdinc flag was injected into CFLAGS, but when building libpayload itself some headers were being used from the host system. This change puts -nostdinc into the Makefile and xcompile script, fixes up one include path in include/inttypes.h, adds the compiler provided include directory to the include search path, and deletes the two now redundant stdint.h files. BUG=None TEST=With this and other changes, built libpayload and depthcharge for Daisy, Link, and Fox. BRANCH=None Change-Id: Ia7817fceab5297cd82ccc0d392330de0df61980e Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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