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2017-08-16AGESA: Cleanup ACPI S3 supportKyösti Mälkki
Due to low-memory corruptions S3 support has now been (at least temporarily) removed from AGESA platfroms. Should we bring it back one day, CAR teardown on S3 path will happen with an empty stack so ugly backup/recovery of the stack will no longer be used. If S3 feature is brought back, resume path code for FCH will also see partial rewrite and agesawrapper.c file will not be part of that. Change-Id: Ib38c04d0e74f600e0b719940d5e2530f4c726cfd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-16AGESA f14: Sacrifice ACPI S3 support for EARLY_CBMEM_INITKyösti Mälkki
A decision has been made that boards with LATE_CBMEM_INIT will be dropped from coreboot master starting with next release scheduled for October 2017. As existing implementation of CAR teardown in AGESA can only do either EARLY_CBMEM_INIT or ACPI S3 support, choose the former. ACPI S3 support may be brought back at a later date for these platforms but that requires fair amount of work fixing the MTRR issues causing low-memory corruptions. Change-Id: I5d21cf6cbe02ded67566d37651c2062b436739a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-16util/kbc1126: [cosmetic] change Makefile casingIdwer Vollering
Change-Id: Iac616fdb3de79f4f58c30a2eb674ed5152b6a6e4 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/21050 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-15soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definitionSubrata Banik
LPC pci config register BIOS Control (BC) - offset 0xDC bit 1 is for Lock Down. Change-Id: I4780d2e41c833c0146640f715759dbb0a948c4ab Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-15soc/intel/common/block: Fix PMC common block dependencyShaunak Saha
This patch fix the dependency for PMC common block code. PMC block use SLP_TYP macros and acpi_sleep_from_pm1 function which is defined in arch/acpi.h and guarded by CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES. So we need PMC common block to depend on that config for proper inclusion. Change-Id: I88077626aff3efba0a95b3aaee0dbd71344ccb42 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20964 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-15soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macrosV Sowmya
Rename BAR0 and BAR2 SRAM base and size macros to align with the spec. * PMC_SRAM_BASE_0 -> SRAM_BASE_0 * PMC_SRAM_SIZE_0 -> SRAM_SIZE_0 * PMC_SRAM_BASE_1 -> SRAM_BASE_2 * PMC_SRAM_SIZE_1 -> SRAM_SIZE_2 Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20539 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-15soc/intel/apollolake: Provide option to use Common MP InitBarnali Sarkar
This patch provides the option to use the common CPU Mp Init code by selecting a Config Token. CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT config token can be selected to use the Common MP Init Code, also where CPU MP Init is done before FSP-S Init. And if the config token is not selected, the old way of implementation will exist, where MP Init is been done after FSP-S. CQ-DEPEND=CL:*397551 BUG=none BRANCH=none TEST=Build and boot Reef Change-Id: I35d012785000d3f3bfcc34138cda9cd4591559f6 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-15superio/winbond/w83977tf: Drop early_serial.cKeith Hui
Early serial init on this superio is done by superio/winbond/common/early_serial.c and no board currently references this instance anymore. Change-Id: Iab8dd93663fc78ed0d8c6a5313bb6a1884d1a043 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-15440BX boards: Use combined RAM init routineKeith Hui
Change all 440BX boards to use the combined RAM init routine added in commit 078e3240 (northbridge/intel/i440bx: Merge RAM init routines) [1]. [1] https://review.coreboot.org/20676 Change-Id: I699db882189f99018d4a6fdcb00f9438b2a7a1bc Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-15440BX boards: Drop more unused #includes from romstageKeith Hui
Romstages of many 440BX boards included headers that are redundant. Remove them as part of a bigger cleanup effort. This finishes off what began in https://review.coreboot.org/20693. Change-Id: I102a4f6e492eb607b7f88d4c6e15072a8b7fdc46 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-15google/coral: Fetch SKU ID from ECPatrick Georgi
BUG=b:64468585 BRANCH=none TEST=with the other sku-id related patches applied, coreboot obtains the right SKU ID from EC Change-Id: I96a0e030bbc5f1c98165e70353340c413f8dc352 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-15ec/google: Add command to fetch SKU ID from ECPatrick Georgi
BUG=b:64468585 BRANCH=none TEST=with the other sku-id related patches applied, coreboot obtains the right SKU ID from EC Change-Id: I82e324407b4b96495a3eb3d4caf110f9eae05116 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-15soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao
The following changes can make system call into FSP siliconinit and exit from that until payloads. 1. Add frame to call fspsinit. 2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit. This patch was merged too early, and reverted. Originally reviewed on https://review.coreboot.org/#/c/20581 Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20687 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-15soc/intel/cannonlake: Add postcar stage supportLijian Zhao
Initialize postcar frame once finish FSP memoryinit This patch was merged too early and reverted. Originally reviewed on https://review.coreboot.org/#/c/20534 Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20688 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-15buildgcc: surround *.log with apostrophes when build failsIdwer Vollering
Apparently the script's output text is unclear. Emphasize the file name, keeping the dot to close the sentence. Change-Id: I1f214b71629eda5fc54e5671ce63e58948343656 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/21012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-15soc/intel/common/block: Add LPC Common code and use it for APLRavi Sarawadi
Add LPC common code to be shared across Intel platforms. Also add LPC library functions to be shared across platforms. Use common LPC code for Apollo Lake soc. Update existing Apollolake mainboard variants {google,intel,siemens} to use new common LPC header file. Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-15soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macroAaron Durbin
The PCH_P2SB_EPMASK macro takes a parameter. Ensure parenthesis are put around the parameter expansion. Change-Id: I978e9397036ea3630434982fe4ecd698877fe0d6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-15payloads/Makefile.inc: Add GRUB2 to list of payloadsNico Huber
Change-Id: Iea4a609631ac2007b7b1845ff540abc912004be0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-15payloads/external/GRUB2: Sanitize MakefileNico Huber
We were explicitly passing CC and TARGET_CC to configure but overwrote that decision later by passing CC (with the value of TARGET_CC) directly to a recursive make call. The latter overwrite was introduced because `unexport` alone doesn't work on variables that were specified on a make command line (they are added to MAKEOVERRIDES and passed to further re- cursive make calls). Instead of unexporting random variables, unexport those that were actu- ally passed from payloads/external/Makefile.inc and clear MAKEOVERRIDES. Do not pass OBJDUMP as that is nowhere to be found in the GRUB sources. And, last but not least, add --disable-werror because building GRUB is very susceptible to changes in the flex version. Change-Id: Iaff2c72e89a5a540fe365eacb84811d5cff9d4d4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-15device/smbus: Drop some never used boilerplateNico Huber
It was added with the words "Update the device header files" and we maintained it for nearly 13 years :) These functions are part of the SMBus spec but they are rarely used and keeping them just in case increases the maintenance burden. Change-Id: I69a1ea155a21463fc09b7b2c5b7302515a0030b2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-14stoneyridge: Fix CPU ASL \_PR tableMarc Jones
The PMIO region was moved, but not updated in the ASL. Change to generate \_PR table runtime and to report the correct PMIO region and length. Fix on Kahlee, where the EC overlaps the region: [ 0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0 [ 0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16 BUG=b:63902389 BRANCH=none TEST=Cros_ec_lps can reserve the region. ACPI tables are correct. Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20910 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-14i2c: Move to Linux like `struct i2c_msg`Nico Huber
Our current struct for I2C segments `i2c_seg` was close to being compa- tible to the Linux version `i2c_msg`, close to being compatible to SMBus and close to being readable (e.g. what was `chip` supposed to mean?) but turned out to be hard to fix. Instead of extending it in a backwards compatible way (and not touching current controller drivers), replace it with a Linux source compatible `struct i2c_msg` and patch all the drivers and users with Coccinelle. The new `struct i2c_msg` should ease porting drivers from Linux and help to write SMBus compatible controller drivers. Beside integer type changes, the field `read` is replaced with a generic field `flags` and `chip` is renamed to `slave`. Patched with Coccinelle using the clumsy spatch below and some manual changes: * Nested struct initializers and one field access skipped by Coccinelle. * Removed assumption in the code that I2C_M_RD is 1. * In `i2c.h`, changed all occurences of `chip` to `slave`. @@ @@ -struct i2c_seg +struct i2c_msg @@ identifier msg; expression e; @@ ( struct i2c_msg msg = { - .read = 0, + .flags = 0, }; | struct i2c_msg msg = { - .read = 1, + .flags = I2C_M_RD, }; | struct i2c_msg msg = { - .chip = e, + .slave = e, }; ) @@ struct i2c_msg msg; statement S1, S2; @@ ( -if (msg.read) +if (msg.flags & I2C_M_RD) S1 else S2 | -if (msg.read) +if (msg.flags & I2C_M_RD) S1 ) @@ struct i2c_msg *msg; statement S1, S2; @@ ( -if (msg->read) +if (msg->flags & I2C_M_RD) S1 else S2 | -if (msg->read) +if (msg->flags & I2C_M_RD) S1 ) @@ struct i2c_msg msg; expression e; @@ ( -msg.read = 0; +msg.flags = 0; | -msg.read = 1; +msg.flags = I2C_M_RD; | -msg.read = e; +msg.flags = e ? I2C_M_RD : 0; | -!!(msg.read) +(msg.flags & I2C_M_RD) | -(msg.read) +(msg.flags & I2C_M_RD) ) @@ struct i2c_msg *msg; expression e; @@ ( -msg->read = 0; +msg->flags = 0; | -msg->read = 1; +msg->flags = I2C_M_RD; | -msg->read = e; +msg->flags = e ? I2C_M_RD : 0; | -!!(msg->read) +(msg->flags & I2C_M_RD) | -(msg->read) +(msg->flags & I2C_M_RD) ) @@ struct i2c_msg msg; @@ -msg.chip +msg.slave @@ struct i2c_msg *msg; expression e; @@ -msg[e].chip +msg[e].slave @ slave disable ptr_to_array @ struct i2c_msg *msg; @@ -msg->chip +msg->slave Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-14libpayload: add *SECS_PER_SEC macros to stddef.hCaveh Jalali
this adds convenience definitions for MSECS_PER_SEC, USECS_PER_MSEC, and USECS_PER_SEC along the lines of the time units in coreboot's <timer.h>. Change-Id: I489dc2d1ff55d137936acec74ac875dc7fbc1713 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/20882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-14Makefile.inc: lint: Update to run lint-extended scriptsMartin Roth
- Add lint-extended as a valid option - Call lint-extend from what-jenkins-does and test-lint - When logging to a junit.xml file, name the file extended-junit.xml so it doesn't conflict with the stable junit.xml file. Change-Id: I7e4156844b8c60790e03a0e43564610bb0c8f386 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2017-08-14util/lint: add extended stable checkpatch for testingMartin Roth
The checkpatch script takes a while to run, so don't add it to the lint-stable checks which run pre-commit. Change-Id: I907176c21c057564495b75133ba10b0761c9fe7b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2017-08-14nb/intel/sandybridge/gma: Fix S3 resumePatrick Rudolph
The S3 resume path is broken on current Linux (4.11.3) and maybe on older kernel, too. Don't run the native graphics init when on S3 resume to fix it. Tested on Lenovo T430. Change-Id: Ifad145c86c2e8f019c507f97c889b70b7aa49882 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-14soc/intel/cannonlake: Remove unused systemagent registersSubrata Banik
This patch to make code cleaner and remove unused systemagent register macros. [same as KBL implementation] Change-Id: I13b9c83097fc98183ea138c9087b5fc7834efd58 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14soc/intel/cannonlake: Initialize struct member to 0Subrata Banik
As per GCC 7.1 compiler struct reset_reply is considered as uninitialized inside send_heci_reset_message function. Change-Id: I01b95d31bfb1d2e9af1704a28dacb9cfd1cdcb50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14common/block/lpss: Add CLK read function into LPSS commonSubrata Banik
This patch add new API to read LPSS CLK register. Also combine multiple LPSS_CLOCK_CTL_REG writes into a single write inside lpss_clk_update function. Change-Id: I420919ad9154c4cf426bc232c5eb59d95fd698d2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14stoneyridge: Rename hudson to southbridgeMarc Jones
Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-14console: Add weak method to notify about deathPatrick Rudolph
Call weak method die_notify. The method should be overwritten in mainboard directory to signal that a fatal error had occurred. On boards that do share the same EC and where the EC is capable of controlling LEDs or a buzzer the method can be overwritten in EC directory instead. Tested on Lenovo T500. Change-Id: I71f8ddfc96047e8a0d39f084588db1fe2f251612 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19696 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-11nb/intel/x4x/gma.c: Probe VGA EDID on DVI-I portsArthur Heymans
This allows the use of the native VGA init on boards featuring DVI-I ports. Digital output is not supported. Change-Id: I11a4dd68746e06c7e27ecf3e765bdd0d8cf40515 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-11driver/intel/gma: Allow use of GFX_GMA_ANALOG_I2C_HDMI_x in C NGIArthur Heymans
These Kconfig options can be reused for the same purpose of selecting the correct i2c pins for probing the analog output EDID in C native graphic init. For this purpose this patch makes those options independent of GFX_GMA and MAINBOARD_HAS_LIBGFXINIT. Change-Id: If29c541d414e12b95d96ae9c249a7a20e863fe06 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-11ec/google: update ec_commands.hPatrick Georgi
Copy from chrome-ec codebase, except for keeping the long-form license header. BUG=b:64468585 BRANCH=none TEST=with the other sku-id related patches applied, coreboot obtains the right SKU ID from EC Change-Id: I513123547f3854945e827d2f7f6c0df6591886eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20945 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-11mb/google/poppy: Update PL2 settingsSumeet Pawnikar
Update PL2 override setting to 15W as per KBL Power Arch Guide. Change-Id: I4a6f875f8c3bdb012d6ff97c1429f32db5210893 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/20943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-11util/cbmem, util/cbfstool: resolve macro errors on FreeBSDIdwer Vollering
Using sys/cdefs.h would come to mind, however this include would not solve the build error. Built and runtime tested on FreeBSD 12.0-CURRENT, r322031 Change-Id: I6ec9bc7fea72aa69a41439e002f381bd5e5b6bc6 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/20924 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-11drivers/intel/gma/opregion: migrate from nb/commonMatt DeVillier
Migrate opregion code from northbridge/intel/common to drivers/intel/gma in preparation for consolidation with soc/intel/common opregion code. Rename init_igd_opregion() for clarity and disambiguation with other implementations. Change-Id: I2d0bae98f04dbe7e896ca34e15f24d29b6aa2ed6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-08-11ec: add support for KBC1126 in HP laptopsIru Cai
- let the coreboot build system insert the two blobs to the coreboot image - EC and Super I/O initialization - ACPI support Tested on 2760p, 8460p, 2570p, 8470p. Issue: Kernel gives the following error: ACPI Error: No handler for Region [ECRM] (...) [EmbeddedControl] ACPI Error: Region EmbeddedControl (ID=3) has no handler TODO: - consider moving the Super I/O initialization code to ramstage, or reuse the existing sio/smsc/kbc1100 code (if so, how to add the additional kbc1126 specific functions to sio/kbc1100) - sort out the ACPI code which is mostly from the ACPI dump of vendor firmware - find out why the digitizer in hp/2760p doesn't work - GRUB payload freezing on all HP Elitebooks may be related to EC Change-Id: I6b16eb7e26303eda740f52d667dedb7cc04b4ef0 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/19072 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-11soc/cannonlake: Enable SMM code for Cannon LakeBrandon Breitenstein
The minimum needed defines are included here and pm.h will be updated when the PMC code for cannonlake is uploaded. Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-11Fine-tune compiler flagsStefan Reinauer
Per default, GCC enables -fdelete-null-pointer-checks, which is harmful and hence we should disable it: "Assume that programs cannot safely dereference null pointers, and that no code or data element resides there." We want to be careful with our stack usage, hence enable -fconserve-stack: "Attempt to minimize stack usage. The compiler will attempt to use less stack space, even if that makes the program slower." Change-Id: I74eac2b07c986553f79898a2f2e57bbead4223f8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-11soc/intel/cannonlake: Add missing _PCH_DEV definitionsFurquan Shaikh
Add all missing _PCH_DEV definitions to pci_devs.h Change-Id: I0f2eec5dff000738f41cfa6aec11b54a65f8adc3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-11payloads/external/tianocore: Add and apply patches for tianocoreEvelyn Huang
Create a directory patches, and add necessary patches to be applied to upstream tianocore. Patches include: -Patch for no PCI address enumeration -Patches to enable keyboard input -Patch to disable serial to speed up boot process. Patches pulled from https://github.com/MattDevo/edk2. Additionally, modify tianocore Makefile to apply patches during build. Change-Id: I4eaa602418995a68753b1ed13af8c6374eaa312f Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-11copy & update test routines from what-jenkins-doesMartin Roth
Currently the only testing we had was 'what-jenkins-does' and 'make lint'. While the lint testing is suitable for developers, the 'what-jenkins-does' target really isn't, as it was designed specifically for testing on jenkins. This adds the infrastructure for basic tests that are more suitable for the developer. Extended tests and improvements will follow. Add the coreboot-builds directories to .gitignore. TODO: - Save/restore .config - Update test-abuild to use existing COREBOOT_BUILD_DIR variable Change-Id: I19e1256d79531112ff84e47a307f55791533806f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@google.com>
2017-08-11Make: Move testing into a subdirectoryMartin Roth
In preparation for expanding the testing, move the test targets out of the top level Makefile.inc and into a separate subdirectory. Change-Id: Ie252c7555223f9ce76b54e6f7b66d03f3cf60500 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@google.com>
2017-08-10Documentation: Add binary extraction documentationLogan Carlson
Added documentation on how to extract binaries from a ROM image, including: - Using ifdtool to extract binaries. - Using cbfstool to extract binaries. - Changing menuconfig to use the extracted binaries. Change-Id: Ia31b01afc66789f95c7d21a0d41b532bc19a6430 Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/20753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-10libpayload/libpci: Add a constant for PCI class memory otherNico Huber
Change-Id: I71e902c4ec843608c1518fe1e8b90fbcf98a13d1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-10soc/intel/apollolake: Enable UART debug controller on S3 resumeFurquan Shaikh
1. Add a new variable to GNVS to store information during S3 suspend whether UART debug controller is enabled. 2. On resume, read stored GNVS variable to decide if UART debug port controller needs to be initialized. 3. Provide helper functions required by intel/common UARRT driver for enabling controller on S3 resume. BUG=b:64030366 Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20888 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-10soc/intel/skylake: Enable UART debug controller on S3 resumeFurquan Shaikh
1. Add a new variable to GNVS to store information during S3 suspend whether UART debug port controller is enabled. 2. On resume, read stored GNVS variable to decide if UART debug port controller needs to be initialized. 3. Provide helpers functions required by intel/common UART driver for enabling controller on S3 resume. BUG=b:64030366 TEST=Verified behavior with different combinations: 1. Serial console enabled in coreboot: No change in behavior. 2. Serial console enabled only in kernel: coreboot initializes debug controller on S3 resume. 3. Serial console not enabled in coreboot and kernel: coreboot skips initialization of debug controller on S3 resume. Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20886 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-10soc/intel/common/uart: Add support for enabling UART debug controller on resumeFurquan Shaikh
It has been observed on a number of platforms (baytrail, kaby lake) that if serial console is not enabled in coreboot, but is enabled in kernel (v4.4), then on resume kernel hangs. In order to fix this, add support for enabling UART debug port controller on resume. In order to decide whether UART debug port controller should be enabled in ramstage, following things are checked in given order: 1. If coreboot has serial console enabled, there is no need to re-initialize the controller. 2. This special action is taken only for UART debug port controller. 3. If boot is not S3 resume, then initialization is skipped. 4. Callback into SoC to check if it wants to initialize the controller. If all the above conditions are met, then UART debug port controller is initialized and taken out of reset. BUG=b:64030366 TEST=Verified with the entire patchset series that: 1. If coreboot does not have serial console enabled, but Linux kernel has console enabled, then on resume, coreboot initializes UART debug port controller. 2. If coreboot and Linux do not have serial console enabled, then coreboot does not initialize UART debug port controller. 3. If coreboot has serial console enabled, there is no change in behavior. Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20835 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-10soc/intel/common/lpss: Add lpss_is_controller_in_resetFurquan Shaikh
Add new API function lpss_is_controller_in_reset that returns whether the LPSS controller is in reset. Also, add lpss.c to smm stage so that lpss_is_controller_in_reset can be used in smihandler. BUG=b:64030366 Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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