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2012-05-28Enable USE_OPTION_TABLE for ThinkPad X60Motiejus Jakštys
Without this option bluetooth configuration value in nvram is not consulted properly. It also enables built-in volume control (read-only). Tested on: ThinkPad X60s, 1702. Change-Id: I2fc6bb527c6e086a083e63922d1253eda7d4a36d Signed-off-by: Motiejus Jakštys <desired.mta@gmail.com> Reviewed-on: http://review.coreboot.org/985 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-05-26Implement %zu / %zd in printkStefan Reinauer
The SPI drivers from u-boot make heavy use of %zu/%zd (size_t/ssize_t). Implement this in our printk implementation so we get useful output. Change-Id: I91798ff4f28b9c3cd4db204c7ec503596d247dcd Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1043 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-26Move subsystem IDs to devicetree.cbStefan Reinauer
A while back coreboot was changed to read the subsystem IDs from devicetree.cb to allow each onboard PCI device to have its own subsystem id. When we originally branched, this was not the case, and the sandybridge/ivybridge mainboards have not been updated yet. Also, drop the subsystem ID from Emerald Lake 2, since it's not a Google device. Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1042 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-26Reduce default verbosity of SPI flash driversStefan Reinauer
Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled. Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1045 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-26Fix printk types in SPI flash driversStefan Reinauer
- use %zu instead of %zd for size_t (%zd is for ssize_t) - use %x instead of %lx for u32 - break some long lines to avoid commit hook trouble Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1041 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-25Fix typo on Persimmon #if CONFIG_HAVE_ACPI_RESUMEMarc Jones
Stupid typo: APCI instead of ACPI in Persimmon. Change-Id: I6fd7f091cf1f5c4c0e1b57c21553dab93b545eab Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1054 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-05-25nvramtool: use C99 PRIx64 / PRId64 for uint64_t variablesStefan Reinauer
In printf/printk, using %lld or %ld for uint64_t will warn on either 64bit or 32bit machines. However, C99 defines PRIx64 / PRId64 to provide the right modifiers for printing uint64_t variables. Use them instead. Change-Id: I68df5d069a1e99d1a75885173ddfd7815197afea Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1053 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-25Fix size_t for certain versions of GCCStefan Reinauer
When compiling coreboot with the latest ChromeOS toolchain, GCC complains that some printk calls use %zu in connection with size_t types since it resolves the typedefs to long unsigned int. The problem is solved by using the GCC built-in __SIZE_TYPE__ if it exists and define __SIZE_TYPE__ to long unsigned int otherwise. Change-Id: I449c3d385b5633a05e57204704e981de6e017b86 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1040 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-24Add EM100 mode to Intel Firmware Descriptor toolStefan Reinauer
To avoid having two copies for every firmware descriptor (one for EM100 use and one for real SPI flash use), add an EM100 mode to ifdtool that allows to "dumb down" a fast image to the settings required for the EM100 to work. Change-Id: I0ed989f0a49316bc63d8627cb5d4bd988ae7a103 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1039 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-24chromeos: Fix compilation of coreboot-utils packageStefan Reinauer
The ChromeOS build system provides a set of CXXFLAGS, however those do not contain -DCOMPACT. This breaks the compilation of cbfstool in coreboot-utils. This fix overrides CXXFLAGS so that coreboot-utils compiles again. Change-Id: If9495bdd815fe2cdaeba5386afa953558742467b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1038 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-24Converted the FRAMEBUFFER_VESA_MODE to a choice.Steve Goodrich
Being a diligent soul, I changed the "enter a numeric value for the mode you want" option to a choice of common modes. New modes can be added quite easily. Change-Id: I8cf4572c2d36ced6549541ec173c0c02d8eaca4a Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com> Reviewed-on: http://review.coreboot.org/1036 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-24abuild: Disable abuild-level parallelism for nowPatrick Georgi
It still failed because make touches files it isn't supposed to touch. Change-Id: I5a6ceaa9d5da212c1e34b121cf39fa9d27964747 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1037 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-24cbtypes.h: Unify cbtypes.h used in AMD board's codeVikram Narayanan
Remove all the repeated sections of code in cbtypes.h and place it in a common location. Add include dir in vendor code's Makefile. Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/912 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-21Fix Persimmon build without S3.Marc Jones
In the heap function, only check for S3 check when it is built in with CONFIG_HAVE_ACPI_RESUME. Change-Id: I439275a4e1b7b446b499bcf90c925785a14b980d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1034 Tested-by: build bot (Jenkins) Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-15Fix fadt legacy free setting.Marc Jones
The fadt legacy free logic was backwards. Change-Id: Ieb21ef335f7514ced70248d0bf8668ddb73cf59f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1030 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-05-15Change the name of the romstage bootblock.ldMarc Jones
The bootblock.ld linkerscript is used by romstage. Name it accordingly to avoid confusion. Change-Id: I7ca9147bb821fe6f83224d170f5fe25654ef250f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1031 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-05-15Fix Cygwin bootblock generationMarc Jones
Cygwin is case insensitive, so bootblock.s and bootblock.S in the same directory cause a build failure. This changes bootblock.S to bootblock_inc.S, as it is generated from bootblock_inc. crt0.S and crt0.S also had this problem. This changes crt0.S to crt0.romstage.S. Change-Id: I29d230a93b0743e34f11228f9034880ceaf7ab7b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1032 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-05-15Pass IASL to SeaBIOSMarc Jones
Use the coreboot IASL for building SeaBIOS. Change-Id: Ia6c802b090d53b7fbbc8ddb6edad3de6b822ff41 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1033 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-05-14SPI driver: style fixPatrick Georgi
lint tests for labels to start at BOL, no spaces before them. Change-Id: Icf6ce533f26998a81b4be46d17e2d0b6b868904d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1029 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-14crossgcc: Test for m4 and bisonPatrick Georgi
Happened way too often that crossgcc failed because m4 or bison wasn't installed already. Change-Id: Ibcca2183edd5db20608015e3898f8fff9a6d11e8 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1026 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-14crossgcc: update sourcesPatrick Georgi
Update GNU project versions, download GNU project tarballs using ftpmirror.gnu.org (http, picking close servers). Update ACPICA tarballs, ignore https certificates for all downloads. Not very useful, but breaks ACPICA download. Change-Id: I4aa8b08836346d031793a006b20b741d86e48988 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1025 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Raymond Danks <ray.danks@se-eng.com>
2012-05-14abuild: Move configuration handling togetherPatrick Georgi
Handling user options was spread out across the code. Collect as much as possible in the getopt loop. Change-Id: I4979a14988da000c008e155023b960535b529b41 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1028 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-14abuild: Remove abuild.info hackPatrick Georgi
abuild used to allow boards to override certain environment variables using a file called abuild.info. This isn't used, this isn't needed. Drop it. Change-Id: Ic93748f602bf0c354ff1f3be25a050e1cb469256 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1027 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-12Add legacy free setting and override to fadt.cMarc Jones
The FADT iapc_boot_arch indicates the available information for accessing legacy devices. By default, the setting supports legacy. LEGACY_FREE and/or the iapc_boot_arch field may be customized. Change-Id: I5679741e1f8db923d3c00b57f6a5d813550f3a5e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1024 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-05-12Merge sb800 fadt fixes from South Station mainboard to southbridge fadt.Marc Jones
The South Station recieved updates that fix a number of fadt problems. South Station now uses the southbridge fadt. Change-Id: Ib990a69a359a4b7eae3431bb4323acd537acda1d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1021 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-05-11Hook up MRC cache updateStefan Reinauer
Requirements: - must be in ramstage (locking flash while executing code from there might not work) - must be after cbmem is reinitialized (so the mrc cache copy of the current run can be found) Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1002 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
- Separate Sandybridge from ChromeOS a bit The Sandybridge code depends on chromeos features a whole lot. As a first step, provide a code path to look up the MRC cache without depending on u-boot. - Move mrc cache handling to separate file This enables us to handle the MRC cache from ramstage, where we can write the flash safely (eg. to update the cache). Also teach it to lookup the current MRC cache from CBMEM, as the original data block isn't available anymore. After all the preparations, finally write to the SPI as necessary. It's a simple round robin wear levelling that erases the entire MRC cache region when it's full and starts from the beginning. Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1001 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-10Add SPI flash driverStefan Reinauer
This driver is taken from u-boot and adapted to match coreboot. It still contains some hacks and is ICH specific at places. Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/997 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-10abuild: Build boards in parallel if possiblePatrick Georgi
Determine if xargs -P works. If yes, use that to build multiple boards in parallel, instead of relying on make -j X, when doing a full abuild run (instead of single boards). make -j X isn't able to make use of several cores at various serialization points in our build process, so this change results in a >25% speed up for a full abuild run in my tests. Change-Id: Id484a4211c84a3a24115278e0fbe92345f346596 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/409 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-10CIMx: Allow #define LEGACY_FREE overridesMartin Roth
For legacy free AMD systems, the #define LEGACY_FREE cannot currently be overridden. This patch allows the platform_cfg.h to override that. (I know we want to get away from that, but for now...) Also allow BIOS_SIZE to be overridden on SB700 cimx based platforms. Change-Id: I570115248bcbc686062bfb66acb56208240b847a Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1018 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-10Unmark source files as executablesAlec Ari
Change source file modes from 755 to 644 The following files have been grepped for changes: *.c *.h *Kconfig* *Makefile* Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/1023 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-10Integrate MA785GM-US2H to KconfigAlec Ari
MA785GM-US2H was left out of Kconfig. This allows the option to select the board. Change-Id: I9efea96c21dcd0754ab51824b410435b0b5300c2 Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/1022 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-09Update SeaBIOS URLPatrick Georgi
We have a http accessible SeaBIOS mirror at review.coreboot.org. Use it. Change-Id: Icce8e4f9ca1fa69966c82423b2b27057f15b30d2 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1020 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-09Move fadt.c to the cimx sb800 southbridge directory to be shared.Marc Jones
The fadt.c is the same across all the platforms using the sb800 cimx southbridge wrapper. Change-Id: Ifbbfc238732aa46aef96297eaa188b77d27151f3 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1019 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-09Add simple PMIO & PMIO2 read/write routines to CIMX wrapperMartin Roth
These are the PMIO & PMIO2 read & write routines from src/southbridge/amd/sb800/sb800.c & sb800.h for use in the cimx tree. Currently most platforms using CIMX are calling WritePMIO() directly from the src/vendorcode/amd/cimx/sbX00 directories instead of using a wrapper function. These functions only do byte reads & writes. Change-Id: I881a6e2d4ddbba3dbdf4dd33e06313fe88b3682a Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/981 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-08Don't loop infinitely long on serial comm failuresStefan Reinauer
If serial uart (8250/16x50) takes abnormally long to respond, give up on logging to serial console and instead let the system boot. Also reference bit in LSR register with correct name. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Ported from 9dd3ef165a1bf1bc404056d3e54337de1a15ac90 to uart8250mem.c: Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Iaca4f57389c887110e6406d45053935891c96838 Reviewed-on: http://review.coreboot.org/826 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2012-05-08Add a tool to work on i915 hardware in user modeStefan Reinauer
This is the beginning of a tool that transforms the i9x5 code to user mode code. Consider this a very early stage although it does produce two programs. Requires spatch 1.0 or greater. To try it out, assuming you have an up-to-date spatch, sh transform make make broken Please don't fall to the temptation to auto-magicize this process. It's primitive for a reason. That said, suggestions welcome of course. Change-Id: I0188e36637b198b06c17f6d3c714d990e88bd57d Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1003 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-08Fix build with CMOS support on various platformsPatrick Georgi
When bringing in nvramtool as build_opt_tbl replacement, various platforms where left in the cold that don't provide direct IO support from userland (or at least not in a way we support). Build nvramtool without CMOS support when done as part of a coreboot build. We don't need to touch CMOS in this case. Change-Id: Icc88d1d32f10384867a5d44b065f9aa119bb0d50 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/983 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-08Some more #if cleanupPatrick Georgi
Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} + (manual tweak since it hit a false positive) Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} + Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1006 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-08Add config_enabled() from LinuxPatrick Georgi
This change is taken from Linux. It allows to check for Kconfig definitions in the preprocessor and source code using the same idiom. Long term plan is to remove our Kconfig hack to #define values to 0, and this helps. This includes a tiny modification to the macros to fix romcc support. Change-Id: I0fddbea8c8ca215cf226acf39cb329b0ba0445a5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1005 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-04Make CBFS output more consistentStefan Reinauer
- Prefix all CBFS output messages with CBFS: - Add an option DEBUG_CBFS that is off by default. Without DEBUG_CBFS enabled, the code will no longer print all the files it walks for every file lookup. - Add DEBUG() macro next to LOG() and ERROR() to specify which messages should only be visible with DEBUG_CBFS printed. - Actually print a message when the file we're looking for was found. :) old: Searching for fallback/coreboot_ram Check cmos_layout.bin Check pci8086,0106.rom Check fallback/romstage Check fallback/coreboot_ram Change-Id: I2d731fae17a5f6ca51d435cfb7a58d6e017efa24 Stage: loading fallback/coreboot_ram @ 0x100000 (540672 bytes), entry @ 0x100000 Stage: done loading. new: CBFS: Looking for 'fallback/coreboot_ram' CBFS: found. CBFS: loading stage fallback/coreboot_ram @ 0x100000 (507904 bytes), entry @ 0x100000 CBFS: stage loaded. Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/993 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-04siemens/sitemp_g1p1: Drop debug codePatrick Georgi
Change-Id: I40a4201b468131ba67e48ab68d62ca5413f2e2e8 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-04roda/rk886ex: Expose VGA devices in devicetreePatrick Georgi
Otherwise set_subsystem isn't called for these (as they're not marked on_mainboard) Change-Id: I08e781735c59e4aa61009d2afa165d782f5a849e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-04lint: Avoid downloading blobs repositoryPatrick Georgi
The stable lint test "build-dir-handling" ran the build system in a way that made it download the blobs repository. Since this is part of the pre-commit hook, this might have kicked in with users desiring not to have them. Change-Id: I44a00137352c5966ff7fe2a030673276f6803908 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/999 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Don't pre-enable SATA AHCI in romstage.cStefan Reinauer
In a recent commit the SATA code of Panther Point / Cougar Point was changed to enable AHCI mode depending on the device tree settings rather than a hard code hidden in romstage.c. However, Emerald Lake 2 was not fixed up accordingly. Change-Id: I6c93f386509361e1ab5565b0e4d0e84f0ba282a2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/995 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Print some useful debugging information in PSS table creationStefan Reinauer
Change-Id: I1ec7a7e54513671331ac12f08d5f59161b72b0fd Example: PSS: 1900MHz power 35000 control 0x1300 status 0x1300 PSS: 1600MHz power 28468 control 0x1000 status 0x1000 PSS: 1400MHz power 24291 control 0xe00 status 0xe00 PSS: 1200MHz power 20340 control 0xc00 status 0xc00 PSS: 1000MHz power 16569 control 0xa00 status 0xa00 PSS: 800MHz power 12937 control 0x800 status 0x800 PSS: 1900MHz power 35000 control 0x1300 status 0x1300 PSS: 1600MHz power 28468 control 0x1000 status 0x1000 PSS: 1400MHz power 24291 control 0xe00 status 0xe00 PSS: 1200MHz power 20340 control 0xc00 status 0xc00 PSS: 1000MHz power 16569 control 0xa00 status 0xa00 PSS: 800MHz power 12937 control 0x800 status 0x800 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/994 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Make creation of CBMEM_ID_RESUME_SCRATCH depending on AgesaStefan Reinauer
The CBMEM_ID_RESUME_SCRATCH area is only used by Agesa code, on one particular board (AMD Persimmon). Make the creation of that section depending on Agesa so it does consume space on non-Agesa systems. Change-Id: I2a1a4f76991ef936ea68cf75928b20b7ed132b84 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/992 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Add missing newline to printk in Sandybridge init codeStefan Reinauer
Change-Id: I9217a75ec1a0abb898c45752d990231ce98e5fb2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/991 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Tell CBMEM pretty printer about MRC cacheStefan Reinauer
Sandybridge memory initialization produces some amount of training data that has to be kept around in CBMEM. Add a descriptive name to the CBMEM pretty printer to prevent it from just printing the hex value. Change-Id: I587c0bc3dfcf389ba298d445d2594eef73bc69a8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/990 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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