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2012-03-29Refactor publishing CBMEM addresses through coreboot table.Vadim Bendebury
We need to provide u-boot access to several different CBMEM sections. To do that, a common coreboot table structure is used, just different tags match different coreboot table sections. Also, the code is added to export CBMEM console and MRC cache addresses through the same mechanism. Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/724 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29Add timestamp table pointer to the coreboot table.Vadim Bendebury
This change exports the timestamp table pointer through coreboot table to make it possible for u-boot to add timestamps to the table. Inclusion of cbmem.h allows to drop external declarations in coreboot_table.c. Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/716 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29Introduce utility for parsing CBMEM contents.Vadim Bendebury
This is a python script which is supposed to run on a target which is controlled by coreboot. The script examines top of memory looking for the CBMEM signature at addresses aligned at 128K boundary. Once the script finds the CBMEM, it iterates through the CBMEM table of contents and parses two entries: the timestamps and the console log. This submission is just a template to build upon to create a utility for displaying CBMEM information while running Linux on the target. BUG=chrome-os-partner:4200 TEST=manual See test description of d81e6b8c8d41f2d6 for test procedure. Change-Id: Id863a8598eaadc2d20d728f9186843e65cbe6f37 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5942 Tested-by: Vadim Bendebury <vbendeb@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/723 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29CBMEM CONSOLE: Enable coreboot CBMEM console.Vadim Bendebury
The appropriate Makefiles are modified to include the required source code in compilation. Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/722 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29CBMEM CONSOLE: Add code using the new console driver.Vadim Bendebury
The new added code is compiled in when the CBMEM_CONSOLE config flag is enabled. Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/721 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29CBMEM CONSOLE: Add CBMEM type for console buffer.Vadim Bendebury
Add CBMEM type for the console buffer section. Change-Id: I02757c06d71e46af77b02b90b0e6018a37b62406 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/720 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29CBMEM CONSOLE: Add CBMEM console driver implementation.Vadim Bendebury
The CBMEM console driver saves console output in a CBMEM area, which then is made available to Linux applications for perusing. There are some system limitations which need to be worked around to achieve this goal: - some console traffic is generated before DRAM is initialized, leave alone CBMEM initialized. - after the RAM based stage starts, a lot of traffic is generated before CBMEM is initialized. As a result, the console log lives in three different places - the bottom of the cache as RAM space, the CBMEM buffer (where it is expected to be) and a static buffer used early in the RAM stage. When execution starts (in the cache as RAM mode), the console buffer is allocated at the bottom of the cache as RAM memory address range. Once DRAM is initialized, the CBMEM structure is initialized, and then the console buffer contents are copied from the bottom of the cache as RAM space into the CBMEM area right before the cache as RAM mode is disabled. The src/lib/cbmem_console.c:cbmemc_reinit() takes care of the copying. At this point the cache as RAM memory is about to be disabled, but the ROM stage is still going generating console output. To make sure this output is not lost, cbmemc_reinit() saves the new buffer address at a fixed location (0x600 was chosen for this), and the actual "printing" function checks to see if the RAM is already initialized (the stack is in RAM), and if so, gets the console buffer pointer from this location instead of using the cache as RAM address. When the RAM stage starts, a static buffer is used to store the console output, as the CBMEM buffer location is not known. Then, when CBMEM is reinitialized, cbmemc_reinit() again takes care of the copying. In case the allocated buffers are not large enough, the excessive data is dropped, and the copying routine adds some text to the output buffer to indicate that there has been data lost and how many characters were dropped. Change-Id: I8c126e31db6cb2141f7f4f97c5047f39a8db44fc Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/719 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29CBMEM CONSOLE: Add config option for CBMEM stored console log.Vadim Bendebury
Some experiments have demonstrated that total amount of text generated by coreboot console when BIOS_SPEW level is enabled exceeds 40KB. Console output generated before DRAM is initialized can exceed 2KB. This patch introduces the new configuration option and assigns adequate default values to cache based and DRAM based console buffers. BUG=chrome-os-partner:4200 TEST=manual . run the following commands in the root directory cp config.stumpy .config make menuconfig . enable the new option (Console->Send console output to a CBMEM buffer) . save the configuration Observe the following settings added to the config: +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5855 Tested-by: Vadim Bendebury <vbendeb@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/718 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29Increase CBMEM to accommodate larger console.Vadim Bendebury
This change adds 128K to the memory amount set aside for CBMEM in case the CBMEM console is enabled (to keep the CBMEM 128K byte aligned). The console buffer size is being set to 64K, which is enough to accommodate the most verbose coreboot console and u-boot console. Change-Id: If583013dfb210de5028d69577675095c6fe2f3ab Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/725 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-28Add cmos helper functions for reading/writing a dwordDuncan Laurie
These get used later for saving/restoring the MRC scrambler seed values on each boot. Change-Id: I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/717 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-28selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MBStefan Reinauer
This fixes loading SeaBIOS when lower memory is reserved. Change-Id: Idbdcaf95f3307f97307f304d6d677406d059927d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/732 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-28Include arch/acpi.h instead of manually adding acpi_slp_type.Stefan Reinauer
acpi_slp_type is defined in arch/acpi.h, so let's use that instead of manually spreading extern u8 acpi_slp_type throughout the code. Change-Id: Ia5eb420364c15ab5a764bc328bbd201ca9cb7837 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/714 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-28Add timestamp collecting to coreboot.Vadim Bendebury
This patch adds code to initialize the time stamp collection facility in coreboot. It adds a table in the CBMEM section, which provides the base timer reading value (all other readings are offsets of this one) and an array of timestamp id/timestamp value pairs. Just two values are being added now, this will have to be used more extensively and also integrated into payloads to provide more comprehensive boot process time measurements. Also, since the CBMEM area could already contain a section (from the previous run, before reset), when processing a section addition request we should check if a section already exists and return its address, if so. Change-Id: I7ed9f5c400bc5432f228348b41fd19a67c36d533 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/713 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-28Add a config flag to enable time stamp collectionVadim Bendebury
Add a new flag, make it dependent on EARLY_CBMEM_INIT Change-Id: Idbebcaf298238f31a73e9eb4a9af7b03e857bc74 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/712 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-28Initialize CBMEM early.Vadim Bendebury
We want to be able to share data between different phases of firmware (rom stage/ram stage/payload). Coreboot CBMEM seems an appropriate location for this data, but normally it is not initialized until coreboot reaches the ram stage. This change initializes the CBMEM while still in rom stage in case CONFIG_EARLY_CBMEM_INIT is set. Note that there is a discrepancy in how coreboot determines the size of DRAM at rom and ram stages, get_top_of_ram() is used at rom stage and is not defined for all platforms. Those platforms will have to define this function should they enable the CONFIG_EARLY_CBMEM_INIT flag. Change-Id: I81691d45e28de59496fb227f2cca4e8c15ece717 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/711 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-28Introduce config option to initialize CBMEM early.Vadim Bendebury
We want to be able to communicate information between rom and ram stages of coreboot. This configuration option will be used to compile such ability in. Change-Id: I6736fdc264ecd0b63369b28462d7bb96e4c2b012 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/710 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-27Add bifferboardRudolf Marek
This commit adds support for Bifferboard, a 32MB 486 PC Change-Id: Iad790ebf242ef07bf6298f8e3577783e5e743113 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/810 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-27Add 64KB romchip chip sizeRudolf Marek
This is handy for bifferboard to provide same size as original bootloader. Change-Id: I179917d8c6354fa55cebdd70918a96cd299c4f3c Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/809 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-27Add support for RDC R8610 SouthbridgeRudolf Marek
So far it just setups things right for Bifferboard. We may change it in the future to fit other hardware. Change-Id: I1c4ccff4e47b9cb9e31a738f038fc4f4ebe59087 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/808 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-27Add the support for RDC R8610 NorthbridgeRudolf Marek
So far the it just setups the internal resource management for coreboot and detects the memory size. Change-Id: I8506390fa6656abfa40d92b8f6ede9b91fe98680 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/807 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-27Add RDC R8610 PCI IDs.Rudolf Marek
Change-Id: I3f3585f15265aa1377f72ba23accf1adb08cb8ac Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/806 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-26Fix cleaning SeaBIOS from coreboot makefileMarc Jones
The coreboot makefile didn't pass the OUT and CC variables to seabios, so the clean didn't clean anything. Change-Id: Ieaf0c417d6e5dfb9e0a11df70b03d6313919578b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/801 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-26Disable the GDB stub by defaultRudolf Marek
I would prefer to see the exception dump on serial rather than cryptic GDB protocol. Change-Id: Ib25513d33e6a31da24586fecb00adb5206bb43bd Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/811 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-03-25Fix possible deadlock on SMP stop_this_cpuKyösti Mälkki
Do not use printk on the running thread after it has been sent the INIT IPI, execution may halt with console spinlock held. Change-Id: I64608935ea740fb827fa0307442f3fb102de7a08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/776 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-25Intel cpus: Fix deadlock on hyper-threading initKyösti Mälkki
Only the BSP CPU was able to start its hyper-threading CPU siblings. When an AP CPU attempts this it calls start_cpu() within start_cpu(), deadlocking the system with start_cpu_lock. At the time intel_sibling_init() is run, the BSP CPU is still walking the cpu_bus linked list in lapic_cpu_init: start_other_cpus(). A sibling CPU appended at the end of this list will get started. Also fail compile with #error if SERIAL_CPU_INIT==0, as microcode updates on hyper-threading sibling CPUs must be serialized. Tested with HT-enabled P4 Xeons on dual-socket604 platform. Change-Id: I0053f58f49ed604605ce0a55e826d3e1afdc90b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/775 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-25Makefile: rename linker intermediate variableKyösti Mälkki
Renamed CONFIG_ROMBASE to ROMSTAGE_BASE and removed it from Kconfig. Removed no-op calculation in ldscript. Change-Id: I53d39b60f07db76c8537b3133e59360687b9d4a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/802 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-25gitconfig: Improve commit-msg hookPatrick Georgi
There was some corner case where commit-msg failed. Update to latest upstream version. Change-Id: I822d6c3f64728de7356401465e00575ac5af8196 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/798 Tested-by: build bot (Jenkins) Reviewed-by: Bernhard Urban <lewurm@gmail.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-25Replace ramtest pattern to assist in DIMM configurationKyösti Mälkki
This is developer's testtool. Output from a "rotate ones" -style pattern helps figure out how DIMM addresses are encoded or routed on a certain mainboard. Scattered test should cover every data and address lines on the memory bus, but is probably limited to the first bank of first DIMM. Change-Id: I533a7a873bcc434f99e7faed9dc9337d9ab64196 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> [pg: rebase] Reviewed-on: http://review.coreboot.org/294 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-24i82801gx: Support power-on-after-power-fail betterPatrick Georgi
Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/444 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-24i82801gx: Use CMOS variable if available for power-on on power failurePatrick Georgi
We used a hard coded value for some reason. Don't do that, but use CMOS instead. Change-Id: Ib83aa07a3e55bed075150354a060317ebc9d5ba7 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/443 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-24printf: Remove some L modifier usesPatrick Georgi
We use the L modifier in a non-standard way (for long long instead of long double, which we have no business with). clang complains, to reduce its use, to make emulation/qemu-x86 happier. Long term, we should consider eliminating public uses of 'L' (but internal use in vtxprintf to denote long long is fine) Change-Id: If9a17d9ae9925cdc8736445e7d5eedc59c7028c6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/781 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-21Fix libpayload alloc() size and gcc pointer optimization problems.Marc Jones
The previous commit was incomplete and missed setting the entire alloc area. There are also additional problems with gcc optimizations of the pointer math. The "auto" casting by gcc wouldn't return warnings, but it was causing the optimization to be incorrect. We are now very explicit in the casting in the pointer math. Change-Id: I020808c8d1dda544fe862b9efb0e5345eeab5aab Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/804 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-20Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 ↵Rudolf Marek
class cpu. Change-Id: Ic7c4452a1b55bae0cefee118003540ec39ef9fd4 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/683 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-17Another indirection for normal/fallback bootblockPatrick Georgi
Provide a way to redefine the names of normal and fallback via CBFS. This way updates can use some more expressive naming scheme (numbers, dates, version numbers) and replace the coreboot-stages file to point to the new version (with the current version as new "old"). If coreboot-stages doesn't exist, the default behaviour remains to use "normal" and "fallback". Change-Id: I77c134d79ed95831ad5098b7663c15e95d3b5a2a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/589 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-17Intel cpus: Include CAR from socketKyösti Mälkki
It was not obvious which CAR was compiled in. Also build would fail if a socket included two models with both having an include for CAR. Change-Id: I000c2e24807c3d99347a43d120333c13fbf91af4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Fix AMD Fam15 CBMEM allocationStefan Reinauer
The Fam15 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: I8a00e05884bdb1d1a4a012433b0adfbb9eb22983 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/796 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16Fix AMD Fam12 CBMEM allocationStefan Reinauer
The Fam12 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: I1eca18e21fa59ae32e802d8452e42e8b7a3575cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/795 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16Fix AMD Fam10 CBMEM allocationStefan Reinauer
The Fam10 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: Id6c4128d8f5f6a417f83daa3a39b2bfc8e810f8a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/794 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16AMD Agesa: delete no-op bootblock filesKyösti Mälkki
Removes files: src/northbridge/amd/agesa/family10/bootblock.c src/northbridge/amd/agesa/family12/bootblock.c src/northbridge/amd/agesa/family14/bootblock.c src/northbridge/amd/agesa/family15/bootblock.c Change-Id: Ic3617a673b38d065ca272c4de8ef765ecd3f98b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/793 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki
Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove the explicit selects from the mainboards. Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/792 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Fix AMD Agesa leaking KconfigKyösti Mälkki
Kconfig leaked XIP_ROM_SIZE to other platforms and also defined obsolete option XIP_ROM_BASE. Alias AMD_AGESA as NORTHBRIDGE_AMD_AGESA. Break the circular dependency with family15 Kconfig. Change-Id: Ic7891012220e1bef758a5a39002b66971d5206e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/773 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16ROMCC boards have no XIP limitPatrick Georgi
So set their XIP configuration to ROM_SIZE. Change-Id: I6c1abccec3b1d7389c85df55343ff0fc68a61eec Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/797 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2012-03-16Use search path when building dependenciesPatrick Georgi
clang is more picky on that. Change-Id: Iaa8472beb6e275c39037d11e1a72dbb80d46424b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/779 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-16xchg is atomic with side-effectsPatrick Georgi
clang doesn't know about the side effect, so we have to tell it that it's okay not to care about the result. Change-Id: Ib11890bff6779e36cf09c178d224695ea16a8ae8 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-16clang: Don't use mmx nor ssePatrick Georgi
clang is much more trigger happy than gcc on those. Change-Id: Ie7c219de3cc26675692eab7361a4ad551f1c65a7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/786 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-16Intel northbridge I945: Apply un-written naming rulesKyösti Mälkki
Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build. Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time which model of I945 the driver is built for. Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/684 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Via Epia-N and C3: Set ioapic delivery type in KconfigPatrick Georgi
The original comment says it's a Via C3 and not Epia requirement to deliver IOAPIC interrupts on APIC serial bus. Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/435 Tested-by: build bot (Jenkins)
2012-03-16VIA southbridge K8T890: Apply un-written naming rulesKyösti Mälkki
Use separate Kconfig option to select a driver directory for build and the specific type of southbridge to support. Change-Id: I9482d4ea0f0234b9b7ff38144e45022ab95cf3f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/685 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Fix address of IDT in real-mode entryKyösti Mälkki
In a case of CS & 0x0fff != 0x0, lidt memory operand does not point to nullidt, this can raise an exception and shutdown the CPU. When an AP CPU receives 8-bit Start-Up IPI vector yzH, it starts execute at physical address 000yz000H. Seems this translates to either yz00:0000 or y000:z000 (CS:IP), depending of the CPU model. With the change entry16.inc is relocatable as the commentary suggests and can be used as ap_sipi_vector on SMP systems. Change-Id: I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/707 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Fix AMD Fam14 cbmen allocationMarc Jones
The Fam14 northbridge.c had hardcoded the cbmem size. It should use in cbmem.h instead. Change-Id: I910329fc98a4cf04dc81ef66f3aa05a1916f5b1d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/790 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 20:43:53 +0000