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2012-07-14AGESA F15 wrapper for Hudson.zbao
Hudson code has been integrated from CIMx to AGESA. This patch is about the wrapper. Change-Id: I63d951982140b82a3a77a97eb3d55fc75fc0caa3 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1157 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-14Remove useless file from building.zbao
Change-Id: I09c695347c04d7db9add2cbb687d59c829175cfc Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1224 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13sconfig: fix up shipped codePatrick Georgi
The lex compile wasn't current (or something) and so INTA wasn't lexed properly. Change-Id: I5a760430788792f54c4e1e0d419b8dd525079d15 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1226 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-13Add preliminary support for Bachmann electronic OT200Christian Gmeiner
Linux boots fine :) Change-Id: Ifda06e5220666534b87f528deae16d8b956c32b3 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13msrtool: add support for cs5536 LPC_SERIRQ (0x5140004e)Christian Gmeiner
This register is helpful for porting new mainboards based on cs5536 southbridge. Change-Id: Iff3adc2c2fbc672c8541096756f95b3322f6ab19 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1211 Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13MPTAPLE: generate from devicetree.cbSven Schnelle
This patch adds support for autogenerating the MPTABLE from devicetree.cb. This is done by a write_smp_table() declared weak in mpspec.c. If the mainboard doesn't provide it's own function, this generic implementation is called. Syntax in devicetree.cb: ioapic_irq <APICID> <INTA|INTB|INTC|INTD> <INTPIN> The ioapic_irq directive can be used in pci and pci_domain devices. If there's no directive, the autogen code traverses the tree back to the pci_domain and stops at the first device which such a directive, and use that information to generate the entry according to PCI IRQ routing rules. Change-Id: I4df5b198e8430f939d477c14c798414e398a2027 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1138 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13IOAPIC: hook up driver in KconfigSven Schnelle
Missed to add the driver to Kconfig and Makefile.inc. Change-Id: I64b02abc5de2f6483f610436ebb38a7ca433f9b6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1219 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12Drop Kconfig VAR_MTRR_HOLE optionKyösti Mälkki
All but one board use the default value of enabled. Disabling this can only increase the number of MTRR registers used. Change-Id: I7d28adc31b9fae2301e4ff78fcb96486f81d5ec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1213 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-12libpayload: Add reset function for OHCI USB driverAnton Kochkov
Implemented OHCI reset function ohci_reset() in ohci.c for libpayload's USB driver. Change-Id: Id6518cbe00a21202757b34926bad171909740e97 Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1177 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-12Lenovo X60: correct SDHCI write protect polarityJonathan A. Kollasch
Change-Id: I916deffe2c692042f7e54c936902e77770ee69df Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/1205 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-12superiotool: Dump data registers for Nuvoton chipsGuenter Roeck
Add support to dump all data registers for Nuvoton chips (NCT6775F, NCT6776F, and NCT6779D). Register contents will be dumped if the -e option is provided on the command line. Change-Id: I2b425b48c1f28a10ff3c1ca1d7f21c501eff74ad Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-on: http://review.coreboot.org/1150 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12superiotool: Add support for function to dump superio chip data registersGuenter Roeck
Add new function dump_data() to dump a bank of superio data registers. Change-Id: I13a58d87c14d319cfcdea1ec1d54c2b110d90f9f Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-on: http://review.coreboot.org/1149 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12superiotool: Add support for NCT6775F(A/B) and NCT6779DGuenter Roeck
Change-Id: I66667fcb58f6885460021f4a2024d6ba56b95f11 Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-on: http://review.coreboot.org/1148 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12Fix stack assignment during CPU initializationSven Schnelle
There are two errors in the code. The first one is a missing $ sign in mov _stack, %esp. Thanks to Ronald G Minnich for catching that bug. The second bug is the 'incl %eax', which shouldn't be there, as there's no secondary CPU with index 0. CPU0 uses always the stack below _estack. Change-Id: Id267a654ba95b0e898eeaaafb2403b438250a563 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1212 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2012-07-10Fix APIC cpu_indexKyösti Mälkki
If a CPU was pre-allocated, cpu_path is not copied and thus index would not be updated. This breaks cpu_index() and AMD model_fxx is possibly broken without this patch. Change-Id: I77483181cf0bca31423c655942c022bffab3c7ea Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1199 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-10Use dev_lock for alloc_find_dev()Kyösti Mälkki
If threads called alloc_find_dev() with same device_path simultaneously, two device nodes could be allocated. This bug is not triggered by current code. Change-Id: Ifc87021c8d6f422901c5de5dd17392e3e2309afa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1188 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-10Drop start_cpu_lockKyösti Mälkki
Function alloc_find_dev() is serialized. Change-Id: I40d27d1adca629f1f7ce2f09c1cb2fd04b76eb9a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1198 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-10msrtool: Add Intel Nehalem CPUs supportAnton Kochkov
Added Intel processors based on Nehalem architecture support, with decoding MSRs. Change-Id: I576d5eac2542c0b62852bf05e42bc98b134c7eae Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1170 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-10msrtool: Fix Intel CPUs detectionAnton Kochkov
Added vendor check in sys.c file and fixed models checking in intel targets files. Change-Id: I1ce52bbce431dea79e903d6bc7a12e5b9ad061be Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1169 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-09mkelfimage: pkgdata directory created but never usedRaymond Danks
Remove superfluous pkg* definitions and installation of a target directory directory that is never used. Change-Id: I2addf3f316230cdd428def5889fd3beb7c40f422 Signed-off-by: Raymond Danks <ray.danks@se-eng.com> Reviewed-on: http://review.coreboot.org/1195 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-09servengines/pilot superio: add attribute unusedSven Schnelle
Not all users use both functions, so add __attribute__((unused)) to prevent compiler errors. Change-Id: I8485bb9150b04d1f9fdc231152a43bcd6fc713a7 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1193 Tested-by: build bot (Jenkins)
2012-07-09SMBIOS: Add Type 38 (IPMI) data structureSven Schnelle
Change-Id: I9b9a1c7b1cc4aaba7a4791f898653b6fe41d4fcb Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1192 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-07-09i5000: reset system if raminit failsSven Schnelle
Don't stop if RAM init fails at first try. It's better to restart and try again instead of failing on the first try if the second try would have worked. Change-Id: Ib5660265d5b10a01588f2e4022dac2ee34f2c6d0 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1191 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-07-09Add basic ipmi supportSven Schnelle
Implements support code for talking to IPMI hardware that uses a KCS style interface. Change-Id: I9895cc1bf29676115b167081b63b8a430e23eee5 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1190 Tested-by: build bot (Jenkins)
2012-07-07IEI PM-LX-800-R11: Removed bogus Kconfig optionRicardo Martins
The Kconfig file for this board contains a bogus option called CORE_GLIU, this change removes it. Change-Id: I4ea069bdd76be53085ebc9c0fb3dd71ffb2a12e1 Signed-off-by: Ricardo Martins <rasmartins@gmail.com> Reviewed-on: http://review.coreboot.org/1179 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-07-06inteltool: fixup intel 5000 chipset pci idsSven Schnelle
Change-Id: I2cd1dac0dd9a5da1000a3ffa3e1c8ee4c5c8ba43 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1175 Tested-by: build bot (Jenkins)
2012-07-06i5000: Add PCI ids for all i5000 flavoursSven Schnelle
Change-Id: I48be647e3f38038830200bcc64429cbf86990ad7 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1174 Tested-by: build bot (Jenkins)
2012-07-06IEI PM-LX-800-R11: Added preliminary mainboard supportRicardo Martins
Details for this board are available at http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=08142307826854456110 Most of the functionality provided by the original BIOS is implemented. Change-Id: Id9eb10a2f9e49377ea587bddadbba7d76223a715 Signed-off-by: Ricardo Martins <rasmartins@gmail.com> Reviewed-on: http://review.coreboot.org/1168 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-06i945: Reset IGD on bootPatrick Georgi
This is mostly necessary for reboot, but it doesn't hurt the boot process. On reboot explicitely reset the integrated graphics, otherwise the VGABIOS might not be able to reinitialize it properly, and you either have a still of the last pre-reboot image, garbage or an empty screen, but no text-mode. Change-Id: Ic3d6932fbaf720d88daaac7e4b09c3c0b9f0b0e2 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1178 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-06superiotool: Add support for git-based version numberGuenter Roeck
The superiotool Makefile extracts a version string from SVN. This does not work with a git repository, and results in an empty version string. Use the output of 'git describe' as version string instead. Change-Id: Idf92c02753b28ef5bcdd3b6df4a08d79ae974434 Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-on: http://review.coreboot.org/1151 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-05PCI Type2 config must dieRonald G. Minnich
PCI Type 2 config was a strange and never-used config mechanism. It is unlikely that in the 13 years of coreboot's existence that type 2 was ever used; it just made life complicated for everyone. It lived long enough in coreboot to be replaced by mmioconf. Prior to making the device tree visible in romstage we want to get rid of type2. Delete two files we don't need any more (yay!). Replace two functions with one: pci_config_default, which returns a pointer to the default config method. At some future time this may change to mmio but for now it is old type1 style. Change-Id: Icc4ccf379a89bfca8be43f305b68ab45d88bf0ab Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1159 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-05Only copy real-mode section of SIPI vectorKyösti Mälkki
The SIPI vector copy can use a static location below 1MB, aligned to 4kB. Jump out of the copy once in protected mode. Change-Id: I6299aa3448270663941cf2c4113efee74bcc7993 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1165 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-05Fix the CPU index parameter passed to secondary_cpu_init().Kyösti Mälkki
Count 0,1,2,3,... instead of 0,2,3,4,... Change-Id: I3c6b85e5e71b32deac5470809e1618d28f19c00f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1173 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Intel cpus: Extend cache to cover complete Flash DeviceKyösti Mälkki
CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup would not cover the bottom 4 MB when ramstage is decompressed. Verify CACHE_ROM_SIZE is power of two. One may set CACHE_ROM_SIZE==0 to disable this cache. Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1146 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Intel model_106cx: change CAR to model_6exKyösti Mälkki
Diff between model_106cx and model_6ex CAR codes suggests currently used model_106cx CAR is not optimal - destination RAM and source ROM of ramstage copy_and_run are only partly set cacheable. It appears variable MTRR setting for XIP cache is left enabled on model_106cx code, where it should have extended to cover all of Flash. Introduces untested functional change on boards: intel/d945gclf iwave/iWRainbowG6 Deletes file: model_106cx/cache_as_ram.inc Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/642 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Intel cpus: delete dead CAR code and whitespace fixesKyösti Mälkki
A diff from model_6fx to model_106cx suggests there is little CORE2 specific code that was once considered useful to have. In its current status however, sockets supporting model_6fx use model_6ex CAR init, so that specific code is actually never used. Deletes file: model_6fx/cache_as_ram.inc Change-Id: I6c0204446fa98207e31f91895e1cf30fde42382c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/640 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Add generic IOAPIC driverSven Schnelle
Used for automatic generation of IOAPIC interrupt entries. Change-Id: Ia746f01906c840800956ce551306f864e440b6ec Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1137 Tested-by: build bot (Jenkins)
2012-07-04Intel cpus: use CPU_ADDR_BITS from Kconfig during CARKyösti Mälkki
Default CPU_ADDR_BITS is 36. For Atom (model_106cx) use 32. This model is known to fail execution-in-place (XIP) with the default 36. Pentium M should use 32, but doesn't even with this patch. Some Xeon and CORE(2) models should use 38 or 40. Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/639 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Supermicro X7DB8: add w83793 Hardware monitorSven Schnelle
used for fan control and thermal management on that board. Change-Id: I4e5c986ab6174b7a356d682e21732c46181af211 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1167 Tested-by: build bot (Jenkins)
2012-07-04Add Nuvoton W83793 hardware monitor driverSven Schnelle
Change-Id: I3ecb5c8666eea247bf4c31aaf9426bd9ef66bf68 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1166 Tested-by: build bot (Jenkins)
2012-07-03Fix AMD S3 block generator on CygwinPatrick Georgi
awk on Cygwin created the UTF-8 value for the 0xff code point, which makes it two bytes wide. This broke the build. Change-Id: I4937ae7ce1136ba7a76d05b42f9dd2771203175d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1164 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-03SMBIOS: move serial number and version out to KconfChristian Gmeiner
With this change it is possible to define serial number and version of the mainboard. These informations are used in SMBIOS tables. Change-Id: I1634882270f6cb94e00aceb7832e7fd14adc186b Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1163 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03Fix the error message for romstage when .bss or .data are non-zeroRonald G. Minnich
The error message from romstage is annoying and misleading: "Do not use global variables in romstage" Because it can occur even when global variables are not used in some circumstances, but also because it gives you only a rough idea where to look. This change sucks but sucks less. We still don't know which file the problem is in but at least we know if it is data or bss. Replace the error message with something that provides more information and less guessing on the part of the script: ".bss is non-zero size in romstage which is not allowed -- global variable?" or ".data is non-zero size in romstage which is not allowed -- global variable?" To test: build coreboot as normal. It builds. Add char d[32]; to romstage.c and get the first error message; add int x = 32; to romstage.c and get the second. Change-Id: I300ec05bdb4b30d7ef3f5112e6cc09b1fafe8263 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1160 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03AGESA F15 wrapper for Trinityzbao
The wrapper for Trinity. Support S3. Parme is a example board. Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03AGESA F15tn: AMD family15 AGESA code for Trinityzbao
AMD AGESA code for trinity. Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
The new broadcast code doesn't support serial init - if a CPU needs serial init, this should be handled in the model specific CPU init code. Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1140 Tested-by: build bot (Jenkins)
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
The current code for initializing AP cpus has several shortcomings: - it assumes APIC IDs are sequential - it uses only the BSP for determining the AP count, which is bad if there's more than one physical CPU, and CPUs are of different type Note that the new code call cpu->ops->init() in parallel, and therefore some CPU code needs to be changed to address that. One example are old Intel HT enabled CPUs which can't do microcode update in parallel. Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1139 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-02Intel CPUs: execute microcode update only once per coreKyösti Mälkki
Early HT-enabled CPUs do not serialize microcode updates within a core. Solve this by running microcode updates on the thread with the smallest lapic ID of a core only. Also set MTRRs once per core only. Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1142 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-29libpayload: OHCI driver correct PCI BAR readingAnton Kochkov
Correct registers base (PCI BAR) reading to be more specification friendly. Registers base only in [31-12] bits, all other proposed to be 0 but that not true for some motherboards. So adding mask to use only valid bits. Change-Id: I2e9a4997e016dab812ccfe654e966bc91d42a625 Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1143 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-29libpayload: use correct types in UHCI driverAnton Kochkov
As we using 16-bit reading and writing in UHCI drive, so all variables related to that must be 16-bit too. Change-Id: Ib1abb03d054c167512e21f24f3c3da688c7fd01f Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1144 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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