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2017-03-17soc/intel/broadwell: Fix spacing issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that '<=' (ctx:WxV) ERROR: spaces required around that '<=' (ctx:VxV) ERROR: spaces required around that '>' (ctx:VxV) ERROR: spaces required around that '>=' (ctx:VxV) ERROR: spaces required around that '+=' (ctx:VxV) ERROR: spaces required around that '<' (ctx:VxV) ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" ERROR: space required before the open parenthesis '(' WARNING: space prohibited between function name and open parenthesis '(' WARNING: please, no space before tabs WARNING: please, no spaces at the start of a line False positives are generated for the following test: WARNING: space prohibited between function name and open parenthesis '(' in both pei_data.h and pei_wrapper.h TEST=None Change-Id: Icab08e5fcb6d5089902ae5ec2aa5bbee5ac432ed Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18872 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-17google/veyron: Clean out unused board variantsJulius Werner
We have code for certain Veyron variant names that were either never made into an actual board (Gus, Nicky, Thea) or used for Google-internal test boards that no longer exist (Pinky, Shark). Let's clean them out to avoid confusing people. Change-Id: Icdce5f0f3613e089d0994318b02dba54170f0c42 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18860 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-17google/veyron: Work around RAM code strapping errorJulius Werner
With a recent patch (google/veyron_*: Add new Micron and Hynix modules) we switched RAM codes for Veyron boards to tri-state since we were running out of binary numbers. Unfortunately we only tested that change on Minnie and Speedy, and it turns out that it broke Jaq, Jerry and Mighty. The "high" RAM code pins on those boards were incorrectly strapped with 100Kohm resistors (as opposed to 1Kohm on Minnie and Speedy), which is too high to overpower the SoC-internal pull-down we use to differentiate "high" from "tri-state". Since we already used tri-state codes on some Minnie and Speedy SKUs we have to hack up the code to work differently on these two groups of boards to keep everything working. BRANCH=veyron BUG=b:36279493 TEST=Compiled, confirmed ram_code called the right function depending on board. Change-Id: I253b213ef7ca621ce47a7a55a5119a167d944078 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18859 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-17mainboard/google/poppy: Enable EC SW syncFurquan Shaikh
Now that EC on poppy is stable, it is time to switch on EC SW sync. BUG=b:36178824 BRANCH=None TEST=Verified that EC SW sync is done properly and device boots to OS. Change-Id: I1395ad8af73128a8dd220351f5b5da157659b19e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18838 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17soc/intel/apollolake: Reduce D3 cold delay for eMMC controllerZhuo-hao Lee
eMMC Controller is taking over 100ms to resume during runtime which results in I/O latency issues on the Apollo Lake system such as Snappy. The cause is the Linux Kernel setting the firmware reset time to 100 ms by default. This patch adds _DSM method for eMMC comtroller for specifying the device readiness durations. Function index 9 returns package of five integers to set D3 cold delay to zero and ACPI constant Ones for the elements where overriding the default values is not desired. BUG=b:35774937 BRANCH=none TEST=update snappy coreboot and test i/o latency is under 100ms Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee@intel.com> Signed-off-by: Sowmya V <v.sowmya@intel.com> Change-Id: Idcfe4252b20bead15c2e5b9cb000ff797295f06a Reviewed-on: https://review.coreboot.org/18806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-17arch/x86: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I3495cd30d1737d9ee728c8a9e72bd426d7a69c37 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18864 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix prefer errors detected by checkpatchLee Leahy
Fix the following warnings detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: plain inline is preferred over __inline__ TEST=Build and run on Galileo Gen2 Change-Id: I8ba98dfe04481a7ccf4f3b910660178b7e22a4a7 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18863 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix space issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: space required before the open parenthesis '(' ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' ERROR: space prohibited after that open square bracket '[' ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: space required after that ';' (ctx:VxV) ERROR: spaces required around that ':' (ctx:ExV) ERROR: spaces required around that ':' (ctx:VxW) ERROR: spaces required around that ':' (ctx:WxV) ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that '+=' (ctx:VxV) ERROR: spaces required around that '<=' (ctx:WxV) ERROR: spaces required around that '||' (ctx:VxW) ERROR: space prohibited before that '++' (ctx:WxO) ERROR: need consistent spacing around '+' (ctx:WxV) ERROR: spaces required around that '<' (ctx:WxV) ERROR: spaces required around that '<' (ctx:VxV) ERROR: need consistent spacing around '>>' (ctx:WxV) ERROR: "(foo*)" should be "(foo *)" ERROR: "foo* bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: code indent should use tabs where possible WARNING: space prohibited between function name and open parenthesis '(' WARNING: unnecessary whitespace before a quoted newline WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs WARNING: Unnecessary space before function pointer arguments TEST=Build and run on Galileo Gen2 Change-Id: I2d7e1a329c6b2e8ca9633a97b595566544d7fd33 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix issues with braces detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: open brace '{' following function declarations go on the next line ERROR: that open brace { should be on the previous line ERROR: else should follow close brace '}' WARNING: braces {} are not necessary for any arm of this statement WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: I13d1967757e106c8300a15baed25d920c52a1a95 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18861 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17soc/intel/braswell: Fix most of the issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: that open brace { should be on the previous line ERROR: return is not a function, parentheses are not required WARNING: braces {} are not necessary for any arm of this statement WARNING: line over 80 characters WARNING: braces {} are not necessary for single statement blocks WARNING: Avoid unnecessary line continuations WARNING: break is not useful after a goto or return WARNING: else is not generally useful after a break or return False positives are generated by checkpatch for the following test: ERROR: Macros with complex values should be enclosed in parentheses TEST=Build for cyan Change-Id: I19048895145b138a63100b29f829ff446ff71b58 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18871 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-03-17soc/intel/braswell: Add int to unsignedLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build for cyan Change-Id: Ib5c6a1bf5308a8add42d7371854b80ea53d7ae84 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18870 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-03-17soc/intel/braswell: Fix spacing issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited before that ',' (ctx:WxE) ERROR: spaces required around that '=' (ctx:WxV) ERROR: code indent should use tabs where possible WARNING: space prohibited between function name and open parenthesis '(' WARNING: please, no spaces at the start of a line TEST=Build for cyan Change-Id: I84d4204585b498b695608c5008fdfb7961e2416f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18869 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-03-17soc/intel/skylake: Fix remaining issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: Macros with complex values should be enclosed in parentheses ERROR: "foo * bar" should be "foo *bar" ERROR: space required before the open parenthesis '(' ERROR: spaces required around that '=' (ctx:VxW) WARNING: space prohibited between function name and open parenthesis '(' WARNING: storage class should be at the beginning of the declaration WARNING: char * array declaration might be better as static const WARNING: please, no space before tabs WARNING: braces {} are not necessary for single statement blocks WARNING: else is not generally useful after a break or return WARNING: static const char * array should probably be static const char * const TEST=Build for glados Change-Id: Ic14ca3abd193cfe257504a55ab6b74782b26bf6d Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18868 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-17soc/intel/skylake: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch: WARNING: line over 80 characters TEST=Build for glados Change-Id: I79341f46ca06ac052f987975ccaf975470d27806 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18867 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2017-03-17soc/intel/skylake: Add int to unsignedLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build for glados Change-Id: Idc2ad265e8ed8cd7fd6d228cfbe4cbbcb9d3ebfc Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18866 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-16google/poppy: Use rt5663 interrupt as GpioInt instead of PIRQRizwan Qureshi
The kernel driver for rt5663 expects to get an interrupt on both a rising and falling edge, and using a legacy interrupt doesn't provide that flexibility. Instead configure this pin as a GPIO and use the interrupt through the GPIO controller. This allows using GpioInt() with ActiveBoth setting and results in correct operation of the headset jack. This is a clone of Duncan's patch for eve at I6f181ec560fe9d34efc023ef6e78e33cb0b4c529 BUG=none BRANCH=none TEST=test on poppy that headset jack detect is read properly at boot, and that plugging in and removing both generate a single interrupt event in the driver. Change-Id: I4aaa4164cb277a98ab5d5f033632f5e16bfb779e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18853 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16google/eve: Use rt5663 interrupt as GpioInt instead of PIRQDuncan Laurie
The kernel driver for rt5663 expects to get an interrupt on both a rising and falling edge, and using a legacy interrupt doesn't provide that flexibility. Instead configure this pin as a GPIO and use the interrupt through the GPIO controller. This allows using GpioInt() with ActiveBoth setting and results in correct operation of the headset jack. BUG=b:35585307 BRANCH=none TEST=test on Eve that headset jack detect is read properly at boot, and that plugging in and removing both generate a single interrupt event in the driver. Change-Id: I6f181ec560fe9d34efc023ef6e78e33cb0b4c529 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18836 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16i2c/generic: Add support for GPIO IRQDuncan Laurie
Add support for using GPIO IRQ instead of PIRQ with an I2C device. This allows a device to use an edge triggered interrupt that will trigger on both high and low transitions. The _DSD method for describing these GPIOs has a field for 'active low' which is supposed to be 1 if the pin is active low, otherwise is zero. The value in here doesn't mean too much for GpioInt() as those will end up using the value from GpioInt() when it actually requests the interrupt. BUG=b:35581264 BRANCH=none TEST=test on Eve board that codec IRQ can be delcared as GPIO IRQ Change-Id: I02c64c7fc28dc2d608ad40db889c7242892f16db Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18835 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-16acpi_device: Add macro for GpioInt that uses both polarityDuncan Laurie
GPIO edge interrupts can report that they are ActiveBoth and will generate an interrupt event on both rising and falling edges. Add a macro so this type of GPIO interrupt can be used. BUG=b:35581264 BRANCH=none TEST=successfully use this interrupt type on Eve Change-Id: I91408386538e442bddcacc9840e0aa14370a446c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18834 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-16acpi_device: Prefix IRQ macros with ACPIDuncan Laurie
Switch some IRQ_* macros to ACPI_IRQ_* instead so they do not fail at compile time if they are used. BUG=b:35581264 BRANCH=none TEST=successfully compile with ACPI_GPIO_IRQ_LEVEL_HIGH Change-Id: Id4040eca4c7c9d8f7b4f0add411d5d6fe5ed1eb8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18833 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-16binaryPI: Fix SSE regression and align stack earlyKyösti Mälkki
When allowing use of SSE instructions, stack must be aligned to 16 bytes. Adjust x86 entry to C accordingly, by pushing values to maintain the alignment. For some builds, new toolchain and GCC-6.3 could emit SSE instruction 'andps (%esp),%xmm0' with incorrectly aligned esp, raising exception and thus preventing boot. Change-Id: I452d40eadac2b743d0d8431809c9a81bf28c330a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-16asrock/e350m1: Include ASL for PS/2 controllerPaul Menzel
On the ASRock E350M1, with Linux 4.10 after resuming from S3, the PS/2 keyboard does not work. Adding the ASL code, fixes this. The Linux messages change like below. Before (equivalent to `i8042.nopnp`): ``` kernel: i8042: PNP: No PS/2 controller found. kernel: i8042: Probing ports directly. kernel: serio: i8042 KBD port at 0x60,0x64 irq 1 kernel: serio: i8042 AUX port at 0x60,0x64 irq 12 kernel: mousedev: PS/2 mouse device common for all mice ``` After: ``` kernel: i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1 kernel: i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp kernel: serio: i8042 KBD port at 0x60,0x64 irq 1 kernel: mousedev: PS/2 mouse device common for all mice ``` Change-Id: I0a06311860398cac9cf1a077e3aba75da779f45d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18574 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-03-16cpu/intel: Fix the remaining issues detected by checkpatchLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: switch and case should be at the same indent WARNING: Consecutive strings are generally better as a single string WARNING: static const char * array should probably be static const char * const TEST=Build and run on Galileo Gen2 Change-Id: I03d5d0d2db0d5e9b33c8ec807b236fe229bcc8f3 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/intel: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I74f25da5c53bd518189ce86817d6e3385b29c3b4 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18850 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/intel: Fix brace issues detected by checkpatch.plLee Leahy
Fix the following error and warning detected by checkpatch.pl: ERROR: that open brace { should be on the previous line WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: Icdd6bd9ae578589b4d42002d200fa8f83920265e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18849 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/intel: Add int to unsignedLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build and run on Galileo Gen2 Change-Id: I207713a3370e5a9abed4535187aa2aaeef502d6f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18848 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16mainboard/google/reef: Increase PL2 Max to 15WTim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_DVT_v0.6_20170314.xlsx) 1. Increase PL2 Max to 15W. BUG=b:35583586 BRANCH=reef TEST=build and verify PL2 Max value on electro dut Change-Id: I13167e28267d5827d79a6bde31f077a01f2bd535 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18807 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16cpu/intel: Fix the spacing issuesLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: spaces required around that '=' (ctx:VxV) ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' ERROR: need consistent spacing around '-' (ctx:WxV) ERROR: spaces required around that '>' (ctx:VxV) ERROR: need consistent spacing around '>>' (ctx:WxV) ERROR: need consistent spacing around '<<' (ctx:VxW) ERROR: spaces required around that '||' (ctx:VxV) ERROR: "foo * bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" WARNING: space prohibited between function name and open parenthesis '(' WARNING: storage class should be at the beginning of the declaration TEST=Build and run on Galileo Gen2 Change-Id: I6602fbc8602171ab6c2f3b6c204558ad2c811179 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18847 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/intel: Indent with tabsLee Leahy
Fix the following error and warning detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no space before tabs TEST=Build and run on Galileo Gen2 Change-Id: I5bcd82561ef5856e99055d46528dcf3a283d2310 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18846 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/x86: Fix misc. remaining issues detected by checkpatchLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: trailing statements should be on next line WARNING: storage class should be at the beginning of the declaration WARNING: type 'long unsigned int' should be specified in [[un]signed] [short|int|long|long long] order TEST=Build and run on Galileo Gen2 Change-Id: I9cfe42cf1836cfd40ffcf67237c818543f508feb Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18845 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/x86: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I56ea28826963403dc0719f40c13782c56dc97feb Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18844 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/x86: Add int to unsignedLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build and run on Galileo Gen2 Change-Id: I97bbe8ba19680bdb99fa38daa5e18b440c338576 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18843 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/x86: Remove braces and else if unnecessaryLee Leahy
Fix the following warnings detected by checkpatch.pl WARNING: braces {} are not necessary for single statement blocks WARNING: braces {} are not necessary for any arm of this statement WARNING: else is not generally useful after a break or return TEST=Build and run on Galileo Gen2 Change-Id: I2d6b22c66d52f5f2d24b15270ad4b52894adebc2 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18842 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/x86: Use tabs for indentLee Leahy
Fix the following error and warning detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no spaces at the start of a line TEST=Build and run on Galileo Gen2 Change-Id: Ie6e4dd4c3eb0d2c44ecd008740dfc348d496fe78 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18841 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/x86: Fix various issues detected by checkpatch.plLee Leahy
Fix the following errors and warning detected by checkpatch.pl: ERROR: spaces required around that '=' (ctx:VxV) ERROR: space prohibited after that open parenthesis '(' ERROR: need consistent spacing around '|' (ctx:WxV) ERROR: need consistent spacing around '|' (ctx:VxW) ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that '==' (ctx:VxV) ERROR: spaces required around that ':' (ctx:ExV) WARNING: space prohibited between function name and open parenthesis '(' TEST=Build and run on Galileo Gen2 Change-Id: I61d08055b207c607d5b7d72b0094ad8e24fbd106 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18840 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16src/cpu/x86: Remove space between * and variable nameLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" TEST=Build and run on Galileo Gen2 Change-Id: I8b5342df3f42dbb4576aecf5b0a59f195ae8511e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18839 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16mainboard/intel/galileo: Add vboot supportLee Leahy
Add the necessary files and changes to support vboot. TEST=Build and run on Galileo Gen2 with a SparkFun CryptoShield 1. Obtain and install a SparkFun CryptoShield. https://www.sparkfun.com/products/13183 2. Edit src/mainboard/intel/galileo/Kconfig to select VBOOT_WITH_CRYPTO_SHIELD 3. Use make menuconfig to update the config values and select a payload that will fit. I used SeaBIOS which does not boot. 4. Build coreboot 5. Use the command file below to generate the signed coreboot image. 6. Flash build/coreboot.rom onto the Galileo board 7. The test is successful if verstage detects that it needs recovery after Phase 1. This is expected because the image does not contain the GBB section. 8. Flash build/coreboot.signed.bin onto the Galileo board 9. The test is successful if verstage reaches Phase 4 and selects SLOT A to load the rest of the files. commands: gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob dd conv=fdatasync ibs=4096 obs=4096 count=1553 \ if=build/coreboot.rom of=build/coreboot.signed.rom dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \ of=build/coreboot.signed.rom dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 \ count=368 if=build/coreboot.rom of=build/coreboot.signed.rom gbb_utility \ --set --hwid='Galileo' \ -r $PWD/keys/recovery_key.vbpubk \ -k $PWD/keys/root_key.vbpubk \ build/coreboot.signed.rom 3rdparty/vboot/scripts/image_signing/sign_firmware.sh \ build/coreboot.signed.rom \ $PWD/keys \ build/coreboot.signed.rom Change-Id: I02eb0ef647cd34c13a5fe8be0bdbe1bb38524d0c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18821 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16drivers/i2c/tpm: Add support for Atmel TPM (AT97SC3204)Lee Leahy
The I2C interface for the Atmel AT97SC3204 TPM varies greatly from the existing I2C TPM support. The Atmel part just passes the commands and responses from the TIS layer across the I2C interface. TEST=Build and run on Galileo Gen2 with Crypto Shield and vboot enabled Change-Id: Ib2ef0ffdfc12b2fc11fe4c55b6414924d4b676dd Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18800 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16drivers/i2c/tpm: Add TPM (TIS) debugging supportLee Leahy
Add debugging support for the TIS transactions for the I2C TPM chips. TEST=Build and run on reef Change-Id: Ibc7e26fca781316d625f4da080f34749f18e4f9b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18799 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-15drivers/i2c/tpm: Fix issues detected by checkpatchLee Leahy
Fix the following warnings detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: braces {} are not necessary for single statement blocks WARNING: Unnecessary parentheses - maybe == should be = ? WARNING: line over 80 characters WARNING: missing space after return type TEST=Build and run on Galileo Gen2 Change-Id: I56f915f6c1975cce123fd38043bad2638717d88c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18832 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15google/eve: Update MCU GPIOs configurationVincent Palatin
Keep the BOOT0 pin triggering the MCU bootloader as an input, so the Servo debug board doesn't have to fight with the PCH to program it, the net already has an external pull-down to ensure that the MCU is in normal mode at boot. By default, do not drive the FP sensor reset from the PCH, the MCU is now managing the reset line (but the PCH still has a connection on the current boards). BRANCH=none BUG=b:36025702 TEST=manual testing, program the MCU through a Servo v2 board, and use the FP sensor through the MCU and verify it is not stuck under reset. Change-Id: I19113b5d78013d0ab6ec5a72c6f71dd4c67a88e8 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/18830 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-15google/eve: Apply default AC/DC loadline settingsDuncan Laurie
Set the AC and DC loadline values based on the KBL-Y 2+2 defaults that are applied by FSP. These will be tuned later and are exposed as defaults so the engineers know what to start with. BUG=b:36228330 BRANCH=none TEST=Build and boot on Eve and check debug FSP output to ensure that it is applying the provided loadline values Change-Id: Ieae4f2b201d8210e75bdb9438070a3a2e1fda6b7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18820 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-15intel/skylake: Support for setting AC/DC loadlineDuncan Laurie
Add options to set the AC and DC loadline values for each supported VR type so these can be tuned on a per-board basis in devicetree.cb. BUG=b:36228330 BRANCH=none TEST=Build and boot on Eve and check debug FSP output to ensure that it is applying the provided loadline values Change-Id: I2a5533d2c9fd86351c86584e3738e80ac4c1f915 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18819 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-15intel/skylake: Fix bug in VR configuration with FSP 2.0Duncan Laurie
With the move to FSP 2.0 the number of VR types supported was reduced to 4, and the VR_RING type is no longer present. This means all existing boards using FSP 2.0 are incorrectly passing VR configuration into FSP as the values corresponding to "GT Sliced" and "GT Unsliced" have changed. Fix this by updating the skylake SOC VR handling to account for changes in the FSP configuration and no longer provide VR_RING type when using FSP 2.0. BUG=b:36228330 BRANCH=none TEST=manual: build and boot on Eve Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-15google/eve: Use rt5514 instead of 4ch DMICDuncan Laurie
On this platform the DMICs are connected to the rt5514 DSP instead of directly connected to the SOC. Use the new rt5514 NHLT blob instead of the 4ch DMIC blob and add the required I2C and SPI entries in devicetree so this can get probed properly. BUG=b:35585307 BRANCH=none TEST=build and boot on Eve P1 and check for rt5514 driver enumerated by the kernel Change-Id: I0f2cb532771ee1857df7f33c52a96acf96dc1f54 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18817 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-15intel/skylake: nhlt: Add support for rt5514 NHLT blobDuncan Laurie
Add support for describing the NHLT blob for the rt5514 DSP. Currently this only supports 4 channel capture. BUG=b:35585307 BRANCH=none TEST=build and boot on Eve P1 Change-Id: Ib59b56222f9aa65370fdcf9ddf25145c571b1b2e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18816 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-15acpi: device: Add macro for active high level triggered IRQDuncan Laurie
Add the missing macro for ACPI_IRQ_LEVEL_HIGH so it can get used by devicetree when necessary. BUG=b:35585307 BRANCH=none TEST=Add rt5514 SPI device with active high level IRQ on Eve board and check that it is enumerated in the kernel Change-Id: I25c7b035a198efb218f0f6b4ba3f4a1bf532bcea Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18815 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-15AGESA f14: Fix infinite loopKyösti Mälkki
Fix regression after commit: 22f32c7 cpu/amd/agesa: Unify init files Change-Id: I36fb7369084c68577df69abc251c84dad64f7015 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18822 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2017-03-15siemens/mc_apl1: Clean up the codeMario Scheithauer
This patch make some general adaptations in relation to commit 6a489237 (mainboard/intel/leafhill: Clean up). - add necessary defaults to Kconfig - remove irrelevant entries from FMD file - include romstage file for better understanding Change-Id: I190d648a7ffeca11acc6560db85ff03c78e85b21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18808 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-15soc/intel/quark: Read the rmu.bin file from read-only regionLee Leahy
Always read the rmu.bin file from the read-only section of the SPI flash. Without this change vboot attempts to read this file from the A or B section of the flash. TEST=Build and run on Galileo Gen2 Change-Id: Ied8eaa2cd37645bf401aa957936943946bfd6182 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 09:03:57 +0000