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AgeCommit message (Expand)Author
2012-07-25Fix LAPIC timer on Ivy Bridge systemsStefan Reinauer
2012-07-25ELOG: Add support for a monotonic boot counter in CMOSDuncan Laurie
2012-07-25ELOG: Add support for generating SMBIOS type15 tableDuncan Laurie
2012-07-25More descriptive error messages in Sandybridge raminit codeStefan Reinauer
2012-07-25bd82x6x: Drop unneeded pci_dev_tStefan Reinauer
2012-07-24ELOG: Fix boot count increment for non-wake caseDuncan Laurie
2012-07-24Ivybridge: fix workaround and enable PAIRDuncan Laurie
2012-07-24CPU: Set flex ratio to nominal TDP ratio in bootblockDuncan Laurie
2012-07-24SMM: Fix state save map for sandybridge and TSEGDuncan Laurie
2012-07-24SMM: Add option for SPI driver to be available in SMMDuncan Laurie
2012-07-24SMM: Add support for malloc in SMM if using TSEGDuncan Laurie
2012-07-24ELOG: Add support for flash based event logDuncan Laurie
2012-07-24SMM: Add heap region and move C handler higher in regionDuncan Laurie
2012-07-24CPU: Update ivybridge PP1 current limit valueDuncan Laurie
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
2012-07-24Rename cache_lbmem() to cache_ramstage()Stefan Reinauer
2012-07-24Implement stack overflow checking for the BSPRonald G. Minnich
2012-07-24Fix automatic ME detection in finalizeStefan Reinauer
2012-07-24ChromeOS: Remove board specific acpi_get_vdat_info()Stefan Reinauer
2012-07-24Cougar/Panther Point: Compile in ME7 and ME8 code at the same timeStefan Reinauer
2012-07-24Fix ME hash functions on Panther Point/Cougar PointStefan Reinauer
2012-07-24Config changes to support microcode in CBFSVadim Bendebury
2012-07-24Add BAR address debug information to Oxford PCIe serial driverMarc Jones
2012-07-24Add microcode blob processingVadim Bendebury
2012-07-24Add code to read Intel microcode from CBFSVadim Bendebury
2012-07-24Add PCIe port disable debug messageMarc Jones
2012-07-24Make MAX_PHYSICAL_CPUS invisible on non-AMD boardsStefan Reinauer
2012-07-24bd82x6x: Support power-on-after-power-fail betterStefan Reinauer
2012-07-24Rename microcode include file to be model agnosticVadim Bendebury
2012-07-24Fix function generating GPIO state based vectorVadim Bendebury
2012-07-24Make ACPI code detect Sandy/Ivy Bridge dynamicallyStefan Reinauer
2012-07-24Shrink the stack sizes we need in corebootRonald G. Minnich
2012-07-24Add specific power management init code for PantherPointDuncan Laurie
2012-07-24Drop (empty) sandybridge_late_initialization()Stefan Reinauer
2012-07-24Remove CMOS Extended range enable from romstageDuncan Laurie
2012-07-24RTC: Enable extended CMOS in the bootblockDuncan Laurie
2012-07-24bd82x6x: Convert all PCI ID lists to new schemeStefan Reinauer
2012-07-24Add support for HM70 and NM70 LPC bridgeStefan Reinauer
2012-07-24cs5536: add smbus support in ramstageChristian Gmeiner
2012-07-24Add uartmem_init prototype.Marc Jones
2012-07-24RTC: Add defines for standard clock offsetsDuncan Laurie
2012-07-24Print PCI ID of PCH during boot upStefan Reinauer
2012-07-24ifdtool: Use perror for file write errorsStefan Reinauer
2012-07-24Drop leading spaces from CPU name stringStefan Reinauer
2012-07-24Properly identify ACPI C3 states in _CST table.Duncan Laurie
2012-07-24Remove unused free() functionStefan Reinauer
2012-07-24Add standard header to prevent multiple inclusionVadim Bendebury
2012-07-24Move GGL0001 ACPI code to generic ChromeOS codeStefan Reinauer
2012-07-24Fix MRC cache update delaysStefan Reinauer
2012-07-24Remove code that enables/disables VMX in coreboot on chromebooks.Ronald G. Minnich
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