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2018-01-05mainboard/google/zoombini: add mainboard_opsNick Vaccaro
Add mainboard.c to ramstage. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: Ic7275b07f28a99a91b978d2e8c4118c6858705bc Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-05vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v77_12Srinidhi N Kaushik
Update FSP header files to match FSP v77_12 Following fields have been added in FSP-S UPD: - SkipPunitInit (Skip P-unit Initialization) - HgSubSystemId (Sub system Vendor ID VGA) Change-Id: I6c4c2580b2d0d76038b495be31744c04cc0dc959 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/22820 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-05sb/intel/i82801ix: Don't select HAVE_INTEL_FIRMWARE on Q35-QEMUArthur Heymans
The Qemu q35 target doesn't support or needs Intel Firmware blobs so it doesn't make sense to select that option on this hardware. The result of this change will be that when changing the ROM chip size, CBFS_SIZE will automatically fill the whole flash which is desirable in this case. Change-Id: I89b0c2a7b3e9c163ce4b4eb5b38ab5fa70ba3cfa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23090 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-01-05mainboard/google/kahlee: Update Grunt devicetree.Justin TerAvest
Grunt's devicetree dropped some entries when it was split from the kahlee variant. This commit restores: spd_addr_lookup - memory information for AGESA dram_clear_on_reset - keeps DRAM contents on reset uma_mode - needed for vbios uma_size - needed for vbios Change-Id: I1d8cdc97594867f1d706318370055087976a5104 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05soc/intel/cannonlake: Correct PMC/GPIO routing informationLijian Zhao
PMC and GPIO DWx definition is not identical, hence update that to correct information. For cannonlake lp PCH, GPIO group C, group E and group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add function call to set up GPE routing in bootblock stage. TEST=Boot up into OS, and manually check PMC GPE status Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-01-05nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeoutArthur Heymans
Especially on ICH7 failing to do so results in i2c block read being unusable. On ICH10 this problem doesn't manifest itself that much. This moves disabling the watchdog reboot to the northbridge code like i945 (even though it technically is southbridge stuff). TESTED on Intel DG41WV: hacking on raminit is much nicer since no need to do a hard power down for +4s are needed to clear the timeouts. Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-05soc/amd/common: load post-memory AGESA as rmoduleAaron Durbin
Now that the AGESA binary is split into two sections load the post-memory AGESA binary into ram. It needs to be an rmdoule so that it can be relocated into ram. agesawrapper_amdinitenv() entry CBFS: 'VBOOT' located CBFS at [10000:cfd40) CBFS: Locating 'AGESA_POST_MEM' CBFS: Found @ offset 875c0 size 11c5e Decompressing stage AGESA_POST_MEM @ 0xc757ffc0 (183452 bytes) Loading module at c7580000 with entry c7580000. filesize: 0x2bafc memsize: 0x2bb0d Processing 1112 relocs. Offset value of 0xc7780000 AGESA call 00020001 using c75818fe AGESA call 00020003 using c75818fe Fch OEM config in INIT ENV Done agesawrapper_amdinitenv() returned AGESA_SUCCESS BUG=b:68141063,b:70714803 TEST=Booted kahlee. Change-Id: Ic0454e0d6909cb34ae8be2f4f221152532754d61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05soc/amd/common: Allow AGESA file split for pre- and post-memoryJustin TerAvest
By splitting the binary files for platform initialization, the post-memory code can be modified to stop executing in place (--xip). This change creates two separate sections in CBFS for AGESA and loads the appropriate file at the correct stage. BUG=b:68141063 TEST=Booted kahlee with split agesa enabled. Change-Id: I2fa423df164037bc3738476fd2a34522df279e34 Signed-off-by: Justin TerAvest <teravest@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-04util/gitconfig: Do not wait for user inputAlex Thiessen
When running `make gitconfig` on a freshly cloned repository, the script will wait for user input without a prompt in a call to `sed`, caused by a spurious newline introduced in commit 9ab8ae6a (util/gitconfig: Make gitconfig a bash script). Change-Id: I2aa722c052d24dcffa9688df09bcf8dc767bd0b6 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-01-04util/gitconfig: Support dash in pre-commit hookAlex Thiessen
On debian systems, /bin/sh is `dash` which has built-in `echo` always interpreting escape sequences such as '\n'. The pre-commit hook uses the built-in for piping diff to checkpatch, interpreting the diff's escape sequences in the process and leading to false negatives and preventing commits despite conformance. Use `printf` instead of `echo` when handling diff content. The bug was introduced in commit ef869305 (util/gitconfig: update pre-commit script). Change-Id: I37edfe7b32721cb63d99299563cb11f26082c9a9 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-03soc/amd/stoneyridge: Add I2C supportChris Ching
BUG=b:69416132 BRANCH=none TEST=make Change-Id: Id940af917c9525aba7bc25eea0821f5f36a36653 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-02soc/amd/common/block/pi: Format files to standardsRichard Spiegel
Files agesawrapper.c and heapmanager.c have several non-conformity with coreboot standards, including lines longer than 80 characters, use of "} else {" after a return and wrong comment block formatting. Fix all such issues, so that it passes commit tests. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, just file formatting). Change-Id: Iefe741cd62bc41a7975c3dd10ac9355352de3abb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-02mb/google/poppy/variants/nami: Add empty_ddr4.spd.hex for DDR4Kane Chen
The spd size of DDR4 is 512, but the size empty.spd.hex is 256. With empty.spd.hex and DDR4, it will cause mainboard_get_spd_data loads spd data incorrectly due to the offset is wrong. Change-Id: Iea3f216898525a2a602fabf1835c8a0c1245ee57 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-02google/fizz: Enable SataPwrOptEnable FSP UPDKane Chen
This change is to enable SataPwrOptEnable. With this change, we no longer see SError message in kernel during suspend_stress_test. BUG=b:70491485 Change-Id: Ieb991f6889c5ff3181a670bc7702314049fa983c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-02soc/intel/skylake: Add device setting for sata power optimizationKane Chen
This change provides option in devicetree and feeds the option to FSP SataPwrOptEnable UPD for power saving purpose BUG=b:70491485 Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-25mb/hp: Add CMOS support for all HP Elitebook modelsIru Cai
The cmos.layout files are copied from lenovo/x230 with EC options removed. It's tested on 8470p and the power_on_after_fail option works. Change-Id: I0a50a25798fd31b7acccf9872c50dac2718ce895 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/22842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-25ec/hp/kbc1126: change the default offset of the blobsIru Cai
Using Kconfig options USE_OPTION_TABLE, BOOTBLOCK_NORMAL makes the bootblock to 4200 bytes, so the offsets of these blobs need to be put at a lower address. Change-Id: I8754e43ff318a03447633f7a9a8326d315328607 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/22978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-24drivers/mrc_cache: Make CACHE_MRC_SETTINGS not selectableArthur Heymans
Don't allow the user to select this manually, since it doesn't build on platforms that don't use it. Don't set the bool value so that it doesn't show as not selected in the .config file of platforms that don't use this. Change-Id: Icf026a297204868d485be270ccee7e0bec0ac73b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-23soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2Furquan Shaikh
BUG=b:70628116 Change-Id: I40ebbb143b4618f83f454b9db2717589ba5ce99e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22956 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-23soc/intel/common/block/gspi: Add SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2Furquan Shaikh
Even though kaby lake and cannon lake are using the same GSPI controller, bit meanings (for polarity and state) in SPI_CS_CONTROL register are significantly different. This change provides a new Kconfig option that can be selected by SoCs using these new bit definitions of SPI_CS_CONTROL. Common code takes care of setting the right value for polarity and state field depending upon the version selected by SoC. BUG=b:70628116 Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-23soc/intel/{apollolake, cannonlake, common, skylake}: Add _soc_ prefix in ↵Subrata Banik
weak function This patch ensures all soc function name is having _soc_ prefix in it. TEST=Able to compile SMM common code for all supported SOC. Change-Id: Iab1b2f51eaad87906e35dbb9e90272590974e145 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22mb/intel/dcp847ske: remove reference to non-existent fileAaron Durbin
In commit 7a95204 (intel/dcp847ske: Add Intel NUC DCP847SKE) the default_irq_route.asl file was removed, but this mainboard was missed. Follow suit with the original intent of the commit and fix the build breakage. Change-Id: I909dad7cfc0fab37e29187b2358f7f056216a403 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22975 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-22purism/librem_skl: Improve boot time by enabling SPD Word ReadYouness Alaoui
This speeds up the SPD read ('calling FspMemoryInit' phase) from 218ms to 134ms consistently. Tested on both the Librem 13 v2 and Librem 15 v3. Change-Id: I44fbe96c256972bd074537159771d61fe7adf082 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/22969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-22soc/amd/stoneyridge/chip.c: Move setup_bsp_ramtop to soc_init()Richard Spiegel
Issue first reported at commit 1587dc8a2b, the call of functions setup_bsp_ramtop() and setup_uma_memory() should be moved from enable_dev() to soc_init(). The function setup_uma_memory() no longer exists, its functionality transfered to agesawrapper_amdinitpost. Move setup_bsp_ramtop() as required. BUG=b:62240756 TEST=Build and boot kahlee. Change-Id: I44e6cab17a8f7f364fc57657f41b211ec9d17641 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-22soc/intel: Treat time-out as failure in HECILijian Zhao
If HECI gets times out when waiting for read slots, there's no need to read back reply message to decide if the HECI recieve successed or not. Otherwise, system will stuck after global reset required. BUG=b:707290799 TEST=Boot up meowth board without battery, and confirm hard reset got trigged after heci time out. Change-Id: I7c1655284d7027294d8ff5d6a5dbbebe4cbd0c47 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22inteltool: Add hint for compiler to avoid fall-through warningPaul Menzel
Falling through is intended here, so add a comment that GCC will notice and stop warning about this. Change-Id: I12637b6bc18844a3bc47f06208df7fee7a4feb3b Found-by: gcc-7 (Debian 7-20170316-1) 7.0.1 20170316 (experimental) [trunk revision 246203] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Omar Pakker Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-12-22intel/dcp847ske: Add Intel NUC DCP847SKETobias Diedrich
https://ark.intel.com/products/71620/Intel-NUC-Board-DCP847SKE Created using autoport and manual edits. mainboard_fill_pei_data copied and adjusted from samsung/lumpy. Tested: - RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V). - RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V). - SeaBIOS stable payload. - Linux 4.13.14 payload. - Booting into Linux 4.13.14 with Debian/unstable installed on the internal mSATA slot. - Non-native raminit (works). - Native raminit - KVR1333D3S9 doesn't work. - KVR16LS11 only works at 1.5V. - Native VGA init, HDMI port detection with libgfxinit. - Basic ACPI functions (power button event; power-off; reboot). - Suspend to RAM and resume works. - PCIe WLAN in half-minicard slot. - USB device in half-minicard slot. - PCIe device in full-minicard slot. - mSATA device in full-minicard slot. - Fan spins up/down in response to CPU load. Known issues: - Native raminit fails timC calibration with the RAM I have. - Technical Product Specification mentions overcurrent protection for back panel and front panel USB connectors, but I haven't been able to trigger it with either native fw or coreboot (tried up to 2.5A load). Untested: - USB debug port. Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-22mb/google/fizz: revise LED0 behavior for link speed 100MbGaggery Tsai
This patch revises LED0 Green light behavior from patch 2ecf3f8c. For 100Mb link speed, LED0 should be OFF. BUG=b:65437780, b:68284778, b:69950854, b:65808944 BRANCH=None TEST=Run DUT with 100Mb and 1000Mb ethernet connection and observe LED0 is behaving as expected. Change-Id: Ia805c955711b8ce77eba087a28427a005c456fa1 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22964 Reviewed-by: David Wu <david_wu@quantatw.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-22amd/stoneyridge: Increase pre-cbmem console sizeMarshall Dawson
The existing stoneyridge pre-cbmem console log contains about 250 bytes of unused space. Increase this amount to accomodate any additional debug messages. BUG=b:64980233 TEST=Build and boot Kahlee, inspect console log with "cbmem -c" Change-Id: Ia307795e91d81ff9b2be027916081f6824f90bad Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion supportDivya Chellap
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22vendor/intel/skykabylake: Update FSP header files to version 2.9.2Balaji Manigandan B
There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source(s) of PCIe Root Ports. This UPD is used to disable clock source(s) of disabled PCIe Root Port which has active device connected. CQ-DEPEND=CL:*520658,CL:*520659 BUG=b: BRANCH=None TEST= Build and boot soraka Change-Id: Ia4e4d22be8b00a72de68ddde927a090d3441a76e Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Reviewed-on: https://review.coreboot.org/22692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-22ic2/designware: Move Intel i2c logic to shared driverChris Ching
BUG=b:70232394 BRANCH=none TEST=emerge-reef coreboot emerge-glados Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22soc/amd/stoneyridge: select RTCMarc Jones
Stoneyridge has an RTC. Elog requires it for timestamps. BUG=b:65485690 TEST=Build Kahlee with Elog. Check mosys eventlog list for timestamps. Change-Id: I4d820fbe11043e7e3153d67159f52274d5f14bae Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-22soc/intel/skylake: Make use of common SMM code for SKLSubrata Banik
This patch ensures skylake soc is using common SMM code from intel common block. TEST=Build and boot soraka/eve Change-Id: I8163dc7e18bb417e8c18a12628988959c128b3df Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/22826 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-22soc/intel/cannonlake: Add SoC API to make use SMM common codeSubrata Banik
Add SoC API to detect any illegal access to write into the BIOS located in the FWH. Change-Id: If526cbae9afee47fa272bdf74e04416aff100e88 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22soc/intel/common: Add missing SoC common function into SMM librarySubrata Banik
Modify SMM common code in order to accommodate SKL, CNL, APL, GLK SOC code. Change-Id: Ie9f90df3336c1278b73284815b5197400512c1d2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22869 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-21google/fizz: Enable ec sw sync gbb by defaultShelley Chen
firmware test team is requesting that default gbb flags set to 0x39 rather than 0x239 so that it's consistent with the default gbb flags of other platforms. BUG=b:70392534 BRANCH=None TEST=emerge-fizz coreboot chromeos-bootimage gbb_utility --get --flags image-fizz.bin and make sure that it returns 0x39 instead of 0x239 Change-Id: Ib73e4619b13f6b7c2d01598c926fbbd7d7eb9bef Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22962 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-21mainboard/google/fizz: Enable S0ixShelley Chen
Enable S0ix for fizz. BUG=b:67598361 BRANCH=None TEST=None. Need to be tested with EC and kernel as well. Change-Id: I981d2cc7e969a44567b0f21f63f68c78e73f5cb5 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22955 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-21google/kahlee: Select fanless SMU firmwareMarshall Dawson
Don't rely on the cascading default values. Ensure Kahlee uses the fanless versions of the SMU fimware by selecting it. Change-Id: I0761266f2a4026ebc251b64074c10481118734a2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-21pcengines/apu2: add support for apu4 variantPiotr Król
apu4 is new version of PC Engines platform, which contains 4 Ethernet ports and 4GB of RAM. In functional way it is very similar to apu3. Platform tested with booting Linux voyage (kernel 3.16.7) using USB and SeaBIOS as 1st stage and GRUB as 2nd stage bootloader. Also Debian (kernel 4.8.5) using iPXE. Change-Id: Ia7a9971d25d4ecc215c392be1e46dc1c10129ba7 Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/22629 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-21soc/intel/cannonlake: Implement pmc_soc_restore_power_failure as per EDSSubrata Banik
TEST=CNL_RVP is able to power on after reconnecting power supply. Change-Id: I41e655fe79d958cce9e627ea2f2380185364ab19 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22840 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-21soc/intel/skylake: Move Enable power button SMI code from smi.c to pmc.cSubrata Banik
Original commit hash aeb2d64c85ca2c3a77f50d57e3a92f6fc0a5c2d3 (soc/intel/skylake: Enable power button SMI when jumping to payload) Change-Id: Ia4fe2694006baf24ed475c85aaffa6a0d2a6031d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22868 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-21soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDSSubrata Banik
TEST=KBL_RVP is able to power on after reconnecting power supply. Change-Id: Ic707164a576ffb25418eb6553843cd8edc608800 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-21soc/intel/common: Add API to restore power failure into PMC common codeSubrata Banik
PMC config register need to program to define which state system should be after reapplied power from G3 state. 0 = System will return to S0 state 1 = System will return to S5 state 2 = System will return to previous state before failure Refer to EDS for detailed programming sequence. Change-Id: I0ce2cc77745d00a8cfe3eed7c6372af77e063d02 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22838 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-21mb/lenovo/x131e: remove reference to non-existent fileAaron Durbin
In commit 7f5efd90e (intel/bd82x6x: Use generated ACPI PIRQ) the default_irq_route.asl file was removed, but this mainboard was missed. Follow suit with the original intent of the commit and fix the build breakage. Change-Id: Iac233b802239e4e5cfc66d9545bb637ec4f9f541 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22958 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-12-20mb/intel/glkrvp: Configure SCI/SMI in glkrvp for ESPIShaunak Saha
This patch configures the EC_SCI_GPI when ESPI is enabled.Also adds mainboard espi handler function. TEST= Boot to OS and SMI/SCI is working when ESPI is enabled/disabled. Change-Id: I2b3845d54ad7c1f14edc86f71b3f968424711999 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20soc/intel/apollolake: Add SMI and SCI support for ESPIShaunak Saha
This patch adds the SMI bits for SMI_EN, SMI_STS and GPE register in pm.h. The southbridge handler for espi smi is also added. In gpe.h we add GPE0A_ESPI_SCI_STS which is bit 20 in GPE register and enables the setting of the ESPI_SCI STS bit to generate a wake event and/or an SCI/SMI. TEST= Boot to OS. Change-Id: I2b8372ffbe0949ddd4aa83bdd7c0a01ade3ed40e Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22758 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20mb/compulab/intense_pc: remove non-functional EC replayHal Martin
coreboot console output during POST shows that the EC replay fails to communicate with the EC. Since the replay has no effect, it should be removed from the boot process. coreboot log: Replaying EC dump .......Timeout while sending command 0x81 to EC! .......Timeout while sending data 0x00 to EC! (snip) .......Timeout while sending command 0x81 to EC! .......Timeout while sending data 0xff to EC! .......Timeout while sending data 0xff to EC! done Change-Id: I05fb6358b40f442337f5768afa6253cd9bc32ee1 Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/22736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-20mb/google/fizz: Enable mbox command for ISL VR c-state issueRizwan Qureshi
There is a potential IMVP8 issue for KBL that affects Intersil VRs Fizz is using one of the affected parts. The fix is to use an updated microcode and also send a mailbox box command from FSP. BUG=b:65499724 BRANCH=None TEST=Build and boot Fizz Change-Id: Iebfda02df88ea0d2aaf79e8449b95c0eb2165c6b Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/22763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20mb/lenovo: add Lenovo ThinkPad X131e (Intel)James Ye
The Intel version of ThinkPad X131e can ship with Sandy Bridge or Ivy Bridge processors. The mainboard uses 8MiB+4MiB flash chips, with the 8MiB chip containing the IFD and ME, and the 4MiB chip containing the BIOS. The flash chips can be accessed with an external programmer. This port was primarily created using autoport, with some parts adapted from lenovo/x230 and google/stout. Tested and working: - Machine type 3367AH5 / Intel Celeron 887 (Sandy Bridge) - Boots Debian GNU/Linux 9.2 (Linux 4.9.51) via SeaBIOS - Boot from internal SATA and USB - Native RAM init - Native VGA init - libgfxinit - VGA and HDMI display output - Keyboard, trackpoint, touchpad - Audio (speaker, headphones) - Ethernet (Realtek) - Display backlight - USB 3.0 ports - "Always on" USB port (EHCI debug) - SD card reader - Webcam - Fan and temperature sensors - ACPI S3 (Sleep) - CMOS - TPM Not tested: - WLAN/Bluetooth (Broadcom) - WWAN/mSATA (no card) - Other operating systems Not working or not implemented: - Fn keys - ACPI S4 (Hibernation) "Image mismatch: memory size" Change-Id: If8de3a9308997e2d57aee869023ee9a43a2db872 Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/20694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 14:33:43 +0000