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2016-01-19google/lars: Enable eMMC HS400 modedavid
Kingston eMMC can now run under HS400 mode. BUG=chrome-os-partner:48017 BRANCH=none TEST=run consecutive boot 100 times on Lars proto Kingston SKU, and MMC errors didn't happen. Change-Id: I3c16db6111273fbbabbfba1c315edc780fe23525 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ac474bd7bd33f11904a27691e9eb61bdaf212c6b Original-Change-Id: I9e47b6ba64ac94acff7673fca86fa62bfb30edd9 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320194 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/13004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19google/chell: Enable eMMC HS400 modeRyan Lin
Hynix eMMC can now run under HS400 mode. BUG=chrome-os-partner:47647 TEST=run consective boot 100 times on Chell EVT Hynix SKU, and MMC errors didn't happen. BRANCH=none Change-Id: Icb6fc03d0510d2c5aeb5b08ed7189e954ab39a72 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9966c430a508a13cf1a617f485a48866bec161ca Original-Change-Id: I6bec88f5c2813131a693ddba5523a9d43b2ebd45 Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319627 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13003 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19google/lars: Enable SaGv featuredavid
This change enables SaGv feature for skylake platform. As a result of this patch the skylake platform will train memory at both low & high frequency points. This will be used to dynamically scale the work point (voltage/frequencies). The value "3" here means enable. Following is the table for same. 0=Disabled (SaGv disabled) 1=FixedLow (Fixed to low frequency) 2=FixedHigh (Fixed to High frequency) 3=Enabled( SaGv Enabled.Dynamically changes) BRANCH=None BUG=chrome-os-partner:48534 TEST=Build and boot lars Change-Id: I82b1a428d2d3dce47f46de576f677cf2249b6b5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e252123cc73543d0f1b320af9d8873f99a45ab1 Original-Change-Id: I1a545ff2f38df23964378c0d833e29006b2c5557 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320022 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-on: https://review.coreboot.org/13002 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19intel/skylake: do not save MRC data in recovery modeharidhar
If the system is in recovery don't bother saving MRC training data. BRANCH=None BUG=chrome-os-partner:48534 TEST=Built for kunimitsu. Results show MRC data is not saved in recovery mode. Change-Id: I236b7fe1860ac86722562c9a749067496dfe98f8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: acca68bb5fece58549d762bfaef3e9f2eb0d3066 Original-Change-Id: Idb0cd7d7c789a58d05160968f6448cb59882056c Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com> Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319221 Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-on: https://review.coreboot.org/13001 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19intel/kunimitsu: Enable FspSkipMpInit tokenRizwan Qureshi
MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB. CQ-DEPEND=CL:310192 Change-Id: Idd9b1424f23765ce227005a322ac72d9e9fc841a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5c52d0f0cc5d480c87fababc3316009e3ade6e45 Original-Change-Id: I9d92046d0237680b8d562814a9a605a36efb9516 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312926 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12992 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/chell: Enable FspSkipMpInit tokenBarnali Sarkar
MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=none CQ-DEPEND=CL:319353 Change-Id: I22c1add182b299e2ad9d413bc13c5a5acc6a3179 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ccf89c9d1fe18b74c385e7d12a6aef5b63d7b243 Original-Change-Id: I53b754fd10a140588ad67d9292d9bc04a6d43677 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319194 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13000 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/lars: Enable FspSkipMpInit tokenBarnali Sarkar
MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in Lars with SkipMpInit enabled from CB CQ-DEPEND=CL:319353 Change-Id: Ib35d9072b883592d22466dfeb1fd45403c0479d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 91cf59ea7865568eca2ce242d81c4c486076d5ac Original-Change-Id: Ibb46fc6bc7e862c9ea8bc9f9b0d508c3707282a2 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319257 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12999 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19intel/skylake: Disable SaGv in recovery modeharidhar
This patch disables the SaGv feature in recovery mode. Since the memory training happens at both low and high frequency points when SaGv is enabled, recovery mode boot time increases by 5 seconds. To reduce this 5 second increase, the SaGv feature is disabled in recovery mode. The value "0" here means SaGv disable. Following is the table for same. 0=Disabled (SaGv disabled) 1=FixedLow (Fixed to low frequency) 2=FixedHigh (Fixed to High frequency) 3=Enabled (SaGv Enabled. Dynamically changes) BRANCH=None BUG=chrome-os-partner:48534 TEST=Built for kunimitsu. Results show recovery mode boot time is not affected (not increased). Change-Id: I77412a73a183a5dbecf5564a22acc6e63865123e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dc586079052acf9af573b68dff910386cd43484d Original-Change-Id: Ice3e1a630e119d40d3df52e3a53ca984e999ab0b Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com> Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315759 Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-on: https://review.coreboot.org/12998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19intel/skylake: Enable SaGv featureharidhar
This change enables SaGv feature for skylake platform.As a result of this patch the skylake platform will train memory at both low & high frequency points.This will be used to dynamically scale the work point (voltage/frequencies). The value "3" here means enable. Following is the table for same. 0=Disabled(SaGv disabled) 1=FixedLow(Fixed to low frequency) 2=FixedHigh(Fixed to High frequency) 3=Enabled(SaGv Enabled.Dynamically changes) BRANCH=None BUG=chrome-os-partner:48534 TEST=Built for kunimitsu. Tested on D1 silicon. Change-Id: I2892d631d64495e6aed453af4fd526f4bf5bed68 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e09d1a22927f5fcddd6c0be3f9edf3dcb8729be Original-Change-Id: I32a7a53805068a52b381affaf061d69062cd8651 Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com> Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315806 Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-on: https://review.coreboot.org/12997 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/lars: SPD changes for EVT boarddavid
Update Memory IDs for EVT board BUG=None BRANCH=lars TEST=Build and boot lars Change-Id: I8c0c731fc3a8eec0cb558137e9db90170debf2c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a95fbf063b2e41d551171228a1ea8cbcfdcaecc8 Original-Change-Id: I2be8a7db99f17ea2968d7e4c5de83cc3e4cbcd14 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319622 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12996 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19soc/braswell: Remove the unneccessary functions from pcie.cShaunak Saha
Functions in file pcie.c is not needed. TEST=Boot and test wifi and video playback Original-Reviewed-on: https://chromium-review.googlesource.com/298965 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I70337c0fc61c221330836ef17f6cefea8c5f0f11 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/12737 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19intel/skylake: Add support for IV feedback loop capture blobSathya Prakash M R
SSM4567 smart speaker needs Current and Voltage sensing to be captured and reported to the algorithm. This needs 4 CH capture blob. BUG=chrome-os-partner:48625 BRANCH=none TEST=Built and booted. Verified CBFS locates the blob. CQ-DEPEND=CL:*242635 Change-Id: Ie13622da9a9a8ce5930d32e52ddaf2e0d4862895 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 06f1a501dcb3fa6102eccdb3e24f9011b7869ab0 Original-Change-Id: I7b65b7582b619be53544ebbe4b3ea65398d32a34 Original-Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319020 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12995 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19arch/x86: Indent using tabs not spacesMartin Roth
No functional changes - just whitespace fixes. Signed-off-by: Martin Roth <martinroth@google.com> Change-Id: I8ffa87240bcbd3d657ed9dc619b5e5bf9de734d7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12853 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18payloads: fix dependencies for seabios and filoPatrick Georgi
config and revision data need to be around before they're added to CBFS. Change-Id: I195156773effd5137c3fda3639c002fbec6e7158 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12971 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18device/oprom/yabel: Update BSD license headersMartin Roth
All of the yabel files are BSD licensed. Change-Id: Ibe0b3bb67a96c57b5d693676f5e8f19b6bed90fa Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12972 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-18nb/intel/pineview: Fix decode_pciebar()Damien Zammit
Fixes bug that decode_pciebar() function was bypassed due to PCI_DEV(0,0,0) being detected as zero and function returning 0. Change-Id: Ia79bcebbe3ba36f479cbb24dbbb163a031d9c099 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13031 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-01-18google/glados: Enable FspSkipMpInit tokenBarnali Sarkar
MP init is already handled in coreboot, but it is also part of FSP. FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=none CQ-DEPEND=CL:319353 Change-Id: I81c54582a3c980ecdcf329347bcd5982802d681c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e60ee81acaeb1062a31a3e78ed2ba4ccfe816ec5 Original-Change-Id: I71dd07559dffb7886e489274ffc8e71686ca730f Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319370 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12994 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Change in UPD name from SkipMpInit to FspSkipMpInitBarnali Sarkar
Changing the UPD param name from "SkipMpInit" to "FspSkipMpInit" BRANCH=none BUG=none TEST=Build and booted in kunimitsu with FspSkipMpInit token enabled from Coreboot. Change-Id: I5ebe7a1338ac77a62d5aa2e48e083b4fb906bf28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cdaa95a82bc7e90637c6b90e33d88d040e085f58 Original-Change-Id: Ibdaa3d202f8f6f6f0ca6c6d4c6428f1616572f1d Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319353 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12993 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-18google/lars: Enable ALS connected to ECdavid
Lars has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=none BRANCH=none TEST=emerge-lars coreboot Change-Id: I406b634176dac3f4cf1894e6b386af3306d11ffa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37d96458a11c33899f210cc04d3bdab07ec18746 Original-Change-Id: I017aeed1a8684676557e483ffa895dc4bb125d26 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319364 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12990 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/lars: Add keyboard backlight supportdavid
BRANCH=lars BUG=None TEST=alt+f6, alt+f7 Change-Id: I20d44ae806facf7470ab50d7b9ca4f36404b6ea3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3bf8c26a11e632cc9f4112eace813478fb7ff8ca Original-Change-Id: Iaa59818f5d2d17eb6759cefa9b6fbfba82bb2fca Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319270 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12989 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/kunimitsu: Set BOOT_BEEP gpio to a default loRohit Ainapure
The BOOT_BEEP gpio is used to activate the buffer which isolates the I2S signals from PCH while doing a beep from depthcharge. It needs to be lo to deactivate the buffer for audio playback from OS. BUG=chrome-os-partner:47124 BRANCH=None TEST=boot depthcharge & test beep with devbeep. Boot OS and test audio playback. Change-Id: I047513f6cbe9590820dfe3c369161a157864be97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d0e04d6792a4511630b8111d0f4a64226042f3e6 Original-Change-Id: I0fa8f425ac413798740343823d026c6300c8eef1 Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319220 Original-Commit-Ready: Rohit M Ainapure <rohit.m.ainapure@intel.com> Original-Tested-by: Michael Rang <michael.rang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12988 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/fsp1_1: Fix enumeration timestamp and post codeLee Leahy
The timestamps and post codes for the beginning of the FspNotify calls are out of order. Reverse these entries to fix this error. BRANCH=none BUG=None TEST=Build and run on kunimitsu Change-Id: Ibfa1ba4b07e31bf3823469ac2dc7deaa8c67deab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3cd63c56c59337f0ff58fd11a78d08352cf6a04a Original-Change-Id: I4627860d3ebf446523a5662dbbc8e59153441945 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/318903 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Remove unused devicetree configuration variablesDuncan Laurie
The GPU panel configuration variables are unused on skylake and are no longer needed in chip.h. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-chell coreboot Change-Id: Ie6bfb676b5a32b4d4d39dda91b90fc7e973d38e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f261d7ca9ec93aae1362975efde11ac9657b7ca6 Original-Change-Id: If64594455754e4dea1f53511861b74ddd880c5b5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/318923 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12986 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/chell: Add VR config settingsrobbie zhang
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due to a known issue (not able to hit S0ix) on glados. The VR settings will then need to be updated per the board VR design. BRANCH=none BUG=chrome-os-partner:48466 TEST=Build and booted chell Change-Id: Ieb014e2a0cee1cb02a1c095da273b5ac1a19ef5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fcd47a2fb2b369a93d2992fa1c17c2ce91c0e948 Original-Change-Id: Iac197314702fe5897359afc1ad1636bbcdafa204 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317870 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12985 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/glados: Add VR config settingsrobbie zhang
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due to a known issue (not able to hit S0ix) on glados. The VR settings will then need to be updated per the board VR design. BRANCH=none BUG=chrome-os-partner:48466 TEST=Build and booted glados Change-Id: I42d360657ab7c47d66043f39b79540b69a9072d1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d06397c1c32136d1b6a1c1346ed722ad6926ce1a Original-Change-Id: Ib0746cd84c2c8af29f53a65a0a7b85966c918869 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317910 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12984 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: provide default VR configurationAaron Durbin
FSP 1.8.0 will do nothing with the VR settings if VrConfigEnable is non-zero. That behavior is not desired because it's not clear what the behavior will be for various processor SKUs. Instead provide default values for the VR config. Note that PSI3 and PSI4 are not enabled for those defaults. BUG=chrome-os-partner:48466 BRANCH=None TEST=Built and booted glados. Change-Id: I02cb5fbdd4549cc827a0b0e4006bc21da4593b55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a68c53e0fdf15584270dfafc679a22319f497d17 Original-Change-Id: I82b1d1da2cfa3c83ccc6a981e30ffac6fb6c8c4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/318263 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12983 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/glados: Add pull-ups on LPC address lines and setup PCH_WP earlyDuncan Laurie
Copy changes from chell to add 20K pull-up to LPC address lines and setup the PCH_WP signal early so it is set correctly in VBNV. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I3337cb9e5ee445471c7a0b61ee22869f66189b63 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c99dae3729636790c2ad457ec3271d2bd99fb1c4 Original-Change-Id: I7627ec263e710ce186cea15c805203395acf3e99 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317244 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12982 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Add devicetree setting for DDR frequency limit UPDDuncan Laurie
There is a UPD setting exposed by FSP that allows the DDR frequency to be limited. Expose this for devicetree. BUG=chrome-os-partner:47346 BRANCH=none TEST=tested by limiting DDR frequency to 1600 on chell EVT Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220 Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317243 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12981 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Add elog event for THERMTRIPDuncan Laurie
The THERMTRIP status bit is in GBLRST_CAUSE instead of GEN_PMCON like the EDSv1 indicates. Read this status bit and add an elog event if THERMTRIP has fired. BUG=chrome-os-partner:48438 BRANCH=none TEST=tested on chell EVT after thermtrip fired Change-Id: Icd52b753c7f3ab0d48095279f1255dd2dd08fd59 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b090c7897a8f99a685f523990235d83fafa063b2 Original-Change-Id: I5a287d7fdae2ba8ae8585cb9a4d4dd873393e1e6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317242 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12980 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/chell: Minor updates from EVT and FSP 1.8.0Duncan Laurie
- Add pullup on LPC address lines for leakage - Configure PCH_WP early so it gets set properly in VBNV - Disable SD card reader in favor of USB BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on chell EVT Change-Id: Ibac79c6cbef0515b1e8a513cfde5fee184e4c70a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ebd0c16a6009b74d3c6c36878c502fda9bb3020d Original-Change-Id: If2bc4eb546a1aab50d3688b6e92f8c38214c9cca Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317241 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12979 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/lars: Add VrConfig UPD parametersdavid
Follow kunimitsu setting of https://chromium-review.googlesource.com/#/c/313068/ BRANCH=none BUG=chrome-os-partner:48459 TEST=Build and boot in lars Change-Id: Iffa9e1307f478b1d72befd3e5af71e7d40bb55ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6c669014d0773d6790656dd6f957d2c860d00781 Original-Change-Id: I615d53a33ad8e750d4382e2a9ec397c5b6ff55e1 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317222 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12978 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/lars: Correct the output for crossystem wpsw_bootdavid
The write protect GPIO is not being configured early enough. This is leading to coreboot reading incorrect value, and writing the incorrect value in vboot shared file. This is leading to "crossystem wpsw_boot" always returning 0 even with the write protect screw in place during boot. BRANCH=none BUG=chrome-os-partner:48292 TEST=Build and boot on lars Change-Id: I28fbbd690ca6efb539422e9ba02f10e07cd35346 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d229ba9d8934dcb5f22b27ce0ad27601ec87d6ff Original-Change-Id: I64f2497a6bb3a50b0f58c67e2ab6751c4836fd89 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317130 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18skylake boards: csme: add p2sb device and hecienabled devicetree variableArchana Patni
The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0 (default) disables Heci1 and hides the device from OS. It internally uses the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb device in the devicetree which is necessary for hiding and unhiding the device. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for kunimitsu. CQ-DEPEND=CL:*238451 Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05 Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311913 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12977 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18util/lint: Update license linter, make stable versionMartin Roth
- Split the script up to make it easier to update and read. - Check for multiple different license strings. Not all files are GPL licensed. - Don't validate 0 length files - Update list of files to exclude from the license header check. - Add command line option to set directories to check - Add stable version to check a few directories that are fixed. This just calls the non-stable version with the directories to check. Change-Id: I90d4e93a20b4e1638ce4f43f8acbee72dc588625 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12909 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18header files: Fix guard name comments to match guard namesMartin Roth
This just updates existing guard name comments on the header files to match the actual #define name. As a side effect, if there was no newline at the end of these files, one was added. Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18toolchain.inc: Update commentsMartin Roth
This fixes some nits that were pointed out in a previous review, and adds a couple additional comments to explain what is happening. Change-Id: I1ca4bf59ba79744f79fbe73f4e226feeea1cc2ab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13019 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18console/: add missing license headersDamien Roth
These were copied from the linux kernel, so get the standard corboot GPL v2 header. Change-Id: I27ef3326cc42b7e005f94c8b4fd355012a89561d Signed-off-by: Damien Roth <yves.r.roth@gmail.com> Reviewed-on: https://review.coreboot.org/13023 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18commonlib/: Add missing license headersMartin Roth
These files are original to coreboot and get the standard coreboot GPL header. Change-Id: I19565b0d2424a6f37a95ab4d7b16742d23122d1e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18arch/riscv: Add missing license headersMartin Roth
Most of these files are original to coreboot and get the standard coreboot GPL header. encoding.h and atomic.h are from the riscv codebase and have their license. Change-Id: I32506b0ecf88be2f5794dc1e312a6cd9b2a271ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12906 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-18util/lint/kconfig_lint: Add 3 new checksMartin Roth
- Check that selected symbols are type bool - Check that selected symbols aren't created inside a choice - Check that symbols created inside a choice aren't created outside of a choice as well. Change-Id: I08963d637f8bdfb2413cfe831eafdc974d7674ab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12969 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18arch/x86/Makefile.inc: Update symbol check macroMartin Roth
This was breaking the build on OS X, but also wasn't working correctly under linux anymore either. It wouldn't print the illegal symbols when it failed. - Split the generation of the offenders file from the actual check for offending symbols and just send all output to /dev/null. - Rewrite the check for offending symbols in a way that works with OS X. Tested by adding a global variable to romstage and verifying the failure is shown correctly. Verified that it works correctly with no illegal variables. Change-Id: I5b3ac32448851884d78c3b3449508ffe014119ab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13018 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-18intel/kunimitsu: Power gate Kepler devicePravin Angolkar
This patch power gates the Kepler module on skylake kunimitsu board. This is required to save power since this is consuming over 500mw of power in all active use cases. The device can be powered on later by using the kernel driver as required by setting the kepler enable gpio high. BRANCH=None BUG=chrome-os-partner:45962 TEST=Build and Boot Kunimitsu and check lspci. The Kepler device should not be listed. Also power measurement of board should give approximately 300mW of reduction in power. Change-Id: I244a23385e20ef1431dc895536c8a47e1f5770d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8d4fb7d01f32ac307a351c307b8461628c0e5414 Original-Change-Id: Idafa74d7ff14d67a5b1e635f783efd84b5a7399c Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302277 Original-Commit-Ready: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12964 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/kunimitsu: Enable TPM PIRQRishavnath Satapathy
Enable the config option for TPM to use PIRQ instead of SERIRQ and enable the MAINBOARD_HAS_LPC_TPM option. BUG=chrome-os-partner:46335 BRANCH=none TEST=tested this patch with TPM ACPI driver(tpm_tis.force=0) Change-Id: I311cc7d2e70cc52a7e90f3c3c60d422b7b998789 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad9450c342c752f87e3385a2acd5dd79b65cc75f Original-Change-Id: Ib7b1b40c296fce80d5366bd19e7ff20d7161db95 Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316287 Original-Commit-Ready: Pravin K Angolkar <pravin.k.angolkar@intel.com> Original-Commit-Ready: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com> Original-Reviewed-by: Pravin K Angolkar <pravin.k.angolkar@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12963 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/kunimitsu: add nhlt supportNaresh G Solanki
Provide an option for including the NHLT blobs within the kunimitsu mainboard directory while also adding the ACPI NHLT table generation that the current hardware supports. Kunimitsu does support two audio codec, ADI and MAXIM, hence use AUDIO_DB_ID to read correct codec and craete NHLT table, this will also help to load only one amplifier ASL for machine driver consumption. BUG=chrome-os-partner:44481 BRANCH=None TEST=Built and booted kunimitsu board. Audio worked with both ADI and MAXIM audio card. CQ-DEPEND=CL:316352 Change-Id: Ic9b9af83a0229fdf5f1cb019245ae65ad9d2f06c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2db85062d65c5e831da297588aa4abb18d6ed1bb Original-Change-Id: I3b08f3f23b334799a81cde81a30d6f231cc8583f Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315450 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12959 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17intel/skylake: disable heci1 if psf is unlockedArchana Patni
This patch adds support for disabling the heci1 device at the end of boot sequence. Prior to this, FSP would have sent the end of post message to ME and initiated the d0i3 bit. This uses the Psf unlock policy and the p2sb device to disable the heci1 device, then lock the configuration and hide the device. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for kunimitsu or glados board. set the hecienabled policy to 0 and check for heci 1 device status in kernel lspci. CQ-DEPEND=CL:*238451 Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358 Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311912 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12976 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17intel/skylake: During RO mode after FSP reset CB lose original stateSubrata Banik
CB used to clear recovery status towards romstage end after FSP memory init. Later inside FSP silicon init due to HSIO CRC mismatch it will request for an additional reset.On next boot system resume in dev mode rather than recovery because lost its original state due to FSP silicon init reset. Hence an additional 1 reset require to identify original state. With this patch, we will get future platform reset info during romstage and restore back recovery request flag so, in next boot CB can maintain its original status and avoid 1 extra reboot. BUG=chrome-os-partner:43517 BRANCH=none TEST= build and booted Kunimitsu and tested RO mode Change-Id: Ibf86ff2b140cd9ad259eb39987d78177535cd975 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 40ddc21a97b318510116b7d5c4314380778a40f7 Original-Change-Id: Ia52835f87ef580317e91931aee5dd0119dea8111 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302257 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12975 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17google/lars: Enable TPM PIRQdavid
Enable the config option for TPM to use PIRQ instead of SERIRQ and enable the MAINBOARD_HAS_LPC_TPM option. BUG=none BRANCH=none TEST=tested this patch with TPM ACPI driver(tpm_tis.force=0) Change-Id: I761d623d1064b8030f2703500d174259bb20ca79 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2f7bdb1091b7dd62a3c0b4a2272ab9f56fd7acc9 Original-Change-Id: Id1a867980d2e28a1f328aa36bed3c846b2137bec Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317471 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12974 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17google/lars: Enable 20K PU on LPC_LAD 0-3david
At S0, S0ix and S3 LPC LAD signals are floated at 400~500mV. BRANCH=none BUG=chrome-os-partner:48331 TEST=Build and boot on lars Change-Id: I5582007e5caaf444740fa71c9761c27614aafee2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b855fd5834056a3f7d4aef91d634066006990a38 Original-Change-Id: I3a54f9f83f055e433cc1fea38169437ee7f9188f Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317071 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12965 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17intel/sandybridge/raminit: fix ODT settingPatrick Rudolph
Count DIMMs on current memory channel instead of all memory channels. The current code is only able to correctly handle the following memory configurations: One DIMM installed in either channel. Four DIMMs installed, two in each channel. Two DIMMs installed, both in the same channel. For systems that have any other configuration the DRAM On-Die-Termination setting is wrong. For example: Two DIMMs installed, one in each channel. Test system: * Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130) Change-Id: I0e8e1a47a2c33a326926c6aac1ec4d8ffaf57bb6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12892 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-01-17google/lars: Remove/Disable Wake on landavid
Remove the WakeConfigWolEnableOverride to disable WOL override configuration in the General PM Configuration B (GEN_PMCON_B) register BRANCH=none BUG=none TEST=Build and boot on lars Change-Id: I48d3b706517b6ea6bda44800f61bb11da64503fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eab69f2d725df739e5e0e5901a581ad58732cdf9 Original-Change-Id: I42c5a87150638171526ee67f194c1cd9d155203b Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317080 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12962 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>