Age | Commit message (Collapse) | Author |
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All code must agree on PCI enumeration for the CK804 device,
define these only once. The definition in enable_usbdebug.c was
different and was assumed incorrect.
Change-Id: I7d25c145afbad41db81a6b9b4f3956ad50fcb9f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8339
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This reverts commit b8716879917c420d9e7e2618e48b1411a0c6bcc8.
Use of #ifndef here makes it error-prone and hides errors.
Change-Id: I13a999250c80adedb6b3fd4963a862ff106750f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8338
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Ia4829447835dd26381185c586eaac210dc0591d9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8463
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This patch allows the user to set a maximum HT link frequency in
NVRAM, paralleling a similar option available in the proprietary
BIOS on some mainboards.
Change-Id: Iba3789262eefa52421e76533cbf14d9da2ef1de8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8462
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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The existing code generated invalid ACPI processor objects
if the core number was greater than 9. The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.
The modified code will function with up to 99 cores.
Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: I48d2cda330d8e8f1e58bc670e4e898479216e576
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8461
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: I19d6b56e3ac5e6e7946648b97c86a223b748e3bd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8460
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Icebc12d8f83494150a7bdd3adcc168d7b48b2e68
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8458
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8459
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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This removes spurious K8 options and adds appropriate K10 options.
File content taken from the functional K10 ASUS KFSN4-DRE board.
Change-Id: I237bb139056f39f21416268cb52d24c5bc5f111d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8456
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: I6ccf44645dabf8ac3674f40d3c5cbcf694aa6237
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8441
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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All settable memory controller options are now controlled by NVRAM,
making the Kconfig options irrelevant.
Change-Id: I9b2c8798d830e5c41bb9a108514e60d784d2ebc5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8452
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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K10 processors cannot operate at full memory speeds when more than a
certain number of DIMMs are installed on a specific channel. The
allowed DIMM numbers and speeds are listed in the BKDG; this patch
implements the appropriate frequency reduction to ensure stability.
Change-Id: I8ac5b508915e423d262ad36c49de1fe696df2ecd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8435
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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These values were originally hard-coded in the AMD MCT wrapper.
Change-Id: I12056d38d5348e70a44c192385e22e715e207792
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8454
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Ie7a73a5962e61585ebc427005e72715c8da4e0ac
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8451
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Iaece709f521aaf6689b71bc0c71606847c3e1e4e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8439
Tested-by: build bot (Jenkins)
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In specific configurations, such as homogeneous supercomputing systems,
changeable NVRAM parameters are more of a liability than a useful tool.
This patch allows a coreboot image to be compiled that will always set
the NVRAM parameters to their default values, reducing maintainance
overhead on large clusters.
Change-Id: Ic03e34211d4a58cd60740f2d9a6b50e11fe85822
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8446
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Ic86104d6e7811b0bda9279411db84f464324994a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8450
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Id837445f346e9ab0218ccca12794b519a8a71c0d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8449
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This fixes errors of the form:
error: 'Dct0MemSize' may be used uninitialized in this function
Change-Id: Ifc853aea9050994f5641c57a081aa0667331c995
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8455
Tested-by: build bot (Jenkins)
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TEST: Boot with corrupted CMOS and make sure console level defaults
to SPEW, instead of 0, and that cbmem console is not empty.
Change-Id: I8ab2423e99bbe116f52ad27f4b20427d8557f6ff
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8379
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch allows the following memory controller settings to be overridden in NVRAM:
Memory frequency limit
ECC enable
ECC scrub rate
Change-Id: Ibfde3d888b0f81a29a14af2d142171510b87655e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8438
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Currently the coreboot console log contains messages in the following
form.
Show all devs...Before device enumeration.
[…]
Show all devs...After init.
Add a space after the ellipse, so it’s better readable and it does not
look like a newline is missing.
Show all devs... Before device enumeration.
[…]
Show all devs... After init.
Change-Id: Ifa2a37b8d60c433c219df7533a79fced03b6271a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8424
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add the flags used by the Nvidia makefile and use HOSTCC
to build cbootimage. Note that adding -g makes the BCT
very large, so leave that flag out.
Change-Id: I4431efffdfdcbd030665b26f5b799352e38d1f95
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8411
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
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The default linking behavior of ramstage was changed in commit
* 8f99378 ARMv7/Exynos: Fix memory location assumptions
However, that commit failed to address the issue of maintaining
linking behavior on non-Exynos chips. As a result we ended up
linking ramstage at address 0, which is outside of SDRAM.
Explicitly link ramstage at SDRAM base for A10. This patch does not
address the issue on other chips that were broken by commit 8f99378.
Change-Id: I90fa41d3eabf110b5ab24c31b78ac6d0474e4083
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8443
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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PCIe root ports on devices 0:15.0 to 0:15.3 should at first all
appear visible in hardware. The real configuration will be done by
vendorcode once we call sb_Before_Pci_Init().
Change-Id: I01a46c630aa6d55a94af45da6b78c97df7553e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8387
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This has nothing to do with SATA controller. We only need to
fill the table with defaults before we parse devicetree for
changes to device configuration.
Change-Id: Ic4b28b5992ec9bfdf252f61b1c86b0162243cc95
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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If devicetree.cb has GPP port off, really disable it before even
trying to do link training.
Change-Id: I810945da28d86768e88249dc4d29a50ad9f9959b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8385
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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A set of pins can be configured for GPIO or (parallel) PCI bridge use.
When requested configuration is 0:14.4 enabled, register programming
must be done before attempting to enumerate devices behind the bridge.
When requested configuration is 0:14.4 disabled, we must not even
temporarily enable pins for PCI use to avoid spurious GPIO state changes.
As our PCI subsystem currently does not configure visible PCI bridges
that are marked disabled, we cannot mark 0:14.4 disabled just yet but
need to handle pcengines/apu1 as a special case.
Drop related dead code.
Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8329
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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These sb800_enable() messages without newline mess up the log.
Change-Id: I1689b68702e08e2a287083835f310f52f495c451
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8384
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Kconfig variable is not implemented.
Change-Id: I546a1001847e7b1002f96baf49ed3301852a6894
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8345
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Keep the slower HyperTransport configuration for a possible reference
in fam15 boards.
Change-Id: Ifcdedc6385fec80f7d02c55c2aac10e5e2429a18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8344
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I098d1238cda16060c3566f242443007cdaf9bd82
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5106
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Probing is done by reading the ID register and comparing it to a known
value. When there is a mismatch, print an error.
Change-Id: I36fb1fe9b56e97660556dcb27be25bfe5129ad73
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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The actual key values were not added in commit 17ace8255.
TEST: amd/lamar shows the correct result.
Change-Id: I8f20e3d0ce83dd87b6c233ee98c3e77a6b7c1b03
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8375
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
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BUG=None
BRANCH=None
TEST=Compiles successfully for rush
Original-Change-Id: Ic8f5d91f6635ef12845ab049a20df5a6e33bbf55
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203142
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ecf7822812d8745af74eaf135b7b806c23ef51a2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I79abbded94376ba90a8c729aaf856ce303509e48
Reviewed-on: http://review.coreboot.org/8410
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
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This combines the Avalon and Bolton tables of text descriptions
of the IRQ assignments. It also corrects the text string for
the SD controller on Bolton.
Test: This was verified on amd/lamar.
Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8374
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Verstage isn't included yet, but we need to have
the Kconfig option for toolchain.inc to pass.
Change-Id: I7fae73cd3b77fd347398221489caf745274701eb
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8409
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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git submodules have some surprising behaviour, and we make full use
of it. Start building a canonical resource for that so developers
can spend their time on better things than on fighting git.
Change-Id: I5aa721e9b0acb2912a057858fd23a1d59d845ed1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/8371
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Ib83ec5c397fdef5aa9e3376f1c0072cfa2f74fa6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8425
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add two macros to gpio.h which allow to setup 20K
pull-up or pull-down resistor for a given GPIO.
Change-Id: Ie3bc4d40df588ed682cc692e2a80527b9e62a483
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8402
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Two source files were accidently marked executable. Switch them back to
mode 644 (rw-r---r--)
Change-Id: Ic96f6e5e9a05cbffb65cdfb627023d04d3866dc9
Signed-off-by: Stefan Reinauer <stepan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8426
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
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BUG=none
BRANCH=none
TEST=none
Change-Id: I56f357db6d37120772a03a1f7f84ce2a5b5620e9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/241855
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/8396
Tested-by: build bot (Jenkins)
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If one needs raw binary files, .bin extension cannot
be used due to settings in .gitignore. This patch
allows to use .hex files. To avoid lint checks on these
files, exclude the .hex extension from the test.
Change-Id: I4b503229d63694c48cce12ca8cd33ea58172af01
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8403
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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From git's point of view submodules are a weird third thing between file
and directory. Avoid trying to apply file handling on a directory.
Change-Id: Ibbc9c28e1657d96413c5fb08705d30e25171254d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/8372
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I1e4c5c807d4a78844a40083178b6f96ffeb3659e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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SeaVGABIOS supports both the coreboot linear framebuffer and native EGA
text mode. To use SeaBIOS interactively on standard VGA hardware a VBIOS
is needed; SeaVGABIOS is one such option.
TEST: Booted KFSN4-DRE with XGI Volari Z9s and SeaVGABIOS. Was able to
interact with SeaBIOS and comboot menu, then booted Linux successfully.
VGA display was continuously usable from power on to Linux login.
Change-Id: Id4bd4cb5cece9114457633832c5f0e5280c02b47
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8368
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: I92e6e7f1292f66642aa0336064a4eccba104dd08
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5101
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I32eccfb4eae176e0155c53efaf463258653eefc2
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8355
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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