coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-06-14	soc/amd/picasso: correct MCFG ACPI table	Aaron Durbin
2020-06-14	mb/google/volteer: Enable thermal sensor 4 in DPTF for volteer	Deepika Punyamurtula
2020-06-14	dptf: Introduce new paradigm for configuring DPTF parameters	Tim Wawrzynczak
2020-06-14	soc/intel/tigerlake: enable CPU_INTEL_COMMON	Alex Levin
2020-06-14	soc/amd/picasso: Increase SMM_RESERVED_SIZE	Marshall Dawson
2020-06-14	mb/google/puff: add MST and LSPCON details to devicetree	Shiyu Sun
2020-06-14	soc/intel/cannonlake/acpi: Capitalize hex number to unify with Skylake	Paul Menzel
2020-06-14	soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: add cpu entries in ssdt	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: fix MADT ACPI table	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: add IIO stack resources to DSDT	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: add NUMA ACPI tables	Jonathan Zhang
2020-06-14	util/board_status: Also check remotely retrieved coreboot console log	Paul Menzel
2020-06-14	mb/google/hatch/vr/puff: Set up PL2 and PsysPL2	Tim Chen
2020-06-14	mb/google/fizz: add variant chipset display init	Jeff Chase
2020-06-14	util/intelmetool: Add support for Intel Cannon Point LP HECI Controller	Matt DeVillier
2020-06-14	mb/google/dedede: Enable early EC software sync	Meera Ravindranath
2020-06-14	mb/google/dedede: Select Recovery Cache Kconfig option	Meera Ravindranath
2020-06-14	sb/intel/i82801ix: Fix SPDX license header	Kyösti Mälkki
2020-06-14	mb/google/hatch: Switch USB2 port1 and port3 on Noibat	Edward O'Callaghan
2020-06-14	soc/amd/picasso/acpi: Add a wrapper method WAL1 for calling ALIB function 1	Furquan Shaikh
2020-06-14	ec/google/chromeec: Call \PNOT () on initializing AC power state	Furquan Shaikh
2020-06-13	cpu/intel/car: Use symbols for CAR MTRR setup	Kyösti Mälkki
2020-06-13	arch/x86: Add symbols for CAR MTRRs in linker script	Kyösti Mälkki
2020-06-13	soc/intel/common: Introduce ASL2.0 syntax	Alexey Buyanov
2020-06-13	arch/x86: Include id.ld unconditionally in memlayout.ld	Furquan Shaikh
2020-06-13	arch/x86: Drop early_ram.ld	Furquan Shaikh
2020-06-13	soc/amd/picasso: Place early stages and data buffers at the bottom of DRAM	Furquan Shaikh
2020-06-13	util/cbfstool: Drop IS_TOP_ALIGNED_ADDRESS() check in cbfstool_convert_fsp	Furquan Shaikh
2020-06-13	cbmem_id: Add CBMEM ID for early DRAM usage	Furquan Shaikh
2020-06-13	soc/amd/picasso: Add custom memlayout.ld file	Furquan Shaikh
2020-06-13	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	Furquan Shaikh
2020-06-13	mb/google/zork: update DRAM SPD table for vilboz	Paul Ma
2020-06-12	mb/google/volteer/var/voxel: Add memory parts and generate DRAM IDs	Furquan Shaikh
2020-06-12	tests: Add some basic warnings and fix resulting issues	Julius Werner
2020-06-12	vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197	Srinidhi N Kaushik
2020-06-12	mb/google/volteer: Customize PCH VR settings for better Sx power savings	Venkata Krishna Nimmagadda
2020-06-12	soc/intel/tigerlake: Add devicetree support to change PCH VR settings	Venkata Krishna Nimmagadda
2020-06-12	mb/google/dedede: Add new variant boten	Peichao Wang
2020-06-12	nb/intel/i945/rcven.c: Correct comment	Angel Pons
2020-06-12	nb/intel/i945: Clean up raminit coding style	Angel Pons
2020-06-12	mb/google/hatch: Remove unused USB2 port from Noibat	Edward O'Callaghan
2020-06-12	soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run	Furquan Shaikh
2020-06-12	sb/intel/i82801ix: Use PCI bitwise ops	Angel Pons
2020-06-12	mb/google/puff: Update i2c[2] and i2c[3] rise and fall times	Sam McNally
2020-06-12	sb/intel/i82801jx: Use PCI bitwise ops	Angel Pons
2020-06-11	soc/amd/picasso/uart: fix possible out of bounds access	Felix Held
2020-06-11	vc/amd/fsp/platform_descriptors: drop prefix from PCIe/DDI structs	Felix Held
2020-06-11	mb/google/dedede: Add new variant drawcia	Wisley Chen
2020-06-11	mb/google/volteer: Update DPTF TSR2 sensor ID for volteer	Deepika Punyamurtula