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2011-09-12Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methodsTobias Diedrich
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2 uses the same acpi wakeup vector as S3. Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink the power LED while sleeping. acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because it is used in both romstage and ramstage after patch 3/3, whereas i82371eb_early_pm.c is used only in romstage. I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early because I think acpi_is_wakeup_early is a bit misleading as a name since it doesn't return a boolean value. Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the added check for acpi_slp_type == 2 (resume from S2) should not change behaviour of other boards: northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type; northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0; northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3; northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0; southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/188 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-12Miscellaneous AMD F14 warning fixesefdesign98
This commit adds in some more fixes to AMD F14 compile warnings. The change in the mtrr.c file is in prep- aration for changes yet to com, but it is currently innocuous. Change-Id: I6b204fe0af16a97d982f46f0dfeaccc4b8eb883e Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/133 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-09Replace while with do; while to avoid repetitionNoe Rubinstein
Cosmetic only; replaces some 'while' loops with 'do; while' loops to avoid repetition. Replacement performed by the Ruby expression: t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/, "\\1do \\2\n\\1\\3;") Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/183 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09Crank up CPU speed on Intel Core and Core2 CPUsPatrick Georgi
The CPUs start on their slowest speed, and were left that way by coreboot. This change will speed up coreboot a bit, as well as systems that don't change the clock for whatever reason. Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/176 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09Report GSE chipset and warn if the code has been compiled for the wrong chipset.Stefan Reinauer
It would be nicer to unify the code so that it does all detection at runtime instead of compile time (but that would also significantly increase code size) so if someone else wants to give it a shot... Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/184 Tested-by: build bot (Jenkins)
2011-09-07Add support utils for tracingRudolf Marek
Following patch adds a userspace util genprof which is able to convert the console printed traces to gmon.out file used by gprof & friends. The log2dress will replace the adresses in logfile with a line numbers. Change-Id: I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/179 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07Add support for the tracing infastructure in coreboot.Rudolf Marek
The compiler is forced to emmit special functions on every entry/exit of the function. Add a compile time option to support it. Function entries will be printed in the console. The CONFIG_TRACE has more documentation. Patch for userspace tools will follow. Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/178 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07AMD F14 Rev C0 updateKerry She
Add AMD Family14 Rev C0 cpu id Change-Id: Iacd1c7b20e889da61a2085188766285f27e5c018 Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/160 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07AMD SB800 southbridge updateKerry She
This patch enables access to the registers of the hardware monitor logical device in the superio via isa ports 0x295/0x296. Previously this was not enabled in the SB8xx LPC device. This is required for initialisation in init_hwm() in src/superio/winbond/w83627hf/superio.c and also by OS-level sensor monitoring such as lm-sensors to access temperature, fan monitoring and control and voltage registers. asrock/e350m1 and advansus/a785e-i mainboard changes are included herein. Change-Id: I2176885549277b335c0c41b48457d09b9b76b703 Signed-off-by: Per Hansen <perh52@runbox.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/159 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07AMD F14 southbridge updateKerry She
This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein. Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-04Adjust some code/comment of sb700 sata initWang Qing Pei
The inline comment of sata_init function seems not placed correctly. Rearrange it. Change-Id: I63480da60e51cdc68e64c302ad2d8a6197e288f6 Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/186 Tested-by: build bot (Jenkins)
2011-09-04Disable dev3 on ma78gm-us2hWang Qing Pei
Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot. Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/187 Tested-by: build bot (Jenkins)
2011-08-29buildgcc: Do not download GDB source code if run with --skip-gdbPeter Stuge
Change-Id: Ida3680418fdd3136752d51cc19f3e14111c12131 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/175 Tested-by: build bot (Jenkins)
2011-08-27Add a few more patterns to .gitignoreSven Schnelle
Change-Id: If7c1c6d9a96dd788bacee72b6e18a435069cad6e Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/172 Tested-by: build bot (Jenkins)
2011-08-27Add dirty flag to git describeSven Schnelle
git describe knows --dirty, which adds -dirty to the verion number if the tree contains uncommited changes. We should add this flag to make it obvious that the COREBOOT_VERSION might be misleading. This is especially important as this version number is now used in the SMBIOS data structures. Change-Id: If4c608c7455e1bbf0cc530c6299fa00eb0fe4d58 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/173 Tested-by: build bot (Jenkins)
2011-08-26X60/T60: remove obsolete dmi.hSven Schnelle
Change-Id: Id0e8bcc1b93a629f0620b84a060d7ff99a82de78 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/174 Tested-by: build bot (Jenkins)
2011-08-26Add automatic SMBIOS table generationSven Schnelle
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/152 Tested-by: build bot (Jenkins)
2011-08-25Minor ma785gmt clean-upAlec Ari
Change-Id: I9e889a6c475fb3283fa11f8b3de5baaf54235589 Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/167 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-25Fix up various dsdt.asl filesAlec Ari
Change-Id: I46eb27847deb3a903ac9af347992a9954e50ff6e Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/166 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-24Remove dead codeAlec Ari
Remove dead code, copy and pasted from tilapia's mainboard.c file into various asus mainboard.c files Change-Id: Ic715ccaad8ac0210401d4a99ecb11e943f6afe58 Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/168 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-21buildgcc: Remove all bashisms, making the script run also on BSDPeter Stuge
Use sed instead of ${variable:start:length} and ${#variable} Use single = in string comparisons Use `eval echo '$'$variable` instead of ${!variable} Use > file 2>&1 instead of &> file Use readlink -f to expand the path of GCC configure Change-Id: Idc7dfcea3922f55630a6855acdb19e36582708bd Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/165 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-08-21Use git describe to set KERNELVERSIONPeter Stuge
Change-Id: Id579b19fc38c7ca2b98ad1e87aaec71c070a9178 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/163 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-21buildgcc: Fix typo in check for failed iasl buildPeter Stuge
Change-Id: I3e90b90e807ae775ac66af160a0f8547dcb3597a Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/164 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-19Lenovo H8: Always clear audio muteSven Schnelle
The mute bit is set by ACPI before poweroff/going to suspend. So clear it after resume, to have working volume control even if the ACPI doesn't clear it on resume. OSPM should control Audio mute with ec bit 0x30:6, so it is safe to clear this bit even if the user has audio muted. Change-Id: I18bebe532bf21cfb61b3d294a396bf15012f9f1a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/162 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2011-08-18libpayload: export get_cbfs_header()Patrick Georgi
Keep in sync with coreboot's version. Change-Id: I8a253446bd3b2ce9d05c6076a3f49f0260ecd5f9 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/158 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-18X60: use EC events 0x50/0x58 instead of GPIO GPE for Docking/UndockingSven Schnelle
Change-Id: I674e5166f5fb7ba299e6f1231f30434a5bf731c5 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/161 Tested-by: build bot (Jenkins)
2011-08-18export get_cbfs_header()Sven Schnelle
Change-Id: I4b6afcee3d0d169e03165a7fb48cfaef2e8253e2 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/157 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-17libpayload: Some more compatibility (for flashrom)Patrick Georgi
libpci defines an arbitrary set of PCI vendor IDs, flashrom uses the Intel definition. Add it. flashrom also requires inttypes.h, so add the OpenBSD version Change-Id: I9bffd8193f635c375ac4d6b6eae8d3d876b95f5f Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/154 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-16libpayload: EHCI registers are volatilePatrick Georgi
Some gcc versions seem to honor volatile at different places in a struct declaration. Change-Id: I0df2a3fb2eff4cee8cc1b8ac15d9cd9b86178752 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/155 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-14crossgcc: invoke buildgcc with bash, instead of relying on #!/bin/bashJonathan A. Kollasch
Change-Id: I09192e57e2535b2f8f98cabeb755f10c5520c499 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/151 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-08-12buildgcc: improve portabilityJonathan A. Kollasch
`cp --remove-destination` isn't as portable as `rm -f` and `cp`. Change-Id: Ib05bfc121f7a0b467f8104920e14fbd02191585f Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/150 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-10Add iasl to buldgcc and rev the version.Marc Jones
Change-Id: If9144cdf088f16bc3974a1784a442a1fd12ac75b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/147 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-09Do not compile nuvoton superio for all boardAlexandru Gagniuc
The nuvoton WPCM450 code is compiled for all boards regardless of whether or not they use it. Compile it only for boards needing it. Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/129 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-09AMD Family 14 Agesa warning fixefdesign98
This change fixes one Agesa warning. Originally this commit included some changes that I later deemed unnecessary. Change-Id: I31ad13bb92509228b89921561c340c95e5136370 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/132 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-06ms7135: add ACPI supportJonathan A. Kollasch
Change-Id: I64a74d3dc0ea2d006ed4b25657d531fb243c2993 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-06Update AMD F14 Agesa to support Rev C0 cpusefdesign98
This change updates the AMD Agesa code to support the Family 14 rev C0 cpus. It also fixes (again) a ton of warnings, although not all of them are gone. The warning fixes affect code in the Family 12 tree as well, so there are some small changes therein. This code has been tested on a Persimmon and passes Abuild. This is the first (and largest) of a number of commits to complete the upgrade. Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/131 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-04Add voltage control of southbridge and RAM on ms7135Jonathan A. Kollasch
Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04northbridge/intel/i440bx: Registered SDRAM modules support and fixesKeith Hui
Adds support for initializing registered SDRAM modules on Intel 440BX northbridge. Drops unneeded romcc-inspired programming tricks. Only set nbxecc flags (see 440BX datasheet, page 3-16) when a non-ECC module has been detected in a row via SPD; also drops an unneeded intermediate variable used in setting them. Boot tested on ASUS P2B-LS with regular and registered ECC SDRAM under Linux and memtest86+. Change-Id: Idc99d49567cca55f819d6b0e98952b1c3256498a Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04libpayload: Add liblzma, libcbfsPatrick Georgi
Add cbfs core from coreboot into libpayload, and to support lzma decode, add coreboot's lzma code, too. Carl-Daniel agreed to relicense the lzmadecode wrapper as BSD-l, solving licensing problems. Change-Id: Id28990fe7e951d99447e265a4880d70a8f208dd2 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/115 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-04split CBFS support into shared core and extended functionsPatrick Georgi
The core is data structures and basic file finding capabilities, while option ROM handling, and loading stages and payloads is "extended". The core is rewritten to be BSD-l (its header already was), so can be copied to libpayload verbatim. It's also more robust in finding files in corrupted images, eg. after partial erase or update. Change-Id: Ic6923debf8bdf3c67c75746d3b31f3addab3dd74 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/114 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04libpayload: Add PDCurses and ncurses' libform/libmenuPatrick Georgi
PDCurses provides an alternative implementation of the curses library standard in addition to tinycurses. Where tinycurses is really tiny, PDCurses is more complete and provides virtually unlimited windows and the full API. The PDCurses code is brought in "vanilla", with all local changes residing in curses/pdcurses-backend/ In addition to a curses library, this change also provides libpanel (as part of the PDCurses code), and libform and libmenu which were derived from ncurses-5.9. As they rely on ncurses internals (and PDCurses is not ncurses), more changes were required for these libraries to work. The build system is extended to install the right set of header files depending on the selected curses implementation. Change-Id: I9e5b920f94b6510da01da2f656196a993170d1c5 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/106 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
Bring from coreboot v1 support for initializing L2 cache on Slot 1 Pentium II/III CPUs, code names Klamath, Deschutes and Katmai. Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with Pentium III 600MHz, Katmai core. Also add missing include of model_68x in slot_1, to address a similar problem fixed for model_6bx by r5945. Also change Deschutes CPU init sequence to match Katmai. Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-03Remove debugging code, or convert it to be selected by kconfigJonathan A. Kollasch
Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/130 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-03Use preferred style of fixed-width integer typesJonathan A. Kollasch
Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/125 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-26crossgcc: update w32apiPatrick Georgi
crossgcc also needs lzma support as w32api is distributed in .tar.lzma Change-Id: Ia1938fa30262fe0c8bd655a08f9dc731a02e46ba Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/120 Tested-by: build bot (Jenkins)
2011-07-26buildgcc: Break if parts of the toolchain are missingPatrick Georgi
We test for the presence of a couple of tools and even print an error. But the tool didn't stop there. Change-Id: I40dcf7894408ea7b24d5f68c76df4b7541f469bd Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/111 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Add xhcbios and ahcibios rom handlingefdesign98
This change adds xhci and ahci bios rom handling that is similar to the vgabios rom handling in the arch/x86 Makefile.inc to the Persimmon and Torpedo mainboards. It also adds the basis for AHCI BIOS rom handling to the Persimmon Kconfig. Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/109 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Add the SuperMicro H8QGI platformefdesign98
This set adds support for the SuperMicro H8QGI mainboard. It is a publicly available 4 socket board using AMD Family 10 cpus and AMD SR5650 and SB700 bridges. Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/108 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Add SSE3 dependent codeefdesign98
This change separates out changes that were initially found in the commit for XHCI and AHCI changes to "arch/x86/Makefile. inc". It also corrects a comment. The SSE3 dependent code adds a pair of CR4 access functions and a blob of code that re-sets CR4.OSFXSR and CR4.OSXMMEXCPT. Change-Id: Id97256978da81589d97dcae97981a049101b5258 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/113 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-22Update AMD SR5650 and SB700efdesign98
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
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