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2015-03-21libpayload arm64: Remove tight-coupling with any particular ELFurquan Shaikh
Allow more flexibility by reading and writing to system registers at current EL. Instead of specifying what _ELx register to write to, code can specify _current. BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles and boots to kernel on ryu Change-Id: Id38b675bfe67ca1e25f8c268192114e3f0bee800 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6d4d07e26fc964dc3aaebfe03db59596d90093e9 Original-Change-Id: Ic1d9e18e6fc016a04f17621a148e62d6cbd04ce7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214577 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8785 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add library helpersFurquan Shaikh
Add library helpers to access standard arm64 registers. This library also provides functions to directly read/write register based on current el. So, rest of the code doesnt need to keep checking the el and call appropriate function based on that. BUG=chrome-os-partner:31634 BRANCH=None TEST=Libpayload and depthcharge compile successfully for ryu Change-Id: Ibc0ca49f158362d4b7ab2045bf0fbd58ada79360 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2ca6da580cb51b4c23abdaf04fee2785e5780510 Original-Change-Id: I9b63e04aa26a98bbeb34fdef634776d49454ca8d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214575 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8784 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Make exceptions workFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=test_exc generates and handles exceptions properly Change-Id: If3ecab93be6d02942b52960ec97edc687bedf64b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bba2caae0bd436ba9e5215f5d8606ce8c4987c98 Original-Change-Id: I4abe8a0e426eab2532852179dbb32505353cd0a1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214609 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Initialize exception stackFurquan Shaikh
Initialize exception stack to be able to handle exceptions properly BUG=chrome-os-partner:31634 BRANCH=None TEST=test_exc successfully generates and handles exceptions on ryu Change-Id: I19163fae080b9ac3297a7ffe404446e427bf9a1c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99157687c5178c3b3eb79f5589343db1b2b4cc86 Original-Change-Id: I4dc83ff32c1665e22127bf0b1e6d4c6b45c07a4a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214608 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8782 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add console_init to enable console logsFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles sucessfully and hello libpayload seen on screen Change-Id: If312e005e306f7f70138aa27d2ef5b39620ec91e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6d6aa84d7255d33e085f12c609f32309521ff58e Original-Change-Id: I73f888a7b8aa0065c1ca0bf7857c445cc5678cdc Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214073 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8781 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: arch/mips: add virt/bus/phy_to_bus/phy/virt operationsIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA and bring up board; works as expected BRANCH=none Change-Id: I368494f388b82969dda0ce73a38824791efce616 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e4c2bbcbdbcf706062724cffe2d5f15953468ace Original-Change-Id: Id5c9b1d65c6ec87f2aba06995dc940c50afb041f Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245386 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: mips: add SOC CPU frequencyIonela Voinescu
Add CPU frequency corresponding to SOC. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I05458070a15c6cf1ef0fc2104715a63902a38887 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: mips: correct platform IDIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I8e5ac80e95b5169102eaa075bc22045c0789d486 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8745 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: pistachio: fix timer implementationIonela Voinescu
timer_raw_value must return the number of CPU ticks, and not the time obtained by dividing the ticks by the CPU frequency. The CPU counter is increased at every 2 CPU clocks and therfore the number of ticks will be the counter value multiplied by 2. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA; it works properly. BRANCH=none Change-Id: Iae62cb328e882f84822250bdf72146321ca9bbe0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7ab25ce7dcaffb453ee774d870963a56444d46af Original-Change-Id: I74408950900463a2c054d5aebd3edb005a325adb Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242393 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8744 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: mips: add memcmp to the MIPS string functionsIonela Voinescu
The default string functions work with multiple of 4 bytes (sizeof(unsinged long)); MIPS will use LW/SW instructions for these operations and if the source and destination addresses are not aligned it will trigger an exception. Therefore, this implementation does all data access operations per byte, because there is no guarantee that the provided strings are properly aligned. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected BRANCH=none Change-Id: I05b43673deb954f022d12cb9c3d7baac26be2a34 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e13b3d31726404abd8c8e5c8780d3d3e16e032d Original-Change-Id: I456e312eb6b7fee2eff10e461af7f578aed07648 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241885 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: arch/mips: Add basic MIPS architecture supportIonela Voinescu
Add the basic build infrastructure and architectural support required to build for targets using the MIPS architecture. This will require the addition of cache maintenance. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA with Depthcharge as payload; successfully executed payload. BRANCH=none Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf Original-Reviewed-on: https://chromium-review.googlesource.com/219740 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8741 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: cbfs: Fix ram_media map() error return valueJulius Werner
The correct return value for errors on a cbfs_media->map() call is CBFS_MEDIA_INVALID_MAP_ADDRESS, not NULL. Not sure if that's the best choice (since 0xffffffff is probably a more likely valid address than 0 there), but that's what the upper layers expect right now. BRANCH=veyron BUG=None TEST=Press CTRL+L with an RW_LEGACY section filled with 0xff. Observe how cbfs_get_header() returns failure without doing a bunch of NULL pointer accesses first (not that those have any visible effect on Veyron, but that's another problem...) Change-Id: I3d012fc9af9da6e01159990a6bdd62c38fc22329 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a609e17bb9b0ef4d3a833f72fa4fbfd8e8cb0ab Original-Change-Id: I0793434116a8c568e19fe0dee24f13942fc50f25 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238991 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/8758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: Add RAM code to sysinfo_tDavid Hendricks
This adds CB_TAG_RAM_CODE and an entry to sysinfo_t. BUG=chrome-os-partner:31728 BRANCH=none TEST=Built and booted on pinky w/ depthcharge patch and saw that /proc/device-tree/firmware/coreboot/ram-code contains correct value Change-Id: I35ee1bcdc77bc6d4d24c1e804aefdbbfaa3875a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca6d044f2e719ded1d78a5ab3d923e06c3b88d6b Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I69ee1fc7bc09c9d1c387efe2d171c57e62cfaf3f Original-Reviewed-on: https://chromium-review.googlesource.com/231132 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8755 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: Add support for parsing RAMOOPS range from corebootFurquan Shaikh
CQ-DEPEND=CL:228856 BUG=chrome-os-partner:33676 BRANCH=None TEST=Compiles and boots to kernel prompt. ramoops console log verified after causing kernel to fault. Change-Id: I5af9b995113ee30ac60347acba8fa945fb5cd17a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 80c843fc78b137eb5540f8fefc4a69545b896fb6 Original-Change-Id: I8886015977e1fd999ef74fe73d08cff935cbce5c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228742 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8754 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: make wifi calibration table available through sysinfoVadim Bendebury
The WiFi calibration blob saved in the CBMEM by coreboot needs to be visible by depthcharge to supply it to the kernel. BRANCH=storm BUG=chrome-os-partner:32611 TEST=none yet Change-Id: I43a857f073a47ca315d400df4c53d5eb38e91601 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46a649608e6740e07c562c722fadd8c64e264b5f Original-Change-Id: Iecd8739c9269b58064b3c3275f5376cebcd6804b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225506 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8753 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21chromeec: provide proto v3 over i2c supportAaron Durbin
Certain boards need to speak proto v3 over i2c. Leverage the transport agnostic API to share the logic with other proto v3 impelementations. BUG=chrome-os-partner:31148 BRANCH=None TEST=Built and ran on ryu. Can talk to the EC successfully. Change-Id: I1d0cd6907057af4ded3c4460193bbe1d897a1db7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb9ac965ad04c9491f40fd9aa595176a28a467b3 Original-Change-Id: Ib699120fd232392e8caa0889c2bf40f4587a8a35 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211139 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21chromeec: allow transport implementation to provide buffers for proto v3Aaron Durbin
Depending on the transport mechanism for proto v3 different bytes need to be send and/or read before the request and response. Depending on the software and/or controller interface that requirement leads to needing to copy data into temporary buffers. Avoid this by allowing the transport mechanism to provide the request and response buffers. BUG=chrome-os-partner:31148 BRANCH=None TEST=Built for rush and ryu. Ran on ryu with i2c implementation. Also built for rambi to check x86 systems. Change-Id: I35d4d69bd1fa900fc0cfe3822496f381405bdcb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c7224426e1d0bcf06ed010131a2462a6ca201d8b Original-Change-Id: Iad6cce566a253ca72e6f5009a97235ece0a6c1b5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211138 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8827 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21chromeec: correct response length for VBNV writeAaron Durbin
The EC doesn't return any data when one performs a write to VBNV context. Therefore there is a mismatch of expectations. Correct this by properly setting the expected response length. BUG=chrome-os-partner:31148 BRANCH=None TEST=No longer hanging while writing to VBNV on ryu. Change-Id: I7077a507c3280358dac1f88ece62cacee9b71bea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c1735c3377163aeb9e90155cb9f081a1eea919c9 Original-Change-Id: I455724f20f5442bd62a792f09273227417475f07 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211137 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8826 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add function to get coreboot table ptrFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: If89e7a537e6f0321ef43641c924a8ef057f51147 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f39cdbf68b674ef9b65441038ec79548145a88d Original-Change-Id: Ie9904bf8abfa5ce1d87a586e5b08eb320793942f Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217821 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8790 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21cbmem: stop assuming 1MiB of memory can be mappedAaron Durbin
The default mapping size is 1MiB of ram. However, not all systems allow 1MiB of memory to mapped depending on the kernel's memory map. Therefore, be explicit about the sizes to mmap(). The only path that wasn't cleaned up was the coverage path as that needs to handle dynamic cbmem. The correct way to fix that is to add a global like the timestamps that is set while parsing cbtable. BUG=chrome-os-partner:31355 BRANCH=None TEST=Can cbmem -ltc on ryu. Change-Id: I548afa5ddbe0a859f52bc2ab2d0931186ee378a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: df4991ce1da7f0c25e99d84222cbc8d3189d0d66 Original-Change-Id: I27b70ae8a8fba168d1c1829bbef0135c7b651eac Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221971 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21arm: add _end symbol to bootblock.ldAaron Durbin
It's helpful to view program size by inspecting the symbols. _start and _end exist on romstage and ramstage. In order to be consistent add _end for bootblock too. BUG=None BRANCH=None TEST=Built and noted bootblock has _end symbol. Change-Id: I06634b317e957e8271bf32530a56b5541c79b9ee Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b4ac926b30749d22e90a6f12ebac52107e241526 Original-Change-Id: I7f0b4dd4078c7d23c70949563b4c3f4df9e66142 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210832 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8824 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21cbfs: change 1 message level to WARNING if cbfs can't find specific dataKane Chen
In some cases, we need to use 1 common VGA device ID to share among different VGA devices. But it will show error when it can't find a specific pci rom by PCI DID. in fact, it will find the pci rom with common vga ID. Without this commit, you may need to skip error check during suspend_stress_test BUG=none BRANCH=none TEST=build OK, and check no error on Auron and Samus Change-Id: I2b18347e46c831038f048cfd0b065430c72c6f30 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c32ee21b4c942182e5ffb21b58b93fa7c082223 Original-Change-Id: Ib743e960f772b7e2e73a1feb80790a13bd8c06c7 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217415 Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: http://review.coreboot.org/8821 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21superio: ite8772f: Exit extemp busy stateRyan Lin
It causes fan top speed due to this bug + our board-specific workaround, and causes invalid temperature sensor readings. Therefore, re-configure the register "External Temperature Sensor Host Control Register" to terminate processes when this issue happens. BUG=chromium:402204 TEST=ran suspend_stress_test 500 times Change-Id: I439d5de798fbe999e4eec5497e6969b7b453121b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b82f2922c7fce3ca6b2797a8d9775e9db2817fe9 Original-Change-Id: I6e71b6a46a31b00e541c304f1ed58c1678c1d42e Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219445 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/8820 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21ARM64 rmodule: Add new reloc type R_AARCH64_LDST8_ABS_LO12_NCFurquan Shaikh
BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: Id7b0dfb5a51c2f29bdb031b98606940c118959ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a1c4d2f35c135d542708c4dabcca5e8c1d453c0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: If132323885f23d75e1fcde064398e85c2c17f257 Original-Reviewed-on: https://chromium-review.googlesource.com/231560 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8809 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21cbfstool: Remove empty line that looks out of placeJulius Werner
BRANCH=None BUG=None TEST=Manual Change-Id: I8b31a0b194d353ea3e7863513f2e36f3e032fad8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7ccba49a7c2372cdfff6e2947e417d4d4f5436c2 Original-Change-Id: I9beebdf29e4fc4aa645581146fdc61c659de72df Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229973 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/8808 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21rmodtool: add another aarch64 relocationAaron Durbin
BUG=chrome-os-partner:32112 BRANCH=None TEST=Built secmon which had this type of relocation. Change-Id: Ie367c348fbf59465e238e5fa60f217f5373501b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a754bc1fe39c19ab8b2f7be9648cccb06156b0ef Original-Change-Id: If170d9e270daf3153e92d16c06516915c727e930 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218843 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8807 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21rmodtool: Add support for aarch64Furquan Shaikh
BUG=chrome-os-partner:31615 BRANCH=None TEST=Compiles succesfully, rmodule created and loaded for ryu Change-Id: Icc80b845fe43a012665d77c3ef55bd30784fd3fc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24ad4383a9ea75ba6beb084451b74e8a8735085b Original-Change-Id: I4f3a5dbb8fc8150aa670d2e6fed56a6774feb4a6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214329 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8806 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21mainboards/amd/fam10: Add romstage timestampsTimothy Pearson
Example output: 1:start of rom stage 542 2:before ram initialization 193,989 (193,447) 3:after ram initialization 3,319,114 (3,125,124) 4:end of romstage 3,320,004 (889) Change-Id: Idcde7dc4c7a1d6c3118c82b67e8c2fcd4a07553b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8776 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-21x86: fix romstage_null.debug link w/o --gc-sectionsAaron Durbin
When adding gargabe collection to x86 the --gc-sections flags was inadvertently missed when linking romstage_null.debug. Fix this omission. Change-Id: I7d2700755afa78459c6f8707303a0e64936a1a9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8850 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-21libpayload ehci: Use 64-byte aligned data structures for periodic transfersJim Lin
Chapter 3.1 "Periodic Frame List" of EHCI 1.0 specification says "Frame List Link pointers always reference memory objects that are 32-byte aligned." jwerner@chromium.org suggests setting it to be 64-byte aligned for consistency with other EHCI queue structures. BUG=chrome-os-partner:31993 TEST=Tested on nyan platform. Before adding patch, USB keyboard behind an external hub is not working to switch between "Default Locale" and "English" (after pressing ESC+REFRESH+POWER on embedded keyboard and later Left/Right-Arrow key on USB keyboard). Change-Id: Ie6259f2df20ae2618c2074e831fad087f227091d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23fc02e6ba3b17be4eaf18810ec6fc0d9c0e0b9a Original-Change-Id: If52ddc43ebd5d509c19f104928dced5bd09b1706 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218403 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8738 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: EHCI: Fix transaction error for interrupt transferJim Lin
Data toggle should be running like 0, 1, 0, 1, ... In the failed case (where a low-speed USB keyboard or km232 device is installed), data toggle will be running as 0, 1, 0, 1, ..., 1, 1. Therefore causing Halted or Transaction Error bit to be set in qTD Status field. BUG=None BRANCH=None TEST=Tested on nyan_kitty platform, firmware-kitty-5771.61.B branch. Attached USB keyboard or km232 device to root-hub port (same side as SD card slot). Made sure no transaction error after doing interrupt transfer. Change-Id: I576f3c583dae4c279a6e0e8ffdfce5abe463277d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64b0428aaab869e20f6720669e953acf82ecb846 Original-Change-Id: Ic2c0f95cff2ae6e314967b0b82231a962255f1a7 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233857 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8747 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: provide basic 64bit division implementationVadim Bendebury
These functions are usually provided by gcc lib, which is not supposed to be included on embedded platforms. This patch adds a no thrills C implementation. Other than MIPS platforms are happy using the gcc library provided implementation, but in case of Chrome OS MIPS toolchain the libraries are compiled with the small GOT, such that the entire data segment does not fit. With this implementation mips, arm and x86 targets build fine. BRANCH=none BUG=chrome-os-partner:31438 TEST=checked the logic by incorporating this code into a C file and running a loop continuously comparing random inputs' division and left and right shift results. The test ran for extended periods of time without failure. Change-Id: I468acd2fdbcdd493a76758a394e79cad35f9535a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2cc5f8668dd2609408af8da5a74c5a3d063fc0d3 Original-Change-Id: Ib46616d7eb0b2b497199270057514f730bb1cb0b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20Kconfig: Add MAX_REBOOT_CNT descriptionTimothy Pearson
Change-Id: Ie28812a84bd063d097e23294b8588f974a3a19e9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8725 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20bootblocks: use run_romstage()Aaron Durbin
Instead of sprinkling the cbfs calls around (as well as getting return values incorrect) use the common run_romstage() to perform the necessary work to load and run romstage. Change-Id: Id59f47febf5122cb3ee60f9741cfb58cb60ccab5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20romstages: use common run_ramstage()Aaron Durbin
Instead of sprinkling the cbfs calls around (as well as getting return values incorrect) use the common run_ramstage() to perform the necessary work to load and run ramstage. Change-Id: I37b1e94be36ef7a43efe65b2db110742fa105169 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8710 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20loaders: add run_romstage() function to bootblockAaron Durbin
Provide a common run_romstage() function to be used by bootblocks to load and run romstage. This is similar to run_ramstage() in that it provides a single entry point for doing the necessary work of loading and running romstage. Change-Id: Ia9643cc091f97a836cf5caefdff8df4a3443df4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8709 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20qemu-riscv: add preram_cbmem_consoleAaron Durbin
Miraculously a console is being compiled in for romstage. However, as no calls were potentially printing to the preram console this was being ignored. Instead provide the symbol required so as not to fail the build. Change-Id: Id8f0b6e6d15b41fa7fe1b63bf2d91f15baa0edda Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20loaders: add program_loading.h header fileAaron Durbin
Instead of two headers for payload and ramstage loading combine the 2 files into one. This also allows for easier refactoring by keeping header files consistent. Change-Id: I4a6dffb78ad84c78e6e96c886d361413f9b4a17d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8708 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20verstage should include the CBFS SPI wrapper, when configuredVadim Bendebury
Vboot2 targets so far did not have COMMON_CBFS_SPI_WRAPPER configuration option enabled, so the verstage is missing the relevant files in some Makefiles. This patch fixes the problem. BRANCH=none BUG=none TEST=with the rest of the patches applied cosmos target builds fine with COMMON_CBFS_SPI_WRAPPER enabled Change-Id: I3ce78c8afc5f7d8ce822bbf8dd789c0c2ba4b99c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b72693c96f7d8ce94ce6fe12b316d5b88fded579 Original-Change-Id: Iab813b9f5b0156c45b007fe175500ef0de50e65c Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223751 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8772 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi: Add GigaDevice GD25LQ64C/GD25LB64C SPI ROM supportMarc Jones
GD25LQ64C and GD25LB64C have the same ID and settings. BUG=chrome-os-partner:25907 BRANCH=baytrail TEST=Boot with GD25LQ64 and check MRC data save/restore works. Change-Id: I8a4aa7cabd9a7657c2f0bae255a87341db3f1061 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20b5896adbbbdedcb1b7de435466dcc6bfa703cb Original-Change-Id: I86d1e69552b6000faa9e0523356e27d7e2a6a6db Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193238 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8770 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi: do not use malloc in Gigadevice driverDavid Hendricks
This allows us to use the driver before ramstage. BRANCH=none BUG=none TEST=built and booted on Pinky Change-Id: I0700388b0e4e0562e3c0a52863c8357097bfd8d6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd57587dab74de509d5c50cfc1ad337d765af6c8 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I0ce901331e401274254b8889484ffb41359119fa Original-Reviewed-on: https://chromium-review.googlesource.com/235864 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8774 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20spi: do not use malloc in Winbond driverVadim Bendebury
When the driver is included in bootblock, malloc() is not available. Come to think of it, it is perfectly fine to use a statically allocated structure for the SPI device descriptor - coreboot is unlikely to require concurrent support of multiple SPI devices of the same kind. BRANCH=none BUG=chrome-os-partner:31438 TEST=bootblock on the FPGA board recognizes the installed Winbond device: coreboot-4.0 bootblock Tue Nov 11 07:27:24 PST 2014 starting... SF: Detected W25Q16 with page size 1000, total 200000 Change-Id: Iea1936a219d38848580a10f75eb8bbcab17e6507 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b4082442aa526d387a80cb5872d78670e6b468b Original-Change-Id: Iaa69d610ef18e69b1ae5ade2d958f9fe1595a723 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228959 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8771 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi_flash: add support for S25FL116KDaisuke Nojiri
S25FL116K family uses the first 3 bytes in response to a legacy identification command (9f) while previously supported models use the last 4 bytes. This change defines identify functions to allow both types to be handled correctly. BUG=none BRANCH=tot TEST=verified romstage is loaded on cosmos development board. Change-Id: I1970a9af17e81299fada5029724d405de4022156 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 65ff436db2355cb68a766a3dedbcd7e2f765e6db Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Icdd2645e356652672c4482e7b805da1bc0f21e71 Original-Reviewed-on: https://chromium-review.googlesource.com/234431 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20libpayload: move MRC processing to x86 path and remove ACPI_GNVS duplicationVadim Bendebury
It turns out that CB_TAG_ACPI_GNVS is handled in both x86 specific and common coreboot table parsing code. The MRC cache case used only by x86 is handled in the common code. This patch restores sanity and moves processing to where it belongs. BRANCH=none BUG=none TEST=verified that arm and x86 targets build. Change-Id: Iaddaa3380725be6d08a51a96c68b70522531bafe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0afae893d5027026cb666cd46e054aeae4e71f83 Original-Change-Id: I2c114a8469455002c51593cb8be80585925969a7 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225457 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20libpayload: cros: include mac addresses in coreboot tableVadim Bendebury
Pass MAC addresses found in coreboot table into lib_sysinfo. BUG=chrome-os-partner:32152 TEST=with all changes in place MAC addresses are properly inserted into the kernel device tree. Change-Id: I6b13c1c2c246362256abce3efa4a97b355647ef8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e2fe74f86b4ed43eb8a3c9d99055afc5d6fb7b78 Original-Change-Id: I1d0bd437fb27fabd14b9ba1fb5415586cd8847bb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219444 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20libpayload: Consolidate coreboot table parsingVadim Bendebury
There are three instances of coreboot.c in libpayload. for x86, arm and arm64 architectures. The arm and arm64 instances are exactly the same. The differences with the x86 instance are as follows: - a very slightly different set of coreboot table tags is parsed (one tag added and two removed) - instead of checking a fixed address if it contains the coreboot table, the x86 version iterates over two address ranges. This patch refactors the module, leaving architecture specific processing in arch subdirectories and moving the common code into libc. BUG=none TEST=none yet Change-Id: I1c7ad6f74e3498e93df78086ba0ff708c08e0a5c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3df209d58ebd5c5b1cf0168f6466e065d1ef3598 Original-Change-Id: I6dfed73f6ba5939f692d0f98d2774c0e0312a25f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210770 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8750 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-20libpayload: Add board id parsingVadim Bendebury
Make board ID value supplied in the coreboot table available to the bootloader on all three architectures. BUG=chrome-os-partner:30489 TEST=none yet Change-Id: I6c2d39e94212b55650929d7d99896581d23f789d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 723e4a600a5d3a03e960169b04f8322f6dd2486b Original-Change-Id: I7847bd9fe2d000a29c7ae95144f4868d926fb198 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210430 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-20libpayload: Do not include gcclib for mips targetsVadim Bendebury
As opposed to other architectures, on MIPS gcc toolchain provided gcclib is not always adequate, for instance when the library does not account for the case when data segment is too large to fit into the 64K GOT. Let's make sure the library is not included when building for MIPS targets. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of patches applied the FPGA board boots all the way to verifying and loading the kernel from the USB stick. Change-Id: I710d3c49bdc57877152cf28d5bd8cb4fa4d0b9ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f8d7d84c81af7e3eee1c8f3304c15069e8701cde Original-Change-Id: I1a26b9e575a20101329359b80dffc236ef7f9e9f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8740 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20stdlib: Add IS_ALIGNED macroAndrew Bresticker
Add a macro to check if a value is aligned. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: I0680954eb1b1964a631527f96aa0570a32944fa1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4f1717648e0a4b54217d71f8d0a15d496737d156 Original-Change-Id: Ie0bc1374918a7ffaaec5fea62c1193a42edd416c Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246692 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8757 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20libpayload console: Add check for already existing driverFurquan Shaikh
Add support to check if the driver for console_out or console_in is already present in the list. If console_init is called twice, then the driver might get added twice leading to a loop. BUG=None BRANCH=None TEST=With console_init in libpayload and depthcharge both, there are no console loops seen anymore Change-Id: I9103230dfe88added28c51bff33ea4fa1ab034c1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6931236ba2cfa71849973fe41cc340b7d70656ad Original-Change-Id: If9a927318b850ec59619d92b1da4dddd0aa09cd1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214072 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8739 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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