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2013-06-13AMD S3 resume: use a function to replace duplicated codeSiyuan Wang
In function OemAgesaSaveMtrr of 'src/cpu/amd/agesa/s3_resume.c', there are many code like this: msr_data = rdmsr(0x258); flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; Add a function write_mtrr to do this. Change-Id: Id6464e637db1758b07ac2d79d3be1375a8d49651 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3410 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13AMD Thatcher: fix issue 'S3 fails to suspend after wake up from USB keyboard'Siyuan Wang
This issue can be reproduced in Linux by the following steps: 1) use pm-suspend to suspend. 2) use USB keyboard to wake up. 3) use pm-suspend to suspend. FAIL To SUSPEND. The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. In this patch, I add AcpiGpe0Blk using MMIO access and write 1 on bit 11. Write 1 to clear as spec says. I have tested on Thatcher The same change was done for AMD Parmer in commit »AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard' (03901124) [1]. [1] http://review.coreboot.org/#/c/3347/ (Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1) Change-Id: Iaef39237497ef896d0f186e8f5522222c0ce6cb7 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3374 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13AMD: Kconfig cleanupKyösti Mälkki
Change-Id: I21182eae1d389790c330f27e6a830d91c3ee4eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3433 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-13Add support for Intel Nehalem CPUVladimir Serbinenko
Change-Id: I7ecc394b1e5bc0b8b85a8afac22efc0befe2d36a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3395 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13Revert "Add support for Intel Ibex Peak (Mobile 5) southbridge"Stefan Reinauer
This reverts commit 0210119b4b95e84f954cfd6dc11aafbc187421af Change-Id: I5be3f2a54394c592650a0dcd671e4a72ae796cb2 Reviewed-on: http://review.coreboot.org/3443 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-12Add support for Intel Ibex Peak (Mobile 5) southbridgeStefan Reinauer
Change-Id: If56f2cacc5f1b2ef9c7b6aea508d458a43dd1309 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3397 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12Avoid tripping overheat alarm on X201 before ME bootsVladimir Serbinenko
Until ME boots (which takes seconds on X201) the reported temperature is 128 °C which triggers Linux overheat alarm which shuts down. Pretend temperature is 40°C until ME boots. Change-Id: Ia49fa03c6eb27f539a23711f2c8ebfde72b1dc18 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/3404 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12Make acpi/ec.c usable in romstageVladimir Serbinenko
On X201 to enable EHCI debug you need to go through EC if USB power is disabled so we need to inclue ec.c. Change-Id: I8f8b7de639ecaebceaa53cd338136befaeec8214 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/3405 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12Radio and dock support in EC on X60 and X201Vladimir Serbinenko
Enable UMTS on Lenovo X60 and X201. Enable radios if no options are available. Enable dock on Lenovo X201. Based on my X201 branch. Change-Id: I6e8d3bbd6a6b1a8e59473dd5cc8125a1583d75df Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/3377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12am335x: Add struct `am335x_uart` for uart registersDavid Hendricks
Add a struct for referencing UART registers. The layout is quite strange on this chip, as the entire register space can take on three different meanings depending on the line control settings (in the LCR register) And to make things more confusing, some offsets reference different registers depending on if a read or a write operation is used. Change-Id: Ie62af9c0e0edafd01b81686a0fe5c5c1d4fa06c4 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3319 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12usbdebug: Quirk for board aopen/dxplplusuKyösti Mälkki
This ancient board with Intel e7505 invalidates cache while it does HW scrubbing for ECC in romstage. This breaks usbdebug console and prevents system from booting. If both EARLY_CONSOLE and USBDEBUG are selected, skip ECC scrubbing under these rare conditions to boot system. Change-Id: I6cb43bf69af54119f4a582dcaf498dd941d4c62d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3385 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12usbdebug: Drop printk within console_init()Kyösti Mälkki
In case with EARLY_CONSOLE, this printk is called before any other console is configured to transmit data. This outputs garbage on CONSOLE_SERIAL as baudrate is not yet programmed. For case without EARLY_CONSOLE, the order in which different console drivers initialize is obscure. Might sometimes work properly. Change-Id: I3792161e0a6dc17e17262048cc9136044dd69dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3384 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12usbdebug: Improve solving EHCI debug port problemsKyösti Mälkki
Add comment how one can debug the usbdebug hardware init. Do not send printk's to usbdebug console when one is debugging the usbdebug console initialisation itself. Change-Id: I21a285cb31cf64e853bc626f8b6a617bc5a8be19 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3382 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12Fix i82801a/b/c/d IOAPICKyösti Mälkki
Setting IRQ delivery to FSB got lost in the rebase process for commit e6143531. I captured following error on dmesg and this patch fixes it for i82801dx. ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 ..MP-BIOS bug: 8254 timer not connected to IO-APIC ...trying to set up timer (IRQ0) through the 8259A ... ..... (found apic 0 pin 2) ... ....... failed. ...trying to set up timer as Virtual Wire IRQ... ..... works. Change-Id: I0768976cc6b0deab213ad9bd4771e0f278de634c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3371 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12Add spkmodem receiverVladimir Serbinenko
This is spkmodem receiver counterpart. Change-Id: Id27d32608502029fb6fcc8154f508811bf5ca77b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/3411 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12intel/*/smi.c: Output correct GPIO in ALT_GP_SMI_STS register dumpKonstantin Aladyshev
Mapping is as follows: bit 15 corresponds to GPIO15 ... bit 0 corresponds to GPIO0. Change-Id: I661ce56d9373887270ba3c0518892fbbe6d9de7c Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/3436 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11intel/bd82x6x/Makefile.inc: Revert duplicate addition of `usb_debug.c`Paul Menzel
Currently in Intel BD82x6x southbridge’s `Makefile.inc` the file `usb_debug.c` is added twice to the build. This was introduced in commit 4063ede3fb571110c3e65c321049cc2687cc54fa Author: Ronald G. Minnich <rminnich@google.com> Date: Mon Feb 4 20:31:51 2013 -0800 bd82x6x: Fix compiling with USB debug port support Reviewed-on: http://review.coreboot.org/2784 but was unneeded because it had been already added in the following commit. commit 4141993536039e0d45caeacb745a89d388f0724b Author: Sven Schnelle <svens@stackframe.org> Date: Sat Jul 28 08:52:44 2012 +0200 bd82x6x: Fix CONFIG_USBDEBUG Reviewed-on: http://review.coreboot.org/1376 Therefore basically revert that hunk. There is no policy on how to order these additions, so leave it to a possible separate commit, unifying this. Kyösti Mälkki suspects that these additions were meant for the Intel Lynx Point [1]. [1] http://review.coreboot.org/#/c/3424/ Change-Id: Iaa8de6fcc0d6f3a0a92a28fcb603d7777aa8b24c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3425 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11Fix cycle error in intel southbridges to display GPI statusKonstantin Aladyshev
Fix obvious mistake in cycle that displays GPI status I hope i found all duplicates of it. Change-Id: Ic21ff3ecab85953463e5c23daf808dd5edc82ff8 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/3435 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11am335x: Revert how the header load size is calculated to an earlier method.Gabe Black
The current method will treat hex values as 0 and would calculate the wrong size. This change switches back to an earlier method which used shell syntax to add the offset and size. Change-Id: I9fb2d9b323f113cc56a5ad2e38b47d2d22084f08 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3432 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-11winbond/w83627dhg: Add ACPI supportNico Huber
This is loosely based on Christoph Grenz' ACPI code for the W83627HF and makes use of the PnP super i/o ACPI framework. Change-Id: I5e1cd09b83c0041f440562d2a1b73e4560589cb7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3288 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11Start ACPI framework for PnP (super i/o) devicesNico Huber
I'm trying to make writing ACPI code for super i/o devices more comfortable. pnp.asl hosts some general cpp macros. The other four files are to be included in dsdt trees. They are controlled by cpp macros which should be defined/undefined before inclusion. Work was inspired by Christoph Grenz' ACPI code for the W83627HF. Change-Id: Idb55332ba9bc788c98964d30a450e0d734cf28ec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3286 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11am335x: Make the iROM load only the bootblock and ROM stage.Gabe Black
The bootblock and ROM stages are the only ones that are really required to be loaded in the quite limited on chip RAM during startup. Rather than load the whole image which requires everything to be small, load just the bootblock and the ROM stage, allowing the rest of the image to be arbitrarily large. Loading a minimal amount of stuff should also improve boot performance a little bit. Change-Id: I2fede63b8d3d8f0d880e4a692ae423021f8232b6 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3421 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10beaglebone: Expand "ROM" size to 4MB.Gabe Black
Now that the ROM size is decoupled from the size of the on chip RAM, it's size is now only constrained by the size of the medium it's loaded from and the memory it's being loaded into, probably GBs in both cases. Making it 4MB is a reasonable compromise between giving the payload lots of breathing room and wasting space on the source medium which won't be used. Change-Id: I80932e0d4ce2dad02c3879345382e7d6ba44503a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3422 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10beaglebone: Force on every other user LED to show that coreboot is running.Gabe Black
Until we get serial working, this is a good way to show that coreboot is running. It can be removed once we have better methods. Change-Id: I62d25e52aa88a97aba4c959538d680b67a0bbbb2 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3329 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10VX900: Use MIN/MAX from stdlib.h instead of redefining themAlexandru Gagniuc
Change-Id: I2dd693b300085493baa65bb652df8d6cce80b63b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3431 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-10Add support for VIA EPIA-M850 boardAlexandru Gagniuc
EPIA-M850 can now boot linux. For a list of issues, see: http://www.coreboot.org/VIA_EPIA-M850 That's all folks. Change-Id: I7624944dbc05fbf3019897a116954d71dfda0031 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1228 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10VIA VX900: Add minimal ramstage needed to boot linuxAlexandru Gagniuc
This is the minimal code needed to get past ramstage, load SeaBIOS, jump to GRUB2, and boot linux (or load memtest). See individual source files for the status of each individual component. Change-Id: Ib7d5d7593c945f18af2c2fc5e0ae689ba66131a2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3419 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10VX900: Add DDR3 initializationAlexandru Gagniuc
The VX900 can be connected to either DDR2 or DDR3. On my board, it is DDR3, hence why there is no and will be no DDR2 code from my side. This is the raminit for DDR3 dimms for the VX900. I like the term "raminit" better than "memory training". This is a device, not a dog. What works and what doesn't is documented in the code. It does not make sense to hide that information in a commit message. Change-Id: Ib2ebc10e6d4d22d0a937fe9e895c17ce79153c88 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3417 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10ramtest.c: Add silent ram_checkAlexandru Gagniuc
In some cases, we want a ram_check that does not die and does not clobber the terminal with useless output that slows us down a lot. Usage examples include Checking if the RAM is up at the start of raminit, or checking if each rank is accessible as it is being initialized. As with all other ram_checks, this is more of a "Is my DRAM properly configured?" test, which is exactly what we want for something to use during memory initialization. Change-Id: I95d8d9a2ce1e29c74ef97b90aba0773f88ae832c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3416 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10VX900: Add support for early romstageAlexandru Gagniuc
Add support for VX900 early initialization up until, but not including raminit. Add the basic infrastructure, add a romstrap table, and functionality to configure the CPU bus and SMBus. This code is necessary and sufficient to prepare us for raminit. Change-Id: Icc9c41e4927b589f17416836f87a6a5843b24aa7 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3372 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10early_smbus: Add early SMBus implementation for VIA chipsetsAlexandru Gagniuc
Add a common implementation of SMBus functionality for early chipsets. Note however, that existing via chipsets are not ported to this code. Porting will require hardware testing to make sure everything is fine. This code is used in the VIA VX900 branch. Change-Id: If5ad8cd0942ac02d358a0139967e7d85d395660f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/144 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10am335x: Build an omap style header and an image with it at the front.Gabe Black
Loading on an OMAP SOC requires that the first sector of the image have a configuration header, and, when not an execute in place image, an additional header which describes how big the image is and where it should be loaded. This change adds some infrastructure to statically build that header using C code, and to paste the header onto the front of coreboot.rom in a new top level target file called MLO. The configuration header we're using is as inert as possible, in line with what U-Boot is doing. I think it could be used to give additional configuration parameters to the built-in ROM on the SOC, but we don't need to do that, and there didn't seem to be any actual documentation how to do that. Because the header is built from C and is defined per CPU, it would be possible to include extra settings in other CPUs if desired. Adding a new top level build target is a bit disruptive, but should be contained to the am335x directory and not interfere with other mainboards. Change-Id: I06d346a4050c20963b3c7c6e8a152070bf2d145a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3332 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10ARM: Put the ROM stage into the image before other bits.Gabe Black
On ARM, there's frequently some firmware built into the SOC which runs first and which loads other firmware like Coreboot from some other media. To prevent the bootblock from having to know how to find and load the ROM stage from what may be a complicated source (sd card, netbooting, etc.), we can put the ROM stage immediately after the bootblock and ensure that they're both loaded at the same time. This change adjusts the Makefile.inc for ARM so that the ROM stage is put into the image before any other files so that we know it comes first. This changes the behavior of the CONFIG_UPDATE_IMAGE config option used by abuild, although it's not entirely clear whether that's still used. Change-Id: I832386243788156db5f5abbc9760a4e2026cf2cd Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3420 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-06-10OT200: bring LEDs into a defined stateChristian Gmeiner
Keep in mind that we can _NOT_ read back the current state of the LEDS as some crazy FPGA designer wanted it that way. Change-Id: I5cd1ac598072318b3234d1ec35a79271655b46ac Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3271 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-09fam15 vendorcode: Change license to BSD from AMD software licenseSiyuan Wang
fam15 vendorcode (src/vendorcode/amd/agesa/f15tn) was licensed under the AMD software license agreement. Change this license to 3-clause BSD. Change-Id: I7cab09bb58ef7cd24602628e2278672d577214a2 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-09buildgcc: Re-add some break statementsPatrick Georgi
While some of the case .. break statement actually weren't needed, too are, since otherwise the option parsing loop hangs. Exit conditions for that endless loop: "--" or no more arguments, in line with GNU command line parsing rules. Change-Id: I0dbc35e530fb8c93a0f7de05ac47f325555ad4a4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/3418 Tested-by: build bot (Jenkins) Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
2013-06-07usbdebug: Fix use without EARLY_CONSOLEKyösti Mälkki
If EARLY_CONSOLE is not selected, the PCI function for EHCI host controller must be configured in ramstage instead. Change-Id: I20f7569f79484c744bc413450bfa139052f3580f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3383 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-07Lenovo X60: Add int15 handlerDenis 'GNUtoo' Carikli
Without that commit, with CONFIG_PCI_OPTION_ROM_RUN_YABEL, The VGA option rom doesn't init the right display: it initializes the external display, where we have a black scren(with backlight on). This commit is based on the code of mainboard.c in src/mainboard/roda/rk886ex. Change-Id: I8457aaf0503e0efdf0fcba9ff5e8a07ac04c5ca6 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3265 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-06-07i945: Add Display defines for int15h handler.Denis 'GNUtoo' Carikli
Change-Id: I7bc99761c7047e64b4e29c307ad779cec49c17c8 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3306 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-06qemu: copy dsdt tables from SeaBIOS, adapt for coreboot and enable acpiGerd Hoffmann
First copy over from SeaBIOS git repo, then adapt for coreboot: Disable cpu/pci hotplug bits. Disable dynamic pci window. Both depend on stuff in the SSDT tables created by SeaBIOS. Bits are left in, but deactivated via #if 0, so it's easier to see the differences when diffing the coreboot tables with the SeaBIOS tables. Adapt dsdt DefinitionBlock. Enable acpi table generation in acpi_tables.c. With this patch linux boots successfully with ACPI enabled. It's not bug-free though. Missing cpu detection leads to funky messages like this one: weird, boot CPU (#0) not listed by the BIOS. and SMP most likely wouldn't work either. Change-Id: Ic3803a6f1ef6d54c11cc4ca3844d3032a374ae6b Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3342 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-06-06ec/acpi: Add ACPI methods for generic EC accessNico Huber
Port most of the functions found in ec/acpi/ec.c to ACPI Source Language (ASL). These functions are used to control embedded controllers with the standard ACPI interface (mostly through i/o ports 0x62 / 0x66). The following methods are implemented and tested against the power managements channels of a ITE IT8516E embedded controller: * WAIT_EC_SC Wait for a bit in the EC_SC register * SEND_EC_COMMAND Send one command byte to the EC_SC register * SEND_EC_DATA Send one data byte to the EC_DATA register * RECV_EC_DATA Read one byte of data from the EC_DATA register * EC_READ Read one byte from ec memory (through cmd 0x80) * EC_WRITE Write one byte to ec memory (through cmd 0x81) To use the provided methods, one should include `ec/acpi/ec.asl` in the EC device code. Prior doing so, two macros should be defined to identify the used i/o ports: * EC_SC_IO I/o address of the EC_SC register * EC_DATA_IO I/o address of the EC_DATA register Change-Id: I8c6706075fb4980329c228e5b830d5f4e9b188dd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3285 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-06-06Intel Atom cpu support to msrtoolOlivier Langlois
Added support for Intel Atom cpu to msrtool Fixed a cut&paste error in nehalem msr bits definition It has been tested with a N455 cpu and msrtool output can be review at: http://www.trillion01.com/coreboot/msrtool_atom.txt Change-Id: I0ecf455b559185e2d16fa1a655bf021efc2ef537 Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net> Reviewed-on: http://review.coreboot.org/3351 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06AMD Trinity: Remove unnecessary lookup table copyBruce Griffith
The DDI connector table and the PCIe Port List lookup table are copied onto HEAP. This copy is not needed since these are lookup tables used to define the platform configuration. Change-Id: If4760f80e08faa8da4fd11337a3812f89cf805f9 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06AGESA: Add "const" modifier to function parametersBruce Griffith
Add CONST modifiers to read-only pass-by-reference function parameters in AGESA. This allows the use of "const" modifiers on the declaration of lookup tables that are pass-by-reference. These will be used to identify tables that are copied onto the HEAP but don't need to be. Change-Id: Ie1187a427804fddf47b935a110ad23931a3447a9 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06qemu: wind up new cpu chipGerd Hoffmann
Add boot cpu to the device tree. Figure the number of CPUs installed (using the qemu firmware config interface) and add cpu devices for them, so they show up in all generated BIOS tables correctly. This gets SMP going. Change-Id: I0e99f98942d8ca90150b27fc13c1c7e926a1a644 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3345 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06qemu: add x86 cpuGerd Hoffmann
This patch adds a qemu x86 cpu chip. It has no initialization function as this isn't needed on virtual hardware. A virtual machine can have pretty much any CPU: qemu emulates a wide range of x86 CPUs (try 'qemu -cpu ? for a list), also with 'qemu -cpu host' the guest will see a cpu which is (almost) identical to the one on the host machine. So I've added X86_VENDOR_ANY as wildcard match for the cpu_table. Change-Id: Ib01210694b09702e41ed806f31d0033e840a863f Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3344 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06ec/kontron/it8516e: Add it8516e EC driverNico Huber
This driver communicates with the IT8516e on the Kontron KTQM77. Since we don't know if the firmware and protocol are standard for the chip or customized to the board, call it kontron/it8516e. Change-Id: I7382172c6d865d60106c929124444821a07a5184 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3390 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06intel/bd82x6x: Add option to include ethernet firmwareNico Huber
Change-Id: Idf804ed29a67bad732df19e6981f74c8d0c354b5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06intel/bd82x6x: fix building usb debug on SNB/IVBPatrick Georgi
Change-Id: Ica3afbf8277cb025251da7af181f8de0d0036b45 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3389 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06(Trivial) early_smbus: fix printsmbus macroAlexandru Gagniuc
When I've first written this macro in 2011, the correct define for verbose SMBus message was CONFIG_DEBUG_SMBUS_SETUP. This has since been changed to CONFIG_DEBUG_SMBUS. I didn't catch that, and this made the printsmbus macro always evaluate to an empty statement. Use the proper CONFIG_DEBUG_SMBUS define. This makes printsmbus functional again. Change-Id: Iaf03354b179cc4a061e0b65f5b746af10f5d2b88 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3379 Tested-by: build bot (Jenkins) Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 21:45:59 +0000