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2008-11-03Dump ICH8/ICH9/ICH10 SPI registers in flashrom.Carl-Daniel Hailfinger
This helps a lot if we have to track down configuration weirdnesses. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03Add additional SPI sector erase and chip erase command functions toCarl-Daniel Hailfinger
flashrom. Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Thanks to Stefan for reviewing and commenting. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02Drop nr/opcode_index parameter from run_opcode and search the opmenu for the ↵Stefan Reinauer
opcode instead. This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02Get the lzma/ directory from v3 via svn:externals, for use with Bayou.Uwe Hermann
Also, fix a few Makefiles regarding lzma stuff and 'make clean' behaviour. Add bayou.xml.example which users can use as a starting point. Bayou does compile fine now (if you build ../libpayload) before. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02Import a slightly modified Bayou version into svn. This is basedUwe Hermann
on the last snapshot posted by Jordan Crouse. This commit is long overdue. Changes by me include: - Rename 'utils' to 'util' for consistency with our other projects. - Move the main code out of src/* into the top-level directory. - Add missing license headers to the following files: Makefile, pbuilder/liblar/Makefile, util/pbuilder/Makefile. - Dropped the util/pbuilder/lzma completely. I'm working on reusing the lzma/ dir from v3 via svn:externals. Alas, this also means that Bayou won't yet compile out of the box. - Coding-style and white-space fixes (indent) for all files. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02Trim down the list of southbridges supported by the i82801xx driverUwe Hermann
to only a set of reasonably similar ones, namely (for now) ICH0* - ICH6*, and C-ICH. All later ICH* southbridges (ICH7-ICH10) are _very_ different and were surely not working with this driver anyway (and there's no chance to support them reasonably with this driver without ending up in #ifdef hell). ICH7 now has an extra driver in svn, whether ICH8-ICH10 are similar enough to be supported by that ICH7 driver remains to be seen. This patch was informally acked by Stefan Reinauer <stepan@coresystems.de> on IRC. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02Add support for the ST M50FW002 chip to flashrom. Identification only,Carl-Daniel Hailfinger
erase/write are not implemented. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> tested and Acked-by: Elia Yehuda <z4ziggy@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02inteltool 82945G/GZ/P/PL Support (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines.Uwe Hermann
Build-tested on kontron_986lcd_m. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31Move the nvramtool manpage to section 8 (as it's only really usable as root),Uwe Hermann
as we've done with the superiotool and flashrom manpages, too (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30Leave room for ROM growth and for the payload. (trivial)Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30Increased the size of the failover and normal ROM_IMAGE_SIZE so abuild willMarc Jones
pass with toolsets that compile larger images. (trivial) Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30Here's a patch towards r3690 upping the ROM size for the S2912 Fam10 target ↵Arne Georg Gleditsch
to 1M. Both regular and abuild images have been boot tested successfully. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30Add support for the LiPPERT Cool SpaceRunner-LX embedded PC board:Jens Rottmann
- PC/104+ form factor - AMD Geode-LX CPU/northbridge - AMD CS5536 southbridge - ITE IT8712F Super I/O Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30Allow nvramtool to build and work on FreeBSD. Tested on FreeBSD 7.Andriy Gapon
Signed-off-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30Mark two more chips as fully tested (trivial).Uwe Hermann
- SST SST39SF010A - Winbond W29C011 Tested by me on actual hardware, all operations. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Flashrom support for some Numonyx parts (M25PE)Stefan Reinauer
using block erase d8 as discussed with Peter Stuge Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Enable SPI boot flash support on EP80579, which has the ICH7 register setEd Swierk
(trivial). Signed-off-by: Ed Swierk <eswierk@aristanetworks.com> Acked-by: Ed Swierk <eswierk@aristanetworks.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29i945/ICH7: Use #defines from pci_ids.h (trivial).Uwe Hermann
Build-tested with the kontron/986lcd-m target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for the Kontron 986LCD-M mainboard series.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for the Intel 945 northbridge.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for Intel Core Duo and Core 2 Duo (tm) CPUs.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for the Intel ICH7 southbridge.Stefan Reinauer
This includes an early SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Implement support for the Winbond W83627THG.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Changes required to the device allocator:Stefan Reinauer
- leave a hole for mmapped PCIe config space if CONFIG_PCIE_CONFIGSPACE_HOLE is set. - Mask moving bits to 32bit when resources are not supposed above 4G. Linux does not like this, even though the resource is disabled. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28Allow superiotool to compile and work on FreeBSD. Tested on FreeBSD 7.Andriy Gapon
Signed-off-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28Mark Winbond W39V040FA" (512 KB) as fully supported, tested byUwe Hermann
Martin Stecklum <stecky@gmx.net> (both write and erase). The tests were done on an MSI MS-7065 board, so that's supported now too (wiki page will be updated). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28Add support for the Intel 82371MX (MPIIX) southbridge (trivial).Uwe Hermann
Untested, but should work just as well as the other *PIIX* southbridges according to the datasheets. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-27Add initial support for the MSI MS-6147 mainboard.Mats Erik Andersson
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-26Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridges.Uwe Hermann
Tested on PIIX3 hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-25Add support for the VIA VT82C586A/B chipset, improve documentation.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-23Add support for the ITE IT8661F/IT8770F, IT8673F, and IT8671F/IT8687R.Urja Rannikko
They all use a different init sequence than the more modern ITE Super I/Os. For now we only use 0x370 as config port, but 0x3f0 or 0x3bd would also be valid. Contrary to other Super I/Os, the config port for these is _not_ hardcoded via hardware, instead it can be programmed by software, i.e. you get to choose whether you want to use 0x370, 0x3f0, or 0x3bd. Tested on IT8671F by Uwe Hermann and on IT8770F by Urja Rannikko. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-23make escape code handling for serial terminal more robustPatrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22Made await_ide(), which polls for an ide status change, check the statusJens Rottmann
reg much more often. In my case this reduced the time spent in coreboot by 1.5 sec! The timeout values of course aren't changed, only the granularity. Also, I didn't see any udelay() implementation that looked like it couldn't cope with 10 us delays. (Most are written as for (...) inb(0x80) loops.) Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22Changed RAM speed calculation to fix RAM modules getting rejected onlyJens Rottmann
due to integer rounding errors. Previously, the formula was: speed = 2 * (10000/spd_value) For spd_value=60 this means speed = 2 * 166 = 332, which is less than 333 and coreboot died saying RAM was incompatible. The new formula is: speed = 20000 / spd_value For spd_value=60, speed=333, which is fine. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22Speed up copying coreboot to ram by using "movsl" instead of "movsb".Jens Rottmann
Also use different console messages for copying and uncompressing, like it's already done in similar code in other places. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22Fixes a off-by-one error when routing the IRQs. This led to IRQ15 notJens Rottmann
getting assigned. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22Fix ordering problem in the libpayload Makefile. The include ofUwe Hermann
'include util/kconfig/Makefile' must come before certain pattern rules for compilation of kconfig files, otherwise the build would break in most situations. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22add multiboot support to defconfig (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22ouch. something went wrong with applying that old patchStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22This has been sitting here since a looong time.Stefan Reinauer
* allow versions of "install" that don't know -D * install libpayload .config and config.h to the target. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21Reduce serial output, otherwise flashing will fail very often (trivial).Uwe Hermann
This has been tested on hardware by me. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21[PATCH] fix video console initJordan Crouse
Move console_add_output-driver() inside the for() loop Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21I/O ports are 16bit, so change 'unsigned long port_base' to 'u16 port_base'.Uwe Hermann
Also, use more readable #defines instead of hardcoded config ports for PM/PM2 related functions, and simplify them a bit. Build-tested with the AMD dbm690t target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21This patch removes most of the #ifdefs in libc/console.c, andPatrick Georgi
replaces it with two queues (input, output) where drivers (serial, keyboard, video, usb) can attach. The only things left with #ifdefs are initialization (at some point the drivers must get a chance to register) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21Add missing license header.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20[PATCH] libpayload: Fix overflow in _delay functionJordan Crouse
On faster machines, delta might be more then 32 bits Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20[PATCH] libpayload: Add a strtoul() functionJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20[PATCH] libpayload: Bail if the keyboard controller isn't thereJordan Crouse
If the system in question does not have a superIO, then a read of 0x64 will return 0xFF and we will loop forever. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20[PATCH] libpayload: Fix the PCI search functionJordan Crouse
Remove a possiblity for evil recusion and fix the function and slot definition in the PCI search loop Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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