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2012-05-24abuild: Disable abuild-level parallelism for nowPatrick Georgi
It still failed because make touches files it isn't supposed to touch. Change-Id: I5a6ceaa9d5da212c1e34b121cf39fa9d27964747 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1037 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-24cbtypes.h: Unify cbtypes.h used in AMD board's codeVikram Narayanan
Remove all the repeated sections of code in cbtypes.h and place it in a common location. Add include dir in vendor code's Makefile. Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/912 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-21Fix Persimmon build without S3.Marc Jones
In the heap function, only check for S3 check when it is built in with CONFIG_HAVE_ACPI_RESUME. Change-Id: I439275a4e1b7b446b499bcf90c925785a14b980d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1034 Tested-by: build bot (Jenkins) Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-15Fix fadt legacy free setting.Marc Jones
The fadt legacy free logic was backwards. Change-Id: Ieb21ef335f7514ced70248d0bf8668ddb73cf59f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1030 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-05-15Change the name of the romstage bootblock.ldMarc Jones
The bootblock.ld linkerscript is used by romstage. Name it accordingly to avoid confusion. Change-Id: I7ca9147bb821fe6f83224d170f5fe25654ef250f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1031 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-05-15Fix Cygwin bootblock generationMarc Jones
Cygwin is case insensitive, so bootblock.s and bootblock.S in the same directory cause a build failure. This changes bootblock.S to bootblock_inc.S, as it is generated from bootblock_inc. crt0.S and crt0.S also had this problem. This changes crt0.S to crt0.romstage.S. Change-Id: I29d230a93b0743e34f11228f9034880ceaf7ab7b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1032 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-05-15Pass IASL to SeaBIOSMarc Jones
Use the coreboot IASL for building SeaBIOS. Change-Id: Ia6c802b090d53b7fbbc8ddb6edad3de6b822ff41 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1033 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-05-14SPI driver: style fixPatrick Georgi
lint tests for labels to start at BOL, no spaces before them. Change-Id: Icf6ce533f26998a81b4be46d17e2d0b6b868904d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1029 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-14crossgcc: Test for m4 and bisonPatrick Georgi
Happened way too often that crossgcc failed because m4 or bison wasn't installed already. Change-Id: Ibcca2183edd5db20608015e3898f8fff9a6d11e8 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1026 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-14crossgcc: update sourcesPatrick Georgi
Update GNU project versions, download GNU project tarballs using ftpmirror.gnu.org (http, picking close servers). Update ACPICA tarballs, ignore https certificates for all downloads. Not very useful, but breaks ACPICA download. Change-Id: I4aa8b08836346d031793a006b20b741d86e48988 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1025 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Raymond Danks <ray.danks@se-eng.com>
2012-05-14abuild: Move configuration handling togetherPatrick Georgi
Handling user options was spread out across the code. Collect as much as possible in the getopt loop. Change-Id: I4979a14988da000c008e155023b960535b529b41 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1028 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-14abuild: Remove abuild.info hackPatrick Georgi
abuild used to allow boards to override certain environment variables using a file called abuild.info. This isn't used, this isn't needed. Drop it. Change-Id: Ic93748f602bf0c354ff1f3be25a050e1cb469256 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1027 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-12Add legacy free setting and override to fadt.cMarc Jones
The FADT iapc_boot_arch indicates the available information for accessing legacy devices. By default, the setting supports legacy. LEGACY_FREE and/or the iapc_boot_arch field may be customized. Change-Id: I5679741e1f8db923d3c00b57f6a5d813550f3a5e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1024 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-05-12Merge sb800 fadt fixes from South Station mainboard to southbridge fadt.Marc Jones
The South Station recieved updates that fix a number of fadt problems. South Station now uses the southbridge fadt. Change-Id: Ib990a69a359a4b7eae3431bb4323acd537acda1d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1021 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-05-11Hook up MRC cache updateStefan Reinauer
Requirements: - must be in ramstage (locking flash while executing code from there might not work) - must be after cbmem is reinitialized (so the mrc cache copy of the current run can be found) Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1002 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
- Separate Sandybridge from ChromeOS a bit The Sandybridge code depends on chromeos features a whole lot. As a first step, provide a code path to look up the MRC cache without depending on u-boot. - Move mrc cache handling to separate file This enables us to handle the MRC cache from ramstage, where we can write the flash safely (eg. to update the cache). Also teach it to lookup the current MRC cache from CBMEM, as the original data block isn't available anymore. After all the preparations, finally write to the SPI as necessary. It's a simple round robin wear levelling that erases the entire MRC cache region when it's full and starts from the beginning. Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1001 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-10Add SPI flash driverStefan Reinauer
This driver is taken from u-boot and adapted to match coreboot. It still contains some hacks and is ICH specific at places. Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/997 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-10abuild: Build boards in parallel if possiblePatrick Georgi
Determine if xargs -P works. If yes, use that to build multiple boards in parallel, instead of relying on make -j X, when doing a full abuild run (instead of single boards). make -j X isn't able to make use of several cores at various serialization points in our build process, so this change results in a >25% speed up for a full abuild run in my tests. Change-Id: Id484a4211c84a3a24115278e0fbe92345f346596 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/409 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-10CIMx: Allow #define LEGACY_FREE overridesMartin Roth
For legacy free AMD systems, the #define LEGACY_FREE cannot currently be overridden. This patch allows the platform_cfg.h to override that. (I know we want to get away from that, but for now...) Also allow BIOS_SIZE to be overridden on SB700 cimx based platforms. Change-Id: I570115248bcbc686062bfb66acb56208240b847a Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1018 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-10Unmark source files as executablesAlec Ari
Change source file modes from 755 to 644 The following files have been grepped for changes: *.c *.h *Kconfig* *Makefile* Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/1023 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-10Integrate MA785GM-US2H to KconfigAlec Ari
MA785GM-US2H was left out of Kconfig. This allows the option to select the board. Change-Id: I9efea96c21dcd0754ab51824b410435b0b5300c2 Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/1022 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-09Update SeaBIOS URLPatrick Georgi
We have a http accessible SeaBIOS mirror at review.coreboot.org. Use it. Change-Id: Icce8e4f9ca1fa69966c82423b2b27057f15b30d2 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1020 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-09Move fadt.c to the cimx sb800 southbridge directory to be shared.Marc Jones
The fadt.c is the same across all the platforms using the sb800 cimx southbridge wrapper. Change-Id: Ifbbfc238732aa46aef96297eaa188b77d27151f3 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1019 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-09Add simple PMIO & PMIO2 read/write routines to CIMX wrapperMartin Roth
These are the PMIO & PMIO2 read & write routines from src/southbridge/amd/sb800/sb800.c & sb800.h for use in the cimx tree. Currently most platforms using CIMX are calling WritePMIO() directly from the src/vendorcode/amd/cimx/sbX00 directories instead of using a wrapper function. These functions only do byte reads & writes. Change-Id: I881a6e2d4ddbba3dbdf4dd33e06313fe88b3682a Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/981 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-08Don't loop infinitely long on serial comm failuresStefan Reinauer
If serial uart (8250/16x50) takes abnormally long to respond, give up on logging to serial console and instead let the system boot. Also reference bit in LSR register with correct name. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Ported from 9dd3ef165a1bf1bc404056d3e54337de1a15ac90 to uart8250mem.c: Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Iaca4f57389c887110e6406d45053935891c96838 Reviewed-on: http://review.coreboot.org/826 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2012-05-08Add a tool to work on i915 hardware in user modeStefan Reinauer
This is the beginning of a tool that transforms the i9x5 code to user mode code. Consider this a very early stage although it does produce two programs. Requires spatch 1.0 or greater. To try it out, assuming you have an up-to-date spatch, sh transform make make broken Please don't fall to the temptation to auto-magicize this process. It's primitive for a reason. That said, suggestions welcome of course. Change-Id: I0188e36637b198b06c17f6d3c714d990e88bd57d Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1003 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-08Fix build with CMOS support on various platformsPatrick Georgi
When bringing in nvramtool as build_opt_tbl replacement, various platforms where left in the cold that don't provide direct IO support from userland (or at least not in a way we support). Build nvramtool without CMOS support when done as part of a coreboot build. We don't need to touch CMOS in this case. Change-Id: Icc88d1d32f10384867a5d44b065f9aa119bb0d50 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/983 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-08Some more #if cleanupPatrick Georgi
Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} + (manual tweak since it hit a false positive) Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} + Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1006 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-08Add config_enabled() from LinuxPatrick Georgi
This change is taken from Linux. It allows to check for Kconfig definitions in the preprocessor and source code using the same idiom. Long term plan is to remove our Kconfig hack to #define values to 0, and this helps. This includes a tiny modification to the macros to fix romcc support. Change-Id: I0fddbea8c8ca215cf226acf39cb329b0ba0445a5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1005 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-04Make CBFS output more consistentStefan Reinauer
- Prefix all CBFS output messages with CBFS: - Add an option DEBUG_CBFS that is off by default. Without DEBUG_CBFS enabled, the code will no longer print all the files it walks for every file lookup. - Add DEBUG() macro next to LOG() and ERROR() to specify which messages should only be visible with DEBUG_CBFS printed. - Actually print a message when the file we're looking for was found. :) old: Searching for fallback/coreboot_ram Check cmos_layout.bin Check pci8086,0106.rom Check fallback/romstage Check fallback/coreboot_ram Change-Id: I2d731fae17a5f6ca51d435cfb7a58d6e017efa24 Stage: loading fallback/coreboot_ram @ 0x100000 (540672 bytes), entry @ 0x100000 Stage: done loading. new: CBFS: Looking for 'fallback/coreboot_ram' CBFS: found. CBFS: loading stage fallback/coreboot_ram @ 0x100000 (507904 bytes), entry @ 0x100000 CBFS: stage loaded. Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/993 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-04siemens/sitemp_g1p1: Drop debug codePatrick Georgi
Change-Id: I40a4201b468131ba67e48ab68d62ca5413f2e2e8 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-04roda/rk886ex: Expose VGA devices in devicetreePatrick Georgi
Otherwise set_subsystem isn't called for these (as they're not marked on_mainboard) Change-Id: I08e781735c59e4aa61009d2afa165d782f5a849e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-04lint: Avoid downloading blobs repositoryPatrick Georgi
The stable lint test "build-dir-handling" ran the build system in a way that made it download the blobs repository. Since this is part of the pre-commit hook, this might have kicked in with users desiring not to have them. Change-Id: I44a00137352c5966ff7fe2a030673276f6803908 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/999 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Don't pre-enable SATA AHCI in romstage.cStefan Reinauer
In a recent commit the SATA code of Panther Point / Cougar Point was changed to enable AHCI mode depending on the device tree settings rather than a hard code hidden in romstage.c. However, Emerald Lake 2 was not fixed up accordingly. Change-Id: I6c93f386509361e1ab5565b0e4d0e84f0ba282a2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/995 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Print some useful debugging information in PSS table creationStefan Reinauer
Change-Id: I1ec7a7e54513671331ac12f08d5f59161b72b0fd Example: PSS: 1900MHz power 35000 control 0x1300 status 0x1300 PSS: 1600MHz power 28468 control 0x1000 status 0x1000 PSS: 1400MHz power 24291 control 0xe00 status 0xe00 PSS: 1200MHz power 20340 control 0xc00 status 0xc00 PSS: 1000MHz power 16569 control 0xa00 status 0xa00 PSS: 800MHz power 12937 control 0x800 status 0x800 PSS: 1900MHz power 35000 control 0x1300 status 0x1300 PSS: 1600MHz power 28468 control 0x1000 status 0x1000 PSS: 1400MHz power 24291 control 0xe00 status 0xe00 PSS: 1200MHz power 20340 control 0xc00 status 0xc00 PSS: 1000MHz power 16569 control 0xa00 status 0xa00 PSS: 800MHz power 12937 control 0x800 status 0x800 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/994 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Make creation of CBMEM_ID_RESUME_SCRATCH depending on AgesaStefan Reinauer
The CBMEM_ID_RESUME_SCRATCH area is only used by Agesa code, on one particular board (AMD Persimmon). Make the creation of that section depending on Agesa so it does consume space on non-Agesa systems. Change-Id: I2a1a4f76991ef936ea68cf75928b20b7ed132b84 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/992 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Add missing newline to printk in Sandybridge init codeStefan Reinauer
Change-Id: I9217a75ec1a0abb898c45752d990231ce98e5fb2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/991 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Tell CBMEM pretty printer about MRC cacheStefan Reinauer
Sandybridge memory initialization produces some amount of training data that has to be kept around in CBMEM. Add a descriptive name to the CBMEM pretty printer to prevent it from just printing the hex value. Change-Id: I587c0bc3dfcf389ba298d445d2594eef73bc69a8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/990 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Fix register corruption during Intel Microcode updateStefan Reinauer
Another bug in the Intel microcode update code that existed since we switched to LinuxBIOSv2 in 2004: The inline assembly code that reads the CPU revision from an MSR after running cpuid(1) trashes registers EBX and ECX. Only ECX was mentioned in the clobber list. C code running after this function could silently access completely wrong data, which resulted in the wrong date being printed on microcode updates (and potentially other issues happening until the C code writes to EBX again) Change-Id: Ida733fa1747565ec9824d3a37d08b1a73cd8355f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/996 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-02ChromeOS: drop unused debug header descriptionStefan Reinauer
No part of ChromeOS seems to use the debug header description, so drop it to make sure it does not get copied around wrongly. Change-Id: Icb0baedbf6112f11289b2ddd9618a955a424ddf7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/989 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-02Make Intel i5000 specific options only appear on i5000 systemsStefan Reinauer
Change-Id: If183611b0b62d9321a5a12311c4cb3b344b04b36 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/986 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-02Don't include console.h in microcode.c when compiling with ROMCCStefan Reinauer
If microcode.c is built by romcc, this indicates that we are running microcode updates in the bootblock (e.g. before enabling cache as ram). In this case we did not enable any consoles yet, so we don't output anything. This patch removes inclusion of the unnecessary console/console.h for that case, which was breaking with certain configurations. Change-Id: Iebb57794d7b1e84cac253d249d47b88de4dd28a3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/988 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-02Strip quotes from Sandybridge MRC blobStefan Reinauer
This fixes my build when specifying an absolute path to the binary. Change-Id: I95fb3960be70f78146c6afeb9cc777dccdca6b5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/987 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-02Sandybridge: Display platform information earlyVadim Bendebury
It is important to have the system configuration reported as early as possible to have a better idea what exact chipset the platform is running with. This change adds code to have an early coreboot module report the CPU and PCH information. CPU info includes the 32 bit feature information word, the symbolic processor brand string, and information about some features support, as obtained through CPUID instructions. The PCH information includes the symbolic device name and PCI device version. Change-Id: If6c21ad5ffb76d7d57d89f4f87d04bdd7192480a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/975 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-01Fix issue with PCIe power management setupDuncan Laurie
The current early PM setup that attempts to configure dynamic clock gating relies on PCIe functions to be enabled that may not be. Instead of reading port 0 or 4 directly to determine the link width use the register that refelects the soft strapping options as this will always be available. Also add a clear register assignment and break for port 0 in the switch statement instead of falling through to port 4 as that could end up setting the slot power limit based on port 4 values instead of based on port 0. register 0xE1=0x3f and all other root ports should have 0xE1=0x03. When port 0 and 4 are disabled they will have 0xE1=0x3C before being disabled by the pch enable handler. LUMPY default: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5) pci_read8 0 0x1c 0 0xe1 0x3f pci_read8 0 0x1c 3 0xe1 0x03 LUMPY with PCIe port coalesce enabled: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5) pci_read8 0 0x1c 0 0xe1 0x3f pci_read8 0 0x1c 1 0xe1 0x03 Change-Id: I33a37b0ec0c8e570cf5d9dda2c06e0225fee135c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/980 Tested-by: build bot (Jenkins)
2012-05-01Add an option to enable PCIe root port coalescingDuncan Laurie
Background: The PCI spec (3.0-3.2.2.3.4) requires that PCI devices implement function 0. The Linux Kernel therefore will not enumerate a PCI device if it does not present a valid config space at function 0. If a board does not have anything connected to root port 0 and it is desired to disable the unused ports in order to save power then this will cause the other downstream PCIe devices to go missing as they will not be enumerated. Intel chipsets provide a way to map root port numbers to different PCI function numbers, thereby avoiding this issue and allowing root port 0 to be turned off. This change adds a new chip config option 'pcie_port_coalesce' that will collapse the enabled root ports into a linear map starting at zero. This option defaults to disabled as it can have a confusing effect on the system as the declared static devicetree may not match what is seen at runtime. This option is also forced on if the static devicetree disables port 0. When each root port is processed in the early enable stage it looks for a lower numbered root port that has been disabled and then swaps the two assigned function numbers. However the mapping register is write-once so it has to keep track of the proposed mapping changes until all ports have been processed before writing out the final map value. At this point it also updates the function numbers in the static device tree so they are consistent with the new layout. There are a few other closely related fixes in this change: 1) There is a power savings opportunity if an entire bank of ports (0-3 or 4-7) are disabled. This was checking the chipset revision to look for CougarPoint B1+ stepping and that was not passing on PantherPoint where this should always be applied. To fix this I added a function to determine the chipset type based on comparing the upper byte of the device ID. 2) Apply the same chipset type check fix to the IOBP programming. 3) There is another power savings opportunity to enable dynamic clock gating on shared PCIe resources which only applies to ports 0 and 4. However if 0 or 4 is disabled then the later check to enable this would fail as that device is already hidden. LUMPY current: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5) 01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01) 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B LUMPY with PCIe port coalesce enabled: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5) 01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01) 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B Change-Id: I828aa407fdc9c156c1c42eda8e2d893c0aa66eef Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/979 Tested-by: build bot (Jenkins)
2012-05-01Update PCIe Root Port _PRT to handle re-mapped functionsDuncan Laurie
The chipset enforces static-defined interrupt swizzling on PCIe root ports so if a port is remapped to a different function it needs to still report the proper interrupt map to the OS instead of assuming that function number is equivalent to root port number. This change also includes an update to the PCH function disable register which was incorrect for CPT/PPT and would cause unpredictable behavior if used. The kernel command line was changed to add 'nomsi' in order to force PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure that the mapping is correct. LUMPY current: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5) 16: 41518 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k 19: 720 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0 LUMPY with PCIe port coalesce enabled: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5) 16: 38988 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k 19: 347 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0 Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/978 Tested-by: build bot (Jenkins)
2012-05-01Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boardsStefan Reinauer
CONFIG_MAX_PHYSICAL_CPUS is defined by quite a number of mainboards whithout any code actually using the variable. Hence, drop MAX_PHYSICAL_CPUS from Kconfig for those boards. In the long run we should drop CONFIG_MAX_PHYSICAL_CPUS use completely and make the code dynamic or depend on CONFIG_MAX_CPUS instead. Change-Id: I37dcc74d245ddba5186b96bd82220dacb6f4d323 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/984 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-01Fix SATA port map to only enable port 0Stefan Reinauer
The sata controller comes up in legacy/normal mode and is currently put into AHCI mode in romstage. If that is removed and the controller is left alone until the ramstage driver (like we do on Stumpy/Lumpy) then the resource allocator will have configured the device for IDE mode with an IO address in BAR5. Then when the ramstage driver puts the controller into AHCI mode it will not have the correct resources to do the rest of the AHCI setup. So the controller mode needs to be changed in the enable stage rather than in the init phase. This same register contains the port map and it is a R/WO (write once) field so the configured port map must be written at the same time. For non-AHCI mode the devicetree map was ignored before but it is used now. Since the port map register is now written at enable step it does not need to be written again during init. With this change the sata port map can be reduced to just port 0 and then U-boot does not have to probe all available ports. Change-Id: I977952cd88797ab4cea79202e832ecbb5c37e0bd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/977 Tested-by: build bot (Jenkins)
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