summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2017-06-27util: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I0a024d82d331c0794fe087e440b4e1924129a13c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27buildgcc: Adapt messages about GNAT and bootstrappingNico Huber
Don't ask for bootstrapping in case of a different host GCC major version. GCC's versioning scheme changed starting with the release of GCC 5. There are no big changes between the versions any more. Instead, show the message when the host GCC's version is below 4. In case GNAT can't be found, ask the user to abort and install it. Also give hints for Ubuntu where the package versions are a little messy (e.g. the meta packages gcc and gnat often point to different versions). In case GNAT is found but is too old (< 4.9), enable bootstrapping by default and tell the user that building will take longer. In all three cases show a timeout to draw the user's attention. v2: Update GNAT check to also look for `gnatbind`. It has to be somewhere in $PATH. Change-Id: I4d9de11d7469e137ede8ad138296d20c0f8ba78f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20332 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27buildgcc: Rename quit() to exit_handler()Nico Huber
"quit" is a signal name. The FreeBSD `sh` interprets trap quit 1 2 3 15 as command to reset all the respective signal handlers, instead of setting quit() as handler. Change-Id: I69b813ab583f15a9dd89a115f7aea66d966f981b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20391 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr) to AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-27soc/intel/common/opregion: Use enum cb_err as return valuePatrick Rudolph
Return CB_SUCCESS and CB_ERR instead of some integer. Preparation to merge intel/soc and intel/nb opregion implementations. Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27nb/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-27coreinfo: Use regular `if` over `#if` for `IS_ENABLED`Nicola Corna
When using the regular `if` construct, the compiler will check the guarded code independently from the condition. Change-Id: I00c5c7ae3720f75aa9415edb94cd2ce76cee8aee Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/intel/quark: We're not Broadwell anymoreStefan Reinauer
... even though the author of the code probably wished he was working on a (much faster) broadwell system instead. Let's fix the header guard to reflect the right SOC. Noteworthy: clang detected that this was wrong. Change-Id: I74c217c0471800f40c31a9ac38ba5396f82cd724 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27northbridge/amd/pi: Arithmetics is not logicStefan Reinauer
It's pretty obvious that the author did not want to use a logical and (&&) here but an arithmetical and (&) Change-Id: Ic1bece86986906b76308bbb46235c22418e27990 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27README: Update requirementsStefan Reinauer
pkg-conf and libssl-dev are needed for abuild to run successfully on all boards. Change-Id: Ic0ca2036751893ac4bd3ff17c53fe518b22b64ad Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27amd/amdfam10: Remove dead codeStefan Reinauer
dual_node is never used in that function. And it is never set correctly either, because the register f3xe8 is never actually read either. Just remove the whole useless construct. Change-Id: If316da89bceae6b162f20e4b632276db2d9ef423 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27drivers/spi: Don't disable non-existent warnings on clangStefan Reinauer
The warning -Wstack-usage= doesn't seem to exist on clang, so trying to disable it makes the compiler unhappy about non-existent pragmas. Catching this on gcc is good enough, so let's disable it for the clang case Change-Id: Ia3716a83ba41743ac1dbe73e70abd170de30d7ab Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27vendorcode/amd: Satisfy clang's bracing requirementsStefan Reinauer
src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h:3688:7: error: suggest braces around initialization of subobject Change-Id: Id086a64205dfffa2d1324993f4164508b57b6993 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27vendorcode/amd: Make compiler intrinsics clang friendlyStefan Reinauer
Change-Id: Ibff31a9960a23f03facbb09e76d6a5d6fbfb5e94 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27libpayload/drivers/usb/ohci_private.h: Add brackets around macroElyes HAOUAS
Change-Id: Id4892adba161cd08eecde71a011384b6c465b98f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27mainboard/lenovo/x220: allow to use libgfxinitAlexander Couzens
Change-Id: I8b02596b116c0b164e83e7b02449c547224a50a6 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/20330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-27include/device: Add pci ids for Intel CNLLijian Zhao
Change-Id: Ia76c391e04e1e11bd110764902b91ef4ed5e8490 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-27cpu/x86/smm: allow SSE instructions in SMM modulesAaron Durbin
If SSE instructions are enabled in the build assume the SMM modules are compiled with SSE instructions. As such enable the SSE instructions in SMM mode by setting up the cr4 register. In addition, provide a place to save and restore the SSE state in both the relocation handler and permanent handler. Change-Id: Ifa16876b57544919fde88fba5b8f18e4ca286841 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20244 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-27sb/intel/bd82x6x: Fill in acpi_namePatrick Rudolph
Fill in acpi_name to return proper ACPI names. To be used with SSDT generators. The ACPI names have to match those already used in ASL code. By providing the ACPI name it can be retrieved by the acpi_device_name() method and doesn't need to be hardcoded in SSDT generators any more. HDEF is defined in sb/intel/bd82x6x/acpi/audio.asl. LPCB is defined in sb/intel/bd82x6x/acpi/lpc.asl. RP0* is defined in sb/intel/bd82x6x/acpi/pcie.asl. SATA is defined in sb/intel/bd82x6x/acpi/sata.asl. SBUS is defined in sb/intel/bd82x6x/acpi/smbus.asl. EHC? is defined in sb/intel/bd82x6x/acpi/usb.asl. XHC is defined in sb/intel/bd82x6x/acpi/usb.asl. Change-Id: I08611b11c694ee5034bca11cb321915d5c73c2f6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-27nb/intel/sandybridge: Fill in acpi_namePatrick Rudolph
Fill in acpi_name to return proper ACPI names. To be used with SSDT generators. The ACPI names have to match those already used in ASL code. By providing the ACPI name it can be retrieved by the acpi_device_name() method and doesn't need to be hardcoded in SSDT generators any more. GFX0 is used in drivers/intel/gma/acpi/pch.asl. MCHC is used in nb/intel/sandybridge/acpi/hostbridge.asl. Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27util/blobtool: add spec files for DDR3 SPDsMartin Roth
Because of how blobtool works, we need different files for the 128 and 256 byte versions. Change-Id: I9a3a532515eaeeb65ae05ce4f7a37c88500c6193 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-273rdparty/chromeec: Update submodule to upstream masterMartin Roth
Update from commit bcffec7fd - reef: Cleanup battery code to commit 9fb10386a - Poppy: Configure camera PMIC to low power mode. Brings in 794 new commits from Jan 2, 2017 to Jun 21, 2017 Change-Id: I864679360bd3b211b6883a662e20812b49aefbba Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27mb/google: Remove ChromeEC builds for auron and rambiMartin Roth
The ChromeEC board directories for auron and rambi have been removed from the latest version of ChromeEC. Remove them here so the submodule can be brought forward. Change-Id: I763d03009f735d3f8aedbeb44788d03714c86102 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27mainboard/google/poppy: Update world facing camera sensorV Sowmya
Update the world facing camera sensor to OV13858 and also add delay of 5ms after xshutdown rising which indicates system ready status. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successfull. Change-Id: I0cd535e6568f104ffaa1092a13667def646df0eb Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-06-27mainboard/google/poppy: Add clock frequency for camera sensorsV Sowmya
Add clock frequency property into _DSD ACPI object and set it to 19.2MHz for camera sensors. Upstream camera kernel has added a check for clock frequency in sensor probe function and without this property sensor probe fails. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successfull. Change-Id: I147b3c932a33ae034868f7f9b616500d24ca71e3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20294 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-06-27util/crossgcc: Fix building gcc 6.3.0 with clangPatrick Georgi
It assumes that __builtin_longjmp takes a void **, which is decidedly distinctive from void *. Change-Id: I1930bb01dd62bd6abf0688b118236db2a9299e40 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/20366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27crossgcc: Fix building with clang++ in the presence of gccPatrick Georgi
Some environments (<grumble>cros_sdk</grumble>) provide gcc as $CC and clang++ as $CXX. The latter needs the higher bracket-depth while the former has no idea what it means, so tell CC and CXX individually. Change-Id: I72b75fb9bb5df3a9b1561ee8821ec43ada29b24f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/20365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27libpayload: corebootfb: Add null check for framebuffer addressDuncan Laurie
If the framebuffer address is zero the corebootfb_init() function should abort and not attempt to use it for video, otherwise it will likely hang. This was tested by booting on a board that does not have a display attached and includes the previous patch to zero the framebuffer structure in the coreboot tables. Change-Id: I53ca2e947a7915cebb31b51e11ac6c310d9d6c55 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-27lib/coreboot_tables: Zero framebuffer structureDuncan Laurie
Zero the framebuffer structure so if it is not filled in (either if no display is present or if there is an error) then it does not provide garbage data to the payload. This was noticed when booting a board without a display attached as the payload wrote to the framebuffer at a random address. With this change the payload can properly handle the case where a display is not attached and not corrupt memory. Change-Id: I8114d88496cd2a4f2e7f07f377fe76f3180a7f40 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-06-27soc/intel/skylake: storage: Use word access for power state registersDuncan Laurie
In the D0 and D3 ACPI methods use word access to the PME status and control register. This brings the code inline with the Intel reference code and matches how the kernel handles access to this register. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across multiple devices Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27soc/intel/skylake: storage: Add 2ms delay before exiting D3Duncan Laurie
For the skylake/kabylake generation of PCH there is an ACPI workaround for emmc/sd power state that involves disabling and re-enabling dynamic clock gating after enabling power to the controller, before setting the power state to D0. Under certain conditions we have observed that the controller is not powered and ready by the time the kernel attempts to read the PME control and status register and so the system will hang while attempting to read PCI config register 0x84. To ensure that the controller is ready add a 2ms delay after re-enabling dynamic clock gating and before setting the power state to D0. This issue has been observed on eMMC, but the same workaround exists for the SD card interface so the same delay is added there. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across many devices shows no hard hang after 2 days. Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-273rdparty/blobs: Update submoduleMartin Roth
Update blobs pointer to bring in the AGESA.bin changes for amd/00670F00/FP4 and amd/00670F00/FT4. Change-Id: I739124090e41edaf76210cda6189b2c7545cdf58 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-26libpayload: Enable building libpayload with march=i586Lee Leahy
Add a Kconfig value to enable building libpayload with the 586 compiler. Update the cross compiler script to add the Kconfig value name that is used when libpayload builds. The Quark SOC does not support some of the instructions generated with the 686 compiler (e.g. CMOV). Success occurs when payloads/libpayload/build/config.h indicates that CONFIG_LP_USE_MARCH_586=1. TEST=Build and run on Galileo Gen2. Change-Id: I04907e9a38ee139bae2e8b227821f54614707c25 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26buildgcc: Allow environment to override $CC/$CXXNico Huber
Also check for the presence of the given commands or "gcc", "cc" in this order if $CC is empty. To untangle the given compilers from boostrapped ones, introduce hostcc() and hostcxx() functions that return the respec- tive compilers to be used. Change-Id: Ic947be53eec25331173ac82ed742017ca3fbf83c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-26vendorcode/amd: Drop multiple copies of gcc-intrin.hStefan Reinauer
Change-Id: Ifc6a0638c03fa5f3e1007a844e56dfa6f4c71d7e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-26vendorcode/amd: Unify gcc-intrin.hStefan Reinauer
Most of these functions go unused most of the time, but in order to not keep several copies around, let's make sure we are using the same file everywhere first. Change-Id: Ie121e67f3663410fd2860b7d619e8a679c57caba Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-26libpayload/configs: Add configuration for GalileoLee Leahy
Add the default configuration file for the Galileo board. The Quark SOC requires building libpayload with march=i586. TEST=Build and run on Galileo Gen2 Change-Id: Ifd4b533feacbab6f0d357e13d8cebb64bc1c18c6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/intel/fsp_baytrail/include/soc/pci_devs.h: Add brackets around macroElyes HAOUAS
Code checked manually Change-Id: I91ababb3bf7aa1ab0f71bb005c4685e81bb4d92f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26amd/gardenia: Fix most checkpatch errorsMarshall Dawson
Correct all checkpatch errors but leave two errors in place that are caused by AMD typing. Change-Id: I9daa374da76ff991de72d16bad0e8b586aa95525 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26amd/gardenia: Switch to soc/amd/stoneyridgeMarc Jones
Switch Garnenia mainboard to single soc/ directory structure. Change-Id: I095804d603bcccf324d3244965081a9dccba62ae Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/amd/stoneyridge: Add northbridge supportMarc Jones
Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/amd/stoneyridge: Add CPU filesMarc Jones
Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc: Add AMD Stoney Ridge southbridge codeMarc Jones
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26rockchip/rk3399: update the ddr 200MHz frequency configurationCaesar Wang
This patch updates the coreboot DDR Settings to match the configuration used by ARM-Trusted-Firmware. Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/20304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-06-25crossgcc/buildgcc: update file location codeMartin Roth
- Change from 'which' to 'command -v'. 'which' is not a posix command. Change-Id: Icdf18e7e496447157554b8e61b1528f03456536d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20230 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-25xcompile: Fix clang compiler runtime detectionStefan Reinauer
clang, like gcc, needs a compiler runtime library. Unlike gcc, it can use either its own runtime library (compiler-rt), or gcc's version (libgcc). Also unlike gcc, the version of clang that is currently part of our reference toolchain does not provide the necessary versions of compiler-rt for all platforms we support. Hence, for now, use libgcc even on clang builds. This patch allows switching between the two, but switching to compiler-rt will break clang builds, unless someone fixes our reference toolchain to provide libclang_rt.builtins-${ARCH}.a for each of our supported platforms. Change-Id: I5001a4b62ed34df19312f980b927ced8cbaf07db Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-23soc/intel/skylake: Remove post SMM Relocation uCode loadingBarnali Sarkar
As per latest BWG, ucode reloading should be done at the end of Mp Init, i.e., after PRMRR and other features are enabled. No reloading specifically after SMM Relocation is required. As, in the Common CPU MP Init code, we are already doing a uCode load at the end of MP Init Feature Programming, hence, the uCode loading after SMM relocation can be removed. Change-Id: Ib1957c5fe5a8c83bb20b978a9841670b0c3e8846 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-23soc/intel/skylake: Use CPU MP Init Common codeBarnali Sarkar
This patch uses the common CPU Mp Init code. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: Ieb2f8ae25a31e86e9251fe97859678745fe610f5 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-23soc/intel/common/block: Add common MP Init codeBarnali Sarkar
This patch contains State Machine callbacks init_cpus() and post_cpu_init(). Also, it has the SOC call for CPU feature programming. Change-Id: I5b20d413c85bf7ec6ed89b4cdf1770c33507236b Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-23siemens/mc_apl1: Enable decoding for COM 3 on LPCMario Scheithauer
It does not work to enable the LPC range in the function mainboard_init() because the LPC bus driver closes the range during PCI enumeration again. For this reason, enabling decoding of the address range for COM 3 will be done at a later point in time - mainboard_final(). Change-Id: I452bca4e430b1ea75e4a327591da84500491fe84 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 03:15:29 +0000