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2014-11-15sandy/ivybridge: Use DYNAMIC_CBMEM with native raminitKyösti Mälkki
Change-Id: I76577cc3739f23d392d077db5a5edfdbdbe8fb1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7466 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-11-15mainboard/*/debug.c: Remove duplicate or dead codeEdward O'Callaghan
We already have these implemented in 'lib/debug.c'. Will fix '.c' includes in follow ups. Change-Id: I1586d8864db7f93515214ef9a4458ebc618bf61c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7316 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-11-15vboot: allow non-relocatable ramstage loadingAaron Durbin
The vboot implementation previously assumed that ramstage would be a relocatable module. Allow for ramstage not being a relocatable module. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built nyan with vboot. Original-Change-Id: Id3544533740d77e2db6be3960bef0c129173bacc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190923 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 756ee3a6987097c65588c8784ee9653fd6e735e4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I813b07e1bec75640ad4066aca749ba8dccec31d4 Reviewed-on: http://review.coreboot.org/7220 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-15chromeos: provide stub functions for !CONFIG_VBOOT_VERIFY_FIRMWAREAaron Durbin
Instead of checking #if CONFIG_VBOOT_VERIFY_FIRMWARE #else #endif provide empty stub functions for !CONFIG_VBOOT_VERIFY_FIRMWARE. BUG=none BRANCH=baytrail TEST=Built and booted. Original-Change-Id: Id9d1843a0ec47c5a186c9a22ea3e4c13c89ec379 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/184841 (cherry picked from commit f6d95cf4ba6ce1bc0e1df4a0e9f655ad9fea9feb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If35ace863243e36399fc40c2802a2f7f2711e83b Reviewed-on: http://review.coreboot.org/7395 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-14nvidia/cbootimage: update to masterPatrick Georgi
It contains a number of fixes to bugs found by Coverity Scan. Change-Id: I362a069afd37783f59d8831e44ae885e8490819e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7392 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-14AMD: Move RAMBASE and RAMTOPKyösti Mälkki
There are no reasons to not load ramstage @ 0x100000. Boards with HAVE_ACPI_RESUME enabled have performance penalty in using excessive RAMTOP. For these boards, this change releases 11 MiB of RAM from CBMEM allocation to OS. Change-Id: Ib71995aba5e9332d0ec1626b3eb3b4ef6a506d1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7094 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-14AMD (K8/fam10): Rewrite CAR migration in post_cache_as_ramKyösti Mälkki
Old routine copied all of CAR region as-is right below CONFIG_RAMTOP. Most of this region was reserved to interleave AP CPU address spaces and unused on BSP CPU. The only part of CAR region requiring a copy in RAM is the sysinfo structure. Improved routine changes this as follows: A region of size 'backup_size' below CONFIG_RAMTOP is cleared. In case of S3 resume, OS context from this region is first copied to high memory (CBMEM_ID_RESUME). At stack switch, CAR stack is discarded. Top of the stack for BSP is located at 'CONFIG_RAMTOP - car_size' for the remaining part of the romstage. This region is part of 'backup_size' and was zeroed before the switch took place. Before CAR is torn down the region of CAR_GLOBALS (and CAR_CBMEM), including the relevant sysinfo data for AP nodes memory training, is copied at 'CONFIG_RAMTOP - car_size'. NOTE: While CAR_GLOBAL variables are recovered, there are currently no means to calculate their offsets in RAM. NOTE: Boards with multiple CPU packages are likely already broken since bbc880ee amdk8/amdfam10: Use CAR_GLOBAL for sysinfo This moved the copy of sysinfo in RAM from above the stack to below the stack, but code for AP CPU's was not adjusted accordingly. Change-Id: Ie45b576aec6a2e006bfcb26b52fdb77c24f72e3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4583 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-14build system: improve portabilityPatrick Georgi
There are too many differences, and calculating relatively large integer using floats might not be the brightest idea anyway. Also avoid relying on ls(1) output format to determine file sizes. Change-Id: I5f96c036737b74e20f525c3dc9edc011ad403662 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7447 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-14mainboard: Remove commented include lines for mc146818rtc.hEdward O'Callaghan
Change-Id: I4d830d988b74f2403ef8979cbafcaee3018fea62 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7423 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-11-14tegra124: allow tegra124 devices to run vboot rmoduleAaron Durbin
The non-x86 systems need the monotonic timer interface. Add tegra124's timer implementation so vboot can link. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built nyan with vboot verfication. Original-Change-Id: I75b99b6e07eeab0324495f97472f14a36883161e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190925 (cherry picked from commit 1e632e861f0e6d10cea0010561e410c1d6c2f317) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9ef177f7c7bb90ceacfe25162bb97047a7c8599d Reviewed-on: http://review.coreboot.org/7463 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-11-14Big, Blaze: Set I2S1 Source to CLK_M to Fix BeepDaisuke Nojiri
This is a companion patch of CL:191692 "Tegra: Fix Beep". TEST=Booted Big. Verified beeps at dev screen. Measured frequency by smartphone. Built Blaze. BUG=chrome-os-partner:26609 BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I9ba47d06202e9968a908c4a15cfbeac4bfe2c20c Original-Reviewed-on: https://chromium-review.googlesource.com/192063 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 87a0f166e493b98d2a4e597f90ede090161fffdb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id3b819745b0753862e8cfa43e7fa1ed4b27eb462 Reviewed-on: http://review.coreboot.org/7462 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-14nyan: tpm: Increase the TPM frequency to 400 KHz.Gabe Black
The TPM now works correctly with the I2C bus running at 400 KHz. Running it at that frequency saves some boot time. CQ-DEPEND=CL:191634 CQ-DEPEND=CL:191793 BUG=chrome-os-partner:27220 TEST=Built and booted on nyan with and without EFS. BRANCH=None Original-Change-Id: I157308c2745342dc1ada4499433004c7ce1c6435 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191813 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 39a740d488d8f33ee698805bc2a8438263162cc8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I02978407e20cc9d526545157a3a3304729a91010 Reviewed-on: http://review.coreboot.org/7461 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-11-14tegra124: i2c: Reset the controller when there's an error.Gabe Black
This is the only way to clear the error bits in the controller. Without clearing them, every future transaction will look like it failed. BUG=chrome-os-partner:27220 TEST=Built and booted on nyan with the TPM frequency turned up to 400 KHz. BRANCH=None Original-Change-Id: Ib654e60ec3039ad9f5f96aa7288d3d877e5c843a Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191811 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 7b19a095652f1561590dcca922b9f8c308d7de9d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I301b6694cc521601b618973de891e4ed44c6a97d Reviewed-on: http://review.coreboot.org/7460 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-11-14tegra124: fix the dangerous VPR write orderJoseph Lo
Currently we put the VPR write code just right before the AVP is going to freeze. We have no idea does the write operation successful or not before halting the AVP. And the power_on_main_cpu should be the last step of that. So we make a fix to change the order. BUG=none BRANCH=none TEST=LP0 suspend stress test and check the VPR is correct; LP0 suspend stress test with video playback Original-Change-Id: Ia62dde2a020910de39796d1cf62c1bf185cdb372 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192029 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Original-Tested-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit 51473811fa477cca9ad9cbafdaad4fd4a2309234) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia28329e38fcf12994594b73c805d061804aa01c4 Reviewed-on: http://review.coreboot.org/7459 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-11-14tegra124: Add some functions for resetting peripherals.Gabe Black
These make it possible to reset peripherals without having to dig into the crc. BUG=chrome-os-partner:27220 TEST=Built and booted on nyan with EFS and with the TPM bus turned up to 400KHz. BRANCH=None Original-Change-Id: I7e77b719e1ba30d2964cfbfda467f937d80b5b21 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191810 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 18c6a48623ae6eff70ca05ea15a7901972a7bba3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8f46666bcf51215f332724ea871f14fec2b522f0 Reviewed-on: http://review.coreboot.org/7458 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-11-14Nyan: Set I2S1 Source to CLK_MDaisuke Nojiri
This is required to send 1.5Mhz clock to Max98090 and get a right beep sound. BUG=chrome-os-partner:26609 TEST=Booted Nyan. Verified Max98090 can beep. Measured frequency by smartphone. BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ie3ff6df6759cb23d78dc05069553ddb4eb8e508a Original-Reviewed-on: https://chromium-review.googlesource.com/191791 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 2f75a147f26ac334fff174a1f9618a2bbe290fe9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If8c7871dc8202f98ccf23fb0afad1e7745fbf174 Reviewed-on: http://review.coreboot.org/7457 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-14nyan: Move some pinmux and clock/reset configuration to ROM stage.Gabe Black
To enable EFS, we need to be able to talk to the TPM and the EC before the RAM stage starts. That means we need to set up the pins for those busses, clock those controllers and take them out of reset. BUG=None TEST=Built for nyan, nyan_big, and nyan_blaze. Booted on nyan. With other changes which implement EFS on nyan, saw EC and TPM communication work when in vboot. BRANCH=None Original-Change-Id: Ic65d69fd42beec5f03084c8cb970927c2f69dfb6 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191390 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d9c176536b1e2eba47fdca90dd3346052573223e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id3117bd0c36f8b92d85cc0cefde2bed9d8de90d0 Reviewed-on: http://review.coreboot.org/7456 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-14t124: Clean up display init functionsJimmy Zhang
The existing display init functions were translated from a script. The new code will play the same functions but are cleaner and readable and easier to be ported to new panel. BUG=none TEST=build nyan and boot up kernel. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: Ic9983e57684a03e206efe3731968ec62905f4ee8 Original-Reviewed-on: https://chromium-review.googlesource.com/189518 Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 5998f991ea3069d603443b93c2ebdcdcd04af961) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Squashed to pass abuild nyan: Fix the build for big and blaze. The display code for the tegra124 was cleaned up recently, but only the nyan device tree was updated to match the new code, not big's or blaze's. This change copies nyan's device tree over to those other two boards which will get them building again. The settings may not be correct, but they'll be no less correct than they were before. I also updated the copyright date for nyan. BUG=none TEST=Built for nyan, nyan_big, nyan_blaze. Booted on nyan_big and verified the panel wasn't damaged by the new display code or settings. BRANCH=None Original-Change-Id: I75055a01f9402b3a9de9a787a9d3e737d25bb515 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191364 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ea235f23df31b4ca8006dcdf3628eed096e062b9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icdad74bf2d013c3677e1a3373b8f89fad99f616e Reviewed-on: http://review.coreboot.org/7454 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-14blaze: Create a nyan_blaze mainboard, copied from nyan_bigTom Warren
The nyan_blaze board will have different BCT .inc files, to be added/updated later. GPIOs and some devicetree stuff may also differ. BUG=None TEST=Built nyan, nyan_big and nyan_blaze. BRANCH=None Original-Change-Id: I8b16fc71346cf973983aa046096b79cb83ad4bb6 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/190721 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit bea753131e2247a90cc5359fa5f603026d66c7ce) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I435ae78da2f6c4f1a78fea8300b6285e52272535 Reviewed-on: http://review.coreboot.org/7453 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13AMD Trinity: Update the Trinity SMU FirmwareZheng Bao
Change-Id: I059047390e80e084f5d7763259d918446d96931e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7294 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-13intel: use crosscompiler readelf, instead of globalPatrick Georgi
readelf(1) may not know about the i386 flavor, or not be present at all under this name. Change-Id: I285df1f2098200b89918a4c4d3610e6427e86e01 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7448 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-13arm: Put assembly functions into separate sectionsJulius Werner
This patch changes the ENTRY() macro in asm.h to create a new section for every assembler function, thus providing dcache_clean/invalidate_all and friends with the same --gc-sections goodness that our C functions have. This requires a few minor changes of moving around data (to make sure it ends up in the right section) and changing some libgcc functions (which apparently need to have two names?), but nothing serious. (You may note that some of our assembly functions have data, sometimes even writable, within the same .text section. This has been this way before and I'm not looking to change it for now, although it's not totally clean. Since we don't enforce read-only sections through paging, it doesn't really hurt.) BUG=None TEST=Nyan and Snow still boot. Confirm dcache_invalidate_all is not output into any binary anymore since no one actually uses it. Original-Change-Id: I247b29d6173ba516c8dff59126c93b66f7dc4b8d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/183891 (cherry picked from commit 4a3f2e45e06cc8592d56c3577f41ff879f10e9cc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieaa4f2ea9d81c5b9e2b36a772ff9610bdf6446f9 Reviewed-on: http://review.coreboot.org/7451 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13vboot: provide empty vboot_verify_firmware()Aaron Durbin
In the case of CONFIG_VBOOT_VERIFY_FIRMWARE not being selected allow for calling vboot_verify_firmware() with an empty implementation. This allows for one not to clutter the source with ifdefs. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built with a !CONFIG_VBOOT_VERIFY_FIRMWARE and non-guarded call to vboot_verify_firmware(). Original-Change-Id: I72af717ede3c5d1db2a1f8e586fefcca82b191d5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/172711 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit c1e0e5c7b39c947b2a0c237b4678944ab86dd780) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: src/vendorcode/google/chromeos/chromeos.h Change-Id: Iaaa3bedbe8de701726c28412e7eb75de0c58c9c9 Reviewed-on: http://review.coreboot.org/7394 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13qemu-armv7: Minimal changes to pass compiling qemu-v7 platform.Hung-Te Lin
The ARM configuration files have been changed that we need more settings to run Coreboot on qemu-v7. Also fixed the incorrect Makefile settings that caused armv7 to try building with armv8 cache. BRANCH=none BUG=none TEST=make menuconfig # select qemu-armv7 make # pass qemu... # successfully boots to ramstage. Original-Change-Id: I4040e86ad1ff6e8ebd07cfe387c3f5a0e8941800 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/186080 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@google.com> (cherry picked from commit f2fab7383ee5352dab2d5f2b8a7d2d321d5944bc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibe18a1a87f036df148393f8dfc6a6d92dba4ac5c Reviewed-on: http://review.coreboot.org/7421 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13ipq8064: Make timer code compileVadim Bendebury
Commment out nonessential timer services and modify the source code to cleanly build in coeboot environment. Do not remove dead code just yet, these functions might be necessary later. Need to rename the soc timer.h to prevent collisions with timer.h in the top level include directory. Currently build timer code for ramstage only. BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: Ib10133ccb42697840708845a8ea6d75ceeaeb3d5 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194067 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 987ce95220953c16216d1e1d70d5a941d05fc9bc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia9cf175da11c70709354def5e51bf79df4fda2fe Reviewed-on: http://review.coreboot.org/7269 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13ipq8064: Configure proper bootblock stack and load addressVadim Bendebury
The SBL3 currently seems to be preventing the bootblock from being loaded into the IMEM. As a temporary measure, map bootblock into DRAM (as it is available after SBL2 finished running) and specify the correct stack space. BUG=chrome-os-partner:27784 TEST=not much testing yet, just verify 'emerge-storm coreboot' still succeeds. Original-Change-Id: Ibe9d4911ad22ada1bbd01af54a2ef80009df3a28 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196168 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 950323d6091c3b795034c24a08b6c176f56f0e0f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib3ec21f2cb4058b3e3cc82864de89dadf3b6aa84 Reviewed-on: http://review.coreboot.org/7268 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13Use sbl blobs from a private locationVadim Bendebury
The sbl blobs could not yet be published, they have been moved to a private location. Update coreboot to pick up the blobs at the correct place. BRANCH=None CQ-DEPEND=CL:195003 BUG=chrome-os-partner:28059 TEST=manual $ emerge-storm coreboot succeeds Original-Change-Id: I8c4163bc978307e41c156ef9f7f2a211d57db7a8 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194997 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 1a1848b00acfc2f58990559e824ea9c13c3c239c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If597ebbfd348039d578c99cd7a8e3c4bcbf60c10 Reviewed-on: http://review.coreboot.org/7267 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13ipq806x: Add support for GPIO operationsFurquan Shaikh
Basic support for ipq806x GPIO CFG and IO reg operations Reference: IPQ806x PRM, u-boot arch-ipq806x/gpio.* BUG=None BRANCH=None TEST=Compiled successfully Original-Change-Id: Ia0a9f288de3ac7bdb1cd4acbf44ba46af4dcc4e2 Original-Reviewed-on: https://chromium-review.googlesource.com/194217 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0b48e6655e63b467fe79d52149be01d23a2a3712) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I09e222f35b4b20c8eb901f33cf4451085c4c99cc Reviewed-on: http://review.coreboot.org/7266 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan*: Switching unused pin to GPIONeil Chen
Switching unused pin to GPIO to avoid SPI1 conflicting. BUG=chrome-os-partner:26701 BRANCH=none TEST=Built and boot on Nyan Original-Change-Id: I7de5b8d015f6d02baadd41b1b272dfc49d17c376 Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/189970 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit edf12f441adb2395fe2718bed98d79eb3b128f6b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I562b58ba02825b16d374d9f0328f6c75431edc63 Reviewed-on: http://review.coreboot.org/7420 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: big: Only delay when and as long as necessary in the PMIC setup code.Gabe Black
The PMIC setup code was unconditionally waiting for 10ms after each register write. It might be possible for there to be an excess of current from lots of rails switching around at the same time, but we can avoid that with a much shorter delay in a few strategic places. This change also moves the write to LDO3 to just under SD1 because LDO3 should track SD1. The duration and position for the delays and moving LDO3 were provided by Dan Coggin at nvidia. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan rev1. Measured a 230 ms decrease in boot time. BRANCH=None Original-Change-Id: I14805bf1b6242bdd0b286f37ae7d635c03909677 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/189016 Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Daniel Coggin <dcoggin@nvidia.com> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 06c4d346deeb47809cd88655a9fa6712ceef9491) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3ce0bdeb4ee60499f6c192fe0803a4cab3d7a8af Reviewed-on: http://review.coreboot.org/7419 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: big: Set the i2c controller frequencies appropriately.Gabe Black
These had been set to something fairly random which results in a very slow clock on the bus itself. The new settings take into consideration the speed the devices on the bus can run at. The TPM can't seem to handle speeds above 40KHz, but some documentation suggests that it should be able to handle up to at least 100KHz. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan rev1. Built for big. BRANCH=None Original-Change-Id: Iee98957c7e492c7dd08b071aeef3cce75c4a9e56 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/189015 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit afca97a29aeb99d3899b713d0e57a3b3214f0d96) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iab0c50b2119ac322252564354c90b5cb2d255c97 Reviewed-on: http://review.coreboot.org/7418 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13tegra124: Add a macro specifically for configuring the I2C controller clocks.Gabe Black
The divider for the I2C clocks works differently than for other IP blocks and needs to be set up to reflect that. There's also a large internal divider which means you have to do extra calculations to determine what the frequency of the bus itself will be based on the I2C controller clock. The new macro takes the desired frequency of the bus itself and figures everything else out. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan rev1 using this function to set up the i2c busses. BRANCH=None Original-Change-Id: Ib62a5659bcc0d0e15de41887514ae8efb8c8129a Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/189014 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 24714399a9a89cf33ad20ee43da87e9b04ba394c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9a1eabb16fdb27fb813fe6bc56cdcc593eca166e Reviewed-on: http://review.coreboot.org/7417 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13tegra124: Fix some bugs in the clock configuration macros.Gabe Black
There were some missing parenthesis and some extra semicolons which this change adds and removes, respectively. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan rev1. Verified that the same frequency calculated differently results in the same settings. Before operator precedence would pull apart the frequency calculation and use the pieces in the wrong order. BRANCH=None Original-Change-Id: I843d4ae9f7a2ae362926d94b6b77ef31d350a329 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/189013 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 462e61ad898a4d6a99c1d161d77bde245c5b1f5c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifce3aac262cf5e2ec0496c5b3ad894bf6f0f9a46 Reviewed-on: http://review.coreboot.org/7416 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13t124: Skip PLLP init to 408MHzJimmy Zhang
PLLP is configured to 408MHz by hardware on T124. Init PLLP is needed only when to configure it other than 408MHz. BUG=none TEST=build nyan and boot kernel. Original-Change-Id: I8b1abf510ab886e7fddea8864a6d36f12529880e Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188849 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit d32124cb7562cbce1bb929c3e5f238b13a27b752) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I617f77444a8dd97b20763b50066a1298d3b97724 Reviewed-on: http://review.coreboot.org/7415 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13t124: nyan: Enable lock bit on pllJimmy Zhang
A PLL (Phase-Locked Loop) clock must be locked before it is assigned as clock source. Otherwise, this clock is unreliable. Before: c base(60006080): 48003201, misc(6000608c): 03000000 x base(600060e0): 40009e01, misc(600060e4): 00000000 p base(600060a0): 40002201, misc(600060ac): 00000200 u base(600060c0): 40005001, misc(600060cc): 00000300 d base(600060d0): 48011b0c, misc(600060dc): 40400800 dp base(60006590): 58305a01, misc(60006594): 40000000 After: c base(60006080): 48003201, misc(6000608c): 03000000 x base(600060e0): 48009e01, misc(600060e4): 00040000 p base(600060a0): 5801980c, misc(600060ac): 00040800 u base(600060c0): 48005001, misc(600060cc): 00400300 d base(600060d0): 48011b0c, misc(600060dc): 40400800 dp base(60006590): 58305a01, misc(60006594): 40000000 BUG=None TEST=build nyan and boot Original-Change-Id: I7e5a2eeb5b17f761e0c462ec68a8b221f327fedc Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188447 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 7e8e2854b2b7d1ed20d74891c3d19b6c3dd41c55) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ief9efa6937af26fe1a10a7b360fc2f5477416b97 Reviewed-on: http://review.coreboot.org/7414 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13Nyan: Set DMA Reserve to 2MBDaisuke Nojiri
When using LPAE, the address space is split to 2MB blocks. This change makes the space reserved for DMA consistent with the block size. TEST=Booted nyan with and without LPAE. Built nyan_big. BUG=None BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I75c77484f6ca9f23b583ef651956d0265a9b4474 Original-Reviewed-on: https://chromium-review.googlesource.com/188571 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 16a40a48c2e3fc131a348d5e7d377d26f4b20aaf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib79c9491dc504d28f811bbf0d91cffd292f5eb86 Reviewed-on: http://review.coreboot.org/7413 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13tegra124: fix OSC initialization on LP0 resumeAndrew Bresticker
Add a missing "~" so that we mask off just OSC_XOFS field and not the rest of the register. BUG=chrome-os-partner:26326 TEST=XHCI sometimes works after LP0. BRANCH=none Original-Change-Id: I2df2387dbad6920d36aa2ae5e6cd91e9ec42fa08 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/188897 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit bdbe9ead46fa883618a4acedd1feaf676e2eb29b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic853e737fc106527eb3bb15c25bf801a36bbff57 Reviewed-on: http://review.coreboot.org/7412 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13tegra124: fix PLLU parametersAndrew Bresticker
Fix the PLLU parameters to match the recommended values from the TRM, and the values used by the kernel and LP0 blob. This includes adding support for setting an LFCON value. It appears that changing the PLLU parameters across suspend/resume causes XHCI stability issues after resume. BUG=chrome-os-partner:26326 TEST=XHCI works after LP0 suspend/resume on Nyan. BRANCH=none Original-Change-Id: Ia4af12fefeebe607803e7f2f03ee4802367b82c3 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/188752 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit bbc8d92eb462e165c2378bcb3055a3a74b47a19b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I687d1709befc2f5dec094ee423f2ff824412996e Reviewed-on: http://review.coreboot.org/7411 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: Select the CD570M Tegra124 model.Gabe Black
This indirectly selects an appropriate PLLX frequency so the main CPUs run as fast as they can but not faster. BUG=chrome-os-partner:25467 TEST=Booted on nyan rev1. BRANCH=None Original-Change-Id: Ibe61f5e35246b272771debf4fdf90c79b21eb5d0 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188603 Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 947ecbce3cb6e4d7ab07d3ffd5b4694ca6270cde) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9163ddea7f246ae7207a8a715ebae2c9627a7e37 Reviewed-on: http://review.coreboot.org/7410 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13tegra124: Make the PLLX frequency selectable by model.Gabe Black
The PLLX provides the clock for the main cores which can run at different max frequencies depending on the specific model of Tegra124. This change makes it possible to select a model which will, in turn, select a frequency for PLLX. The default is 2GHz which is the lowest maximum frequency. BUG=chrome-os-partner:25467 TEST=Booted on nyan rev1. Verified that the selected PLLX frequency was 2GHz. With a change that selects the right model for nyan, verified that the corresponding frequency was selected. BRANCH=None Original-Change-Id: Iee3a615083dee97ad659ff41cbf867af2a0c325d Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188602 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1282015048420a518e6c6959ce982be70378211a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I448a830f3184ad1afeadbd1c2974c7a27b03a923 Reviewed-on: http://review.coreboot.org/7409 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: Update 924MHz BCT w/latest qual'd cfg, use 924 as default speed for 2GBTom Warren
BUG=none BRANCH=nyan TEST=built and booted coreboot on my Nyan-rev1, browsed, ran Youtube vids, WebGL experiments, etc. Everything seemed OK. Original-Change-Id: I877680c9329ed96a0b602f0690acaa12079786d7 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188550 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit b6ca59e9db26f7422fa43ade889c921257a36851) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If166938f241e2a4a8670bfce2df6591b4b71ff67 Reviewed-on: http://review.coreboot.org/7408 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: nyan_big: Mark the address range covering the SRAM as cachable.Gabe Black
The SRAM is very likely faster than going all the way out to DRAM for data, but I don't think it's part of the cores themselves and won't be as fast as the L1 caches. Enabling caching for this region reduces the time it takes to get to the payload by about 75% when serial output is disabled and the main part of display init is commented out. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan. BRANCH=None Original-Change-Id: I7ff26dea9d50e7d9a76e598e5654488481286b35 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188459 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ac8b9b30490d511ca1b207af6845d50e08ac130f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If79dcd1b116f30b778788ba4fd45d362ff5d8e6e Reviewed-on: http://review.coreboot.org/7407 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: Add 4GB bct supportJimmy Zhang
Replace sdram entry 1 with valid configurations since nyan 4GB board uses RAM_CODE 1. BUG=none TEST=Flash and boot new image.bin. Console shows "RAMCODE=1" and "Total SDRAM (MB): 4096" BRANCH=none Original-Change-Id: Ia872bd7849f1b58075e1f97bf300e081293cb0d4 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/187450 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit f19e2ea3dd4d314b7540c7cf9a11d7af289d24d0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4914c3811b13c8cee0577101bc0c8ee32a0a5b81 Reviewed-on: http://review.coreboot.org/7406 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: big: Check dram_end when setting up caching in ROM stage.Gabe Black
When setting up caching on nyan and big, we would set the region after DRAM to the end of the address space as uncachable. DRAM may actually extend beyond the end of the address space, so that may result in address aliasing or other problems. This change adds a check to make sure there's actually space there. BUG=None TEST=Built for big. BRANCH=None Original-Change-Id: Ic0a98550222f9dfc0aeafd67a2dd1c0c8f4ece44 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/186769 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1866a4d2a001beb97779b611b8b69c63175048f4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If1ca8b5bd4efab8962e03c0d9eaa70c0327ea6b5 Reviewed-on: http://review.coreboot.org/7405 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13libpayload: Add minimal support for PL011 UARTMarcelo Povoa
This creates a new PL011 config variable which avoids the infinite busy wait on serial_putchar() because the register mapping is not compatible with current implementation. BUG=None BRANCH=none TEST=printf() works on the PL011 based ARMv8 foundation model Original-Change-Id: I9feda35a50a3488fc504d1561444161e0889deda Original-Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/187020 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 85779a34a161c324cc8af995ada4393137275f20) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: payloads/libpayload/Config.in payloads/libpayload/drivers/serial.c Change-Id: I23c8b3728cd7d2d7692b3e86a679e061e88f7bb5 Reviewed-on: http://review.coreboot.org/7422 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13libpayload: timer: Move the timer drivers from depthcharge to libpayload.Gabe Black
These drivers are needed right away and never really fit into depthcharge's driver model anyway. CQ-DEPEND=CL:194064 BUG=None TEST=Built and booted nyan, link, and peach_pit and verified that timer values in cbmem were reasonable. Built for nyan_big, nyan_blaze and daisy. BRANCH=None Original-Change-Id: Ia7953cfece57524262a6c7d6537082af7a00f4d6 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194058 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit f30a410f0a248c93bc34f5868af1596bf8ce3cdd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I782d20f3cd63210a87c712643c7a53753f5ef301 Reviewed-on: http://review.coreboot.org/7225 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-13libpayload: usb: Remove automatic clear_stall() calls from transfersJulius Werner
We've recently fixed a problem where an external hard drive would choke due to one too many CLEAR_FEATURE(HALT) commands in the XHCI stack with "libpayload: usb: xhci: Fix STALL endpoint handling". Clearing stall conditions from within the transfer function is wrong in general... this is really something that is host controller agnostic and should be left to the higher-level driver to decide. The mass storage driver (the only one that should really encounter stalls right now) already contains the proper amount of clear_stall() calls... any more than that is redundant and as we found out potentially dangerous. This patch removes automatic clear stalls from UHCI and OHCI drivers as well to make things consistent between host controllers. BUG=chromium:192866 TEST=None. I could borrow the original hard drive from Shawn and compile a Snow to only use the OHCI driver to reproduce/verify this, but alas, I am lazy (and it's really not that important). Original-Change-Id: Ie1e4d4d2d70fa4abf8b4dabd33b10d6d4012048a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193732 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit d46e183f3e7e0b0130becdefa6fd3ef8097df54b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie8f4ab3db8ec0d9a2d1e91c62967833e59c46700 Reviewed-on: http://review.coreboot.org/7223 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13libpayload: usb: Fix up usb_shutdown() code pathsJulius Werner
This patch combines a few minor fixes and refactoring to the various host controller and root hub drivers to ensure they all do the right thing on a call to usb_exit(). It puts a usb_detach_device(0) call into detach_controller() so that the HCD doesn't need to remember to tear down the root hub itself, and makes sure all root hubs properly detach the subtree of devices connected to their ports first (as generic_hub and by extension XHCI had already been doing). It also fixes up some missing free() calls and replaces most 'ptr = malloc(); if (!ptr) fatal()' idioms with the new x(z)alloc(). BUG=chromium:343415 TEST=Tested EHCI on Big and OHCI, EHCI, and XHCI on Snow. Could not test UHCI (unless anyone volunteers to port coreboot to a ZGB? ;) ), but the changes are really tame. Original-Change-Id: I6eca51ff2685d0946fe4267ad7d3ec48ad7fc510 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193731 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 5791b546e5a21a360d0c65888a5b92d5f48f8178) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I00138f0aeceb12ed721f7368c7788c9b6bee227d Reviewed-on: http://review.coreboot.org/7222 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13libpayload: Remove config.pantherMarc Jones
config.panther was added in a chromium upstream patch. We don't want mainboard specific configs in libpayload, so remove it. Change-Id: Ibfb894a0262911c13e88bc161749b78e2b5c5185 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7450 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13libpayload: Update defconfigsMarc Jones
Update x86 and ARM defconfig. Adds default N to specific timer and serial drivers. Change-Id: Ida6b953565dc6053729c2a72c6342d86596c599b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7449 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
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