coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-06-27	northbridge/amd/pi: Arithmetics is not logic	Stefan Reinauer
2017-06-27	README: Update requirements	Stefan Reinauer
2017-06-27	amd/amdfam10: Remove dead code	Stefan Reinauer
2017-06-27	drivers/spi: Don't disable non-existent warnings on clang	Stefan Reinauer
2017-06-27	vendorcode/amd: Satisfy clang's bracing requirements	Stefan Reinauer
2017-06-27	vendorcode/amd: Make compiler intrinsics clang friendly	Stefan Reinauer
2017-06-27	libpayload/drivers/usb/ohci_private.h: Add brackets around macro	Elyes HAOUAS
2017-06-27	mainboard/lenovo/x220: allow to use libgfxinit	Alexander Couzens
2017-06-27	include/device: Add pci ids for Intel CNL	Lijian Zhao
2017-06-27	cpu/x86/smm: allow SSE instructions in SMM modules	Aaron Durbin
2017-06-27	sb/intel/bd82x6x: Fill in acpi_name	Patrick Rudolph
2017-06-27	nb/intel/sandybridge: Fill in acpi_name	Patrick Rudolph
2017-06-27	util/blobtool: add spec files for DDR3 SPDs	Martin Roth
2017-06-27	3rdparty/chromeec: Update submodule to upstream master	Martin Roth
2017-06-27	mb/google: Remove ChromeEC builds for auron and rambi	Martin Roth
2017-06-27	mainboard/google/poppy: Update world facing camera sensor	V Sowmya
2017-06-27	mainboard/google/poppy: Add clock frequency for camera sensors	V Sowmya
2017-06-27	util/crossgcc: Fix building gcc 6.3.0 with clang	Patrick Georgi
2017-06-27	crossgcc: Fix building with clang++ in the presence of gcc	Patrick Georgi
2017-06-27	libpayload: corebootfb: Add null check for framebuffer address	Duncan Laurie
2017-06-27	lib/coreboot_tables: Zero framebuffer structure	Duncan Laurie
2017-06-27	soc/intel/skylake: storage: Use word access for power state registers	Duncan Laurie
2017-06-27	soc/intel/skylake: storage: Add 2ms delay before exiting D3	Duncan Laurie
2017-06-27	3rdparty/blobs: Update submodule	Martin Roth
2017-06-26	libpayload: Enable building libpayload with march=i586	Lee Leahy
2017-06-26	buildgcc: Allow environment to override $CC/$CXX	Nico Huber
2017-06-26	vendorcode/amd: Drop multiple copies of gcc-intrin.h	Stefan Reinauer
2017-06-26	vendorcode/amd: Unify gcc-intrin.h	Stefan Reinauer
2017-06-26	libpayload/configs: Add configuration for Galileo	Lee Leahy
2017-06-26	soc/intel/fsp_baytrail/include/soc/pci_devs.h: Add brackets around macro	Elyes HAOUAS
2017-06-26	amd/gardenia: Fix most checkpatch errors	Marshall Dawson
2017-06-26	amd/gardenia: Switch to soc/amd/stoneyridge	Marc Jones
2017-06-26	soc/amd/stoneyridge: Add northbridge support	Marc Jones
2017-06-26	soc/amd/stoneyridge: Add CPU files	Marc Jones
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones
2017-06-26	rockchip/rk3399: update the ddr 200MHz frequency configuration	Caesar Wang
2017-06-25	crossgcc/buildgcc: update file location code	Martin Roth
2017-06-25	xcompile: Fix clang compiler runtime detection	Stefan Reinauer
2017-06-23	soc/intel/skylake: Remove post SMM Relocation uCode loading	Barnali Sarkar
2017-06-23	soc/intel/skylake: Use CPU MP Init Common code	Barnali Sarkar
2017-06-23	soc/intel/common/block: Add common MP Init code	Barnali Sarkar
2017-06-23	siemens/mc_apl1: Enable decoding for COM 3 on LPC	Mario Scheithauer
2017-06-23	siemens/mc_apl1: Disable XDCI	Mario Scheithauer
2017-06-22	crossgcc: cosmetic overhaul of output	Stefan Reinauer
2017-06-22	crossgcc: Rename print_stable to print_supported	Stefan Reinauer
2017-06-22	cpu/allwinner/a10/clock.h: Add missing bracket	Elyes HAOUAS
2017-06-22	sb/amd/rs780/gfx.c: Add brackets around macro	Elyes HAOUAS
2017-06-22	cpu/x86: Use do while loop	Paul Menzel
2017-06-22	device/dram/ddr3.h: Add brackets around macro	Arthur Heymans
2017-06-22	nb/intel/sandybridge/raminit: Fix dual DIMM command rate	Patrick Rudolph