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2016-03-18coreinfo: Allow numbers in addition to F keysStefan Reinauer
When using coreinfo on a serial console (at least with gtkterm, picocom and minicom on Ubuntu 15.10) you can't send F keys to the payload. Allow 1..9 for F1..F9 Change-Id: Ie3a11fa1de57c7345737a1ccaff177f407cd5e48 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14065 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-18src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI tableJacob Laska
The previous implementation assumed the CPU physical address size to be 40 which is not true of all platforms. Use an existing function to obtain the correct CPU physical address to report in the DMAR ACPI table. Change-Id: Ia79e9dadecc3f5f6a86ce3789b213222bef482b3 Signed-off-by: Jacob Laska <jlaska91@gmail.com> Reviewed-on: https://review.coreboot.org/14102 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-03-18mtrr: Define a function for obtaining free var mtrrFurquan Shaikh
Instead of hard-coding var mtrr numbers in code, use this function to identify the first available variable mtrr. If no such mtrr is available, the function will return -1. Change-Id: I2a1e02cdb45c0ab7e30609641977471eaa2431fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14115 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-18google/oak: Enable RAM_CODE_SUPPORTYidi Lin
BRANCH=none BUG=chrome-os-partner:50820 TEST=check /proc/device-tree/firmware/coreboot/ram-code Change-Id: I5ecf45cada7f8999ad607487d5d9281c4fb659ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 79d2f0e183a2bde70817d673ae315709f46e3361 Original-Change-Id: I35e91b4e29f8e09acd74770715c96cf7320ac22c Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332564 Original-Reviewed-by: Milton Chiang <milton.chiang@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14104 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-18mediatek/mt8173: mt6391: set VSRMCA7 to HW control by SRCVOLTENhenryc.chen
When system enters suspend, SPM will pull SRCVOLTEN low to turn off some power rails. VSRMCA7 should follow this pin to turn on/off the power. BRANCH=none BUG=none TEST=verified on Oak rev5 Change-Id: I9d81f855a74fe02a59246ce0c6a7f0e162b9fd0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d92fb1029b810028138eb91b064b63a58b82602f Original-Change-Id: I37ff0694cbd7b17d5a1ae172c463b4e6aae2b99c Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332345 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14103 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-17build system: Allow overriding the path to the futility binaryPatrick Georgi
Change-Id: I84e68e8407149780769c3e6a1148c175e42d1025 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/14100 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16cpu/x86: compile earlymtrr.c code for romstage as wellAndrey Petrov
In order to make this work earlymtrr.c needed to be removed from intel/truxton/romstage.c. It's not a ROMCC board so there's no reason to be including .c files. Change-Id: If4f5494a53773454b97b90fb856f7e52cadb3f44 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16cpu/x86/mtrr: remove early_mtrr_* functionsAaron Durbin
I see no user of any of this code. Remove it. Change-Id: I776cd3d9ac6578ecb0fe6d98f15611e4463afb7a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14098 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin
The Intel i3100 northbridge code is the only user of cache_ramstage(). Therefore, place it next to the sole consumer. Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14097 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16libpayload: recreate config filesStefan Reinauer
Add all the default options with: for i in configs/* do cp $i .config make savedefconfig mv defconfig $i done This also switches to minimal config files instead of the full configuration files that were previously checked in. Change-Id: If18a32eca4df9e1dfeb0e212b652d972cea8e4b8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14077 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-03-16coreinfo: Rename libpayload variablesStefan Reinauer
LIBCONFIG_PATH -> LIBPAYLOAD_PATH LIBPAYLOAD_DIR -> LIBPAYLOAD_OBJ Change-Id: Idd9947bac594f5b109b877aefac70b1a1d2336eb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14099 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-16rockchip: update make_idb.pyhuang lin
make_idb.py only support RK3288 before, add chip parameter, so we can support RK3399 either. Change-Id: I6811acb7f0cdaf1930af9942a70db54765d544d5 Signed-off-by: huang lin <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/13913 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-16skylake mainboards: Configure gpio PADRSTCFG to PLTRSTNaresh G Solanki
With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over pltrst and hence configuring PADRSTCFG to PLTRST to prevent IRQ strom after S3 resume. BRANCH=glados BUG=chrome-os-partner:50536 TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed after S3 resume. Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68 Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329453 Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331174 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16util/nvidia/cbootimage: update to latest masterPatrick Georgi
This includes a fix that allows using cbootimage with paths containing the "@" sign, which happens sometimes in jenkins configurations. Change-Id: I83154afa35b6d24449e713e57031b1a93d7ac748 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14090 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16parade/ps8640: Clean upPatrick Georgi
Sort out some style issues that were identified by Paul. Change-Id: I9ed946ae613c87234f8c9824eb14b8d28909dfcf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14064 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-15coreinfo: Use tinycursesStefan Reinauer
When using PDcurses over a serial line, the background of coreinfo is not properly cleared. Hence use tinycurses, which was the only option when coreinfo was developed. Change-Id: I15bb6eb552cf924de98d09ef63be33ecf336c526 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14067 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-03-15pcengines/apu1: Enable USB overcurrent detection.Tobias Diedrich
The two external USB ports and the internal USB header have overcurrent protection chips with the low-active overcurrent signal connected to the chipset. The power-on default for this register disables the software detection of overcurrent conditions. After setting the register Linux correctly shows the overcurrent condition in the kernel log (tested by shorting the 5v and gnd lines on J14 / the internal USB header): [ 2015.229921] usb usb1-port3: over-current condition [ 2015.449925] usb usb1-port4: over-current condition Simlar for the external ports: [ 256.237916] usb usb1-port1: over-current condition [ 256.458084] usb usb1-port5: over-current condition Note that each signal is shared between two ports: usboc0#: External ports (port1/5) usboc1#: Internal ports (port3/4) Change-Id: I02d498053b8ec61dc206e74a96c4a1dcfd4fae92 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/14084 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15lenovo: add config ONBOARD_VGA_IS_PRIMARYPatrick Rudolph
Fix for the T4xx and T5xx series. It does not apply to X2xx/X6x series as those have only one GPU, which is always connected to the display. The T6x series needs special care not handled with this patch. Without ONBOARD_VGA_IS_PRIMARY the onboard GPU would be deactivated in case a dedicated GPU is found and active, leaving the system without a working display. Change-Id: I94d1700e9afb75de83a4f2ed1ff53ba3b0559ae1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14031 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2016-03-15google/oak: add table for 4GB configurationPH Hsu
BRANCH=none BUG=chrome-os-partner:49229 BUG=chrome-os-partner:50806 TEST=power on to kernel on Oak Rev3 with 4GB dram Change-Id: I32fa881df12eb9b7f66086904aebde3dd1483fbf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94c8b7ad911c93c4325113e7afc009f2f81d2275 Original-Change-Id: Ia3640882a46e695550e679dc70611855b64a560f Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331811 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14089 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15mediatek/mt8173: Enable 4GB modePH Hsu
If the system is using 4GB of memory, enable 4GB mode in the memory controller. Change-Id: I4d0f8ad8d43ff45dd786f4244b11c0879d2088cd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94c8b7ad911c93c4325113e7afc009f2f81d2275 Original-Change-Id: Ia3640882a46e695550e679dc70611855b64a560f Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331811 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14088 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15google/oak: Remove EC_SUSPEND_L from APKoro Chen
This pin is not used anymore since Rev5. BRANCH=none BUG=chrome-os-partner:49375 TEST=make and boot on Rev4/5 Change-Id: I3c775eb2b5e05256523bfd8be814e516944a2f90 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a87e3babe28413bd879a2d95d4612a5b6b541419 Original-Change-Id: I87972ff8961309ecdad03639e1b6fac1da119cd7 Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331810 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14087 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15Makefile.inc: Add toupper, tolower, and ws_to_under macrosMartin Roth
Add a few additional macros that can be used throughout the coreboot makefiles. tolower: returns the value in all lowercase toupper: returns the value in all uppercase ws_to_under: returns the value with any whitespace changed to underscores Change-Id: Icd0e6586481d8f229af0e899e0c94ef7c5c672c3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14093 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-15payloads: Enable building depthcharge as part of the coreboot buildStefan Reinauer
For CHROMEOS builds, depthcharge can be built automatically. This dependency exists because depthcharge without vboot and subsequent signing of the image doesn't work very well, and both are keyed to that flag as well. Change-Id: Id0195bd3b4e454f382782106d6512469106daac5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/10924 Tested-by: build bot (Jenkins)
2016-03-15x86: Drop CONFIG_COMPILE_IN_DSDTStefan Reinauer
This option is no longer needed, as FMAP support has been fully integrated in coreboot Change-Id: I6121b31bf946532717ba15e12f5c63d2baa95ab2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-15libpayload: Move base address, stack and heap size to KconfigStefan Reinauer
This will allow more payloads to use the standard linker script instead of implementing their own. Change-Id: Ie60120769829f427ceb722109d85859b61dbde31 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Make comment into help textStefan Reinauer
Change-Id: I8c8669e73e335e12cb3785cf84b878c305dd5929 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14068 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Fix ARM workaround codeStefan Reinauer
_LDFLAGS+="foo" did not work in my shell (bash on Ubuntu 15.10), so change it to _LDFLAGS="$_LDFLAGS foo". I'm mildly surprised that this ever worked. Change-Id: I59c10f34992240c6df2ec7f24aebc6daafb76493 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14076 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Add comment about ARM64 exception stackStefan Reinauer
Change-Id: I8b74cbf6bdde32c90ad0510e14e899711269e57f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14075 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15coreinfo: Pretty print RAM addressesStefan Reinauer
Instead of 500, print 0x00000500 in the ram dump module. Change-Id: Id250bd99f36dad4088ab88953fb371c400b4231b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14072 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Move MEMMAP_RAM_ONLY to generic optionsStefan Reinauer
MEMMAP_RAM_ONLY is not an architecture specific option, hence move it out of the architecture specific menu. Change-Id: Iaeef03ed8cbff930a580ad03b1e712087b48714e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Drop CONFIG_LP_CHROMEOSStefan Reinauer
This is adding complexity to the code more than it saves space, plus some of the tables could potentially be interesting outside of the ChromeOS context. Change-Id: I4bf24608f3e26d3b7871a5031ae8f03bc2c8c21f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Unify defconfigsStefan Reinauer
Bring defconfig and defconfig-tinycurses in sync, so that defconfig and defconfig-tinycurses only differ in the selection of the curses implementation. Change-Id: I739c5122b5aaaa2681055c845905721a0b2a11c1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14069 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15vendorcode/intel/Kconfig: Add broadwell_de symbol to fix lintMartin Roth
The Kconfig lint tool is complaining because this symbol doesn't exist. Create a temporary definition that can be removed when the chipset is added. Change-Id: I6a8abffcc91773aae16721ee1f48c4c64bd6b486 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14091 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-14genbuild_h: Fix numeric comparison to remove errorMartin Roth
Change the comparison of build_timeless from -eq to = This was generating an error if BUILD_TIMELESS wasn't set: util/genbuild_h/genbuild_h.sh: line 27: [: : integer expression expected This wasn't causing the script to fail, and won't even if 'set -e' is added to the script because the error happens inside an 'if' clause, which is specifically excluded from failue on 'set -e'. Change-Id: I6a4e147ece23e83ee682d72db35be9e5d4088c78 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14080 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-14util/cbmem: Scale time stamp values correctlyAaron Durbin
Commit c49014e (timestamp: add tick frequency to exported table) refactors the code, but forgets to correctly scale the frequency to megahertz, where the value is read from sysfs, so that printing time stamp information shows milliseconds instead of microseconds, as can be seen on the output `cbmem -t` for the ASRock E350M1 below. ``` 0:1st timestamp 515 10:start of ramstage 515 (0) 30:device enumeration 515 (0) 40:device configuration 610 (94) 50:device enable 614 (4) 60:device initialization 624 (9) 70:device setup done 639 (14) 75:cbmem post 844 (205) 80:write tables 844 (0) 90:load payload 849 (4) 15:starting LZMA decompress (ignore for x86) 849 (0) 16:finished LZMA decompress (ignore for x86) 869 (20) 99:selfboot jump 869 (0) Total Time: 350 ``` So scale the return value correctly to megahertz, by dividing it with 1000. ``` 0:1st timestamp 515,655 10:start of ramstage 515,655 (0) 30:device enumeration 515,663 (7) 40:device configuration 610,620 (94,957) 50:device enable 614,680 (4,059) 60:device initialization 624,618 (9,938) 70:device setup done 639,553 (14,934) 75:cbmem post 844,707 (205,154) 80:write tables 844,710 (2) 90:load payload 849,532 (4,821) 15:starting LZMA decompress (ignore for x86) 849,655 (123) 16:finished LZMA decompress (ignore for x86) 869,903 (20,247) 99:selfboot jump 869,922 (19) Total Time: 354,261 ``` Change-Id: Iea032c62487c7946b6194a90268755034c6350df Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/14086 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-03-14vendorcode/intel/fsp1_0: Add Broadwell-DE SoC vendor codeYork Yang
Initial vendor codes to support Broadwell-DE SoC. This is FSP 1.0 based project and is based on Broadwell-DE Gold release. Change has been verified on Intel Camelback Mountain CRB. Change-Id: I9262c9d70a58f0c7427f0658948adf080f2f6d8f Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: https://review.coreboot.org/14030 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-14intel/fsp_baytrail: Enable LPSS in ACPI modeBen Gardner
This change fixes LPSS ACPI mode. Previously, enabling ACPI mode would result in unusable devices, as the resources were set to 0 and the devices were disabled. lpss.c was copied from intel/baytrail with a few minor adjustment for the different config structure. ACPI mode requires setting PcdLpssSioEnablePciMode==LPSS_PCI_MODE_DISABLE and applying the patch that disables clearing gnvs. https://review.coreboot.org/#/c/14040/ This doesn't handle the case where the FSP has PcdLpssSioEnablePciMode set to disable and the devicetree set to default. Change-Id: I12fffea3820ed948defe7a4f11af6b6363402560 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/14042 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-14intel/fsp1.1: Mark graphics init done after SiliconInit phaseDuncan Laurie
If the VBT was provided to the FSP GOP driver then graphics init will be done as part of SiliconInit step and we can mark that when it is completed. This will result in the "oprom" flag being set properly in the coreboot gpio table and the netboot firmware will have video. [pg: avoided conflict with Quark that comes without silicon_init_params.GraphicsConfigPtr] BUG=chrome-os-partner:50864 BRANCH=glados TEST=boot image.net.bin on chell and get working graphics without being setuck in a reboot loop thinking graphics needs to be started when it already has been. Change-Id: I0e481b4be57096ed5c60d78e3fa00f3bb2a4eae1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 089d93c712431d1b5923e844137c558994555e95 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331301 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-(cherry picked from commit eeb9d470d8118422feb39ca71106972f2882e240) Original-Change-Id: Ic59bad27eb9f184ca3eba24643851bfadfe23ab5 Original-Reviewed-on: https://chromium-review.googlesource.com/331355 Reviewed-on: https://review.coreboot.org/13986 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-03-13nb/amd/mct_ddr3: Use correct initial UI setting during DRAM trainingTimothy Pearson
Rebasing change I3be808db5d15ceec4c36d17582756b01425df09a did not take into account the default UI setting introduced in change I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 , causing DRAM instability and occassional failure to boot. Use the correct 1UI value for the modified function semantics. Change-Id: I9fd24cf83e4c4083c6e467d49021c98e5f5f2c53 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14073 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13coreinfo: Remove the LAR moduleJonathan Neuschäfer
Since libpayload's LAR support was dropped in If6e36569cd, this module doesn't compile anymore. Change-Id: I98f25613a1728e94704d9e9ccb65fd6ba33968b9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14037 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-13util/ifdtool: add option to change chip densityJan Tatje
Adds -D / --density option to change the chip density. This is only implemented for IFD version 1 as I do not have an IFD version 2 to test this. Density of both chips is changed by default, but a chip can be selected using -C / --chip. Change-Id: Iba7affbf6cbefa3147b7b0e019298d905e694716 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/14032 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13intel/fsp_baytrail: Fix LPE initialization and enable ACPI modeBen Gardner
This change properly assigns resources to the LPE (Low Power Engine for Audio) and enables ACPI mode. lpe.c was copied from intel/baytrail with a few minor adjustment for the different config structure. ACPI mode requires setting LpeAcpiModeEnable=LPE_ACPI_MODE_ENABLED and applying the patch that disables clearing gnvs. https://review.coreboot.org/#/c/14040/ Change-Id: I3fff9aa158bde88e571082642d4f985a5ae1976e Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/14041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13intel/fsp_baytrail: Don't clear gnvs in acpi_init_gnvs()Ben Gardner
That wipes out all previously stored settings and breaks running devices in ACPI mode. This more closely matches what is done in intel/baytrail. Change-Id: Ie993c9f9e1eceb73d016d2df72770a27abb26ec1 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/14040 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13abuild: Add option of starting with an existing defconfig fileMartin Roth
We want to start testing builds with additional Kconfig options to try to get more coverage. This will allow us to enable various options to test without having to add each individual option to the abuild script. Change-Id: I9bb2bb6f38589e3bcc1282dc4cad51cf6f5149aa Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14016 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-13northbridge/intel/i3100: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i3100 boards in the chipset. Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13786 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13northbridge/intel/i82810: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i810 boards in the chipset. Change-Id: Ifda7dcfdf37b6affce838ee96ca6382b2d4be8c3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12northbridge/intel/i82830: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i830 boards in the chipset. Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12nb/amd/mct_ddr3: Consolidate duplicated codeTimothy Pearson
read_dqs_read_data_timing_registers() and read_read_dqs_timing_control_registers() served essentially the same function but had slightly different semantics, causing confusion and needlessly complex Family15h code. Consolidate both into read_dqs_read_data_timing_registers() and adjust surrounding code to match new semantics. Change-Id: I3be808db5d15ceec4c36d17582756b01425df09a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13994 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12payloads/seabios: Add "git revision" to the SeaBIOS version menuAntonello Dettori
Add an option to specify a git revision from which to build SeaBIOS. Change-Id: Ifbf3b82e784f79395ab7cd07c5804f72928d7640 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/13937 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins)
2016-03-12intel/skylake: Do not log wake source on resetDuncan Laurie
Skip logging a wake source when just resetting without coming from S3 or S5 state. This will prevent the occasional spurious event like PCI PME from showing up in the event log. BUG=chrome-os-partner:40635 BRANCH=glados TEST=run warm reboot teset on chell and ensure no wake source is logged Change-Id: If739034dc9022b37c90b9cc849a00c604383e70f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7b5cc91adc3ed10df7cebd758cf8144216b9890 Original-Change-Id: I16f4f98df8c70fd25986a8b3644334c7209fd083 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329846 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331173 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13991 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 21:27:57 +0000