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2015-08-09Move function/data sections to common CFLAGSStefan Reinauer
Instead of adding -ffunction-sections and -fdata-sections to every architecture, just add it to CFLAGS_common, thus making sure that new architectures will pick it up automatically. Change-Id: I38e878851226565b7791d05e222cb4e502e0c8a3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11105 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09payloads: Move payloads logic to payloads directoryStefan Reinauer
Change-Id: I6437e30da6ab675d32dc81c5d6d3fd9bcdc67f06 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10923 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09libpayload: Use CONFIG_LP_CCACHE instead of CONFIG_CCACHEStefan Reinauer
CONFIG_CCACHE was obsoleted a long time ago for libpayload. Change-Id: Ib0a418d97f368439476e524b753160a6229bb9f6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10710 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09Makefile.inc: Clean up SeaBIOS clean command lineMartin Roth
Passing the argments to the sub-make is no longer needed. Change-Id: Ie4fa3e36c2911eb25f201506df0e79b415d3e9b9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10656 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09drivers/pc80/i8254.c: Indent with GNU indent 2.2.11Paul Menzel
Run `indent -linux src/drivers/pc80/i8254.c` and manually put the `;` in the while loop back on a separate line. Change-Id: I58c4c5df3846a91ef92aafb608962dc26a21f811 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10452 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09riscv-spike: support for Spike emulation of riscvThaminda Edirisooriya
Spike support: QEMU RISCV is broken, and the maintainers at Berkeley are working on it, but at the moment spike is the only way to test on riscv. Add support for spike console output for debugging. Privileged ISA: Update to privileged ISA in RISCV (machine, supervisor, hypervisor, user modes) broke exisitng RISCV asm, and bootblock.S was updated to match the new spec. Clean old assembly [pg: things build with gcc 4.9 now, but don't expect them to work. Hardcoding register names into the assembler language may not be the smartest idea of the RISCV folks.] Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-09license headers: Drop FSF addresses againPatrick Georgi
Some FSF addresses found their way back into our tree. Change-Id: I34b465fc78734d818eca1d6962a1e62bf9d6e7f3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11145 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-09libpayload: lpgcc: CFLAGS and CMDLINE order inversionPaul Kocialkowski
When building an external payload with lpgcc, the provided cmdline needs to be included before libpayload-specific CFLAGS so that the include priority is the payload first. This way, a payload using e.g. Kconfig that declares a config.h will have its config.h included first, instead of libpayload's config.h. Change-Id: I19b8012623e04c92a427d74904aed7f3bf5f0996 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11113 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09Kconfig: Add KCONFIG_STRICT modeStefan Reinauer
This is basically a -Werror mode for Kconfig. When exporting KCONFIG_STRICT in the Makefile, warnings in Kconfig will produce errors instead. This will make it easier to spot unclean Kconfig files, settings and dependencies. Change-Id: I941af24c3ccb10b8b9ddc5c98327154749ebbbc6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10977 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09f10/f12: Remove whitespace from gcccar.incStefan Reinauer
:'<,'>s,\ *$,, Change-Id: I9fca0e12f02d6fff4644abacecd4a31cea64bbc1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09secimage: Use libz's crc32 functionStefan Reinauer
This is to trick libreboot into not deleting misc.c when checking out coreboot. Change-Id: I8f0bb5cb3eb5681f99c616ae03de126efab852a9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11134 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09secimage: reformatStefan Reinauer
Change-Id: Ibfa8b6b60b2b39212cef27bb2a5f8849218164bb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11133 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09acpi: Align FACS to 64 bytesPatrick Georgi
The spec states (5.2.10): "The BIOS aligns the FACS on a 64-byte boundary anywhere within the system's memory address space." Change-Id: Ie9415e505525dbdd418028d4954018c829921a18 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: fwts 15.08 Reviewed-on: http://review.coreboot.org/11141 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-08samsung/exynos5250: Enable bootblock consolePatrick Georgi
Change-Id: I7b177b4c57f8e304167610205196ecfe4beb4fea Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11102 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-08google/urara: Stub out get_write_protect_state()Patrick Georgi
vboot2 requires it Change-Id: I63bc3f176af72da8ea172a09aa536a10f1184b14 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11099 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-08broadcom/cygnus: returning from verstage without having one is uselessPatrick Georgi
Change-Id: I488b74b73a7654e97958a80fa7c83258fea3e959 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11103 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-08abuild: avoid hanging in oldconfig for parallel buildsPatrick Georgi
oldconfig may wait for some input. Since we don't care while building tools, just provide something. Change-Id: I1c6f1b46957301886a7645cfb6c6bd264437aa7e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11094 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-08abuild: in junit output, name chromeos builds different from normal onesPatrick Georgi
This will allow building and reporting both in one pass. Change-Id: Id7dbe63c7628cb97d9cf190c151bf23c7b264a89 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11093 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-08abuild: when using --chromeos, skip boards with no Chrome OS supportPatrick Georgi
Change-Id: Ic33b9311d5f194908b0a923ef5b342bfe992bdfc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11092 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-08-08abuild: Make help text into a heredocPatrick Georgi
This simplifies editing. Change-Id: Iff7f0cb7e52788836adcc0813a7bfb6d69009eed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11091 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-07via/nano: Move CPU microcode to 3rdparty/blobsStefan Reinauer
Change-Id: I5da2a9fc34d2108caa2f21c0883d209b03a6b872 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11132 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-07documentation: Add documentation for timestamp libraryFurquan Shaikh
[pg: removed discussion of timestamp internals that isn't current anymore in favor of some notes for users: when to run which function, what _not_ to do. Also moved to markdown-ish layout. Will do further style cleanups later.] BUG=chrome-os-partner:32973 BRANCH=None TEST=None Change-Id: I6ea7237f2fa749ce3a493f378f9937e642f3b678 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 97e2a3ebd9552c2a91d9ea62be515059428631cb Original-Change-Id: I4b184ffad6fcd93d63343a9bca34ad013e9d4263 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229861 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10741 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-07vendorcode: Move AMD sources from blobs to vendorcodeMarc Jones
The AMD AGESA binaryPI sources were incorrectly committed to 3rdparty/blobs. Move them from blobs to vendorcode and fix Kconfig and Makefile.inc to match. Change-Id: I55a777553c1203464d7f7f4293b361fedcfa3283 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10982 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-07amd/model_fxx: Move CPU microcode to 3rdparty/blobsStefan Reinauer
Change-Id: I1a772be9d72aa6d6552f5ba21c20b28e400677e9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11131 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-07amd/model_10xxx: Move CPU microcode to 3rdparty/blobsStefan Reinauer
Change-Id: Ib053bdec185eca2b45c95bec713cf0fb6d16c0bc Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11130 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-07Move blobs marker forwardStefan Reinauer
b4ade40 via/nano: Move CPU microcode to 3rdparty/blobs 8921cc4 amd/model_fxx: Move CPU microcode to 3rdparty/blobs 1099605 amd/model_10xxx: Move CPU microcode to 3rdparty/blobs 5f5604e Convert microcode to binary Change-Id: I276537281a01f8497ed87108e66574ec45265f3a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11129 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-06buildgcc: Deal with gmp on 32bit Cygwin on 64bit hostzbao
Similar to what the below change says, ( http://review.coreboot.org/10792 commit ddb8f808940899240411282d0feb1e2f65ef43a9 Author: Patrick Georgi <patrick@georgi-clan.de> Date: Sat Jul 4 17:45:54 2015 +0200 buildgcc: Deal with gmp on 32bit Linux on 64bit CPUs GMP is overeager to detect 64bit ABIs even if the entire running codebase is 32bit (but on a 64bit CPU). Enforce a 32bit build in that situation. ) building GMP can not detect Cygwin is 32bit either if the host which Cygwin is running is 64bit. We set ABI=32 in that case. Change-Id: Ic53d75defebbe902325eb07f3d8631b2a53245ef Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11123 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-06buildgcc: Get the clean and correct uname on Cygwinzbao
Running `uname` on Cygwin gets "CYGWIN_NT-6.1-WOW" instead of "Cygwin". We need to fix the $UNAME on Cygwin. Change-Id: I540bfc52089951006fd0e20bb9893a3d891df9e1 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11124 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-05vendorcode: Fixup AGESA PI Kconfig variablesMarc Jones
The *_SELECTED Kconfig variables are not needed with the options contained within "if CPU_AMD_AGESA_BINARY_PI" introduced in e4c17ce8. It also removes the need to source and select the default prior to selecting the AGESA source or AGESA PI option. Change-Id: Iffa366f575f7f155bd6c7e7ece2a985f747c83be Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10981 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-04x86: Make sure boot device is mapped below 4GStefan Reinauer
On x86-64 the current way of calculating the base address of the boot device (SPI flash) gets an unwanted sign extension, making it live somewhere at the end of 64bit address space. Enforce rom_base to be at the upper end of the 4G address space. Change-Id: Ia81e82094d3c51f6c10e02b4b0df2f3e1519d39e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11121 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-04libpayload: .xcompile target is an actual filePaul Kocialkowski
Marking .xcompile as PHONY implies triggering the xcompile script each time make is invoked. This is particularly problematic, especially when the script cannot find the crossgcc toolchains on its own and has to be fed XGCCPATH. Change-Id: Icb5ae82b210bca1ee9cf56d76130eefde481f81e Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11118 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-04libpayload: Veyron configs unificationPaul Kocialkowski
All the currently-provided configs for veyron boards are the same, so we might as well have a common one that can be used on all boards. Change-Id: I2e24f2d7a5206878381467b97f01d3e752a93289 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11115 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-03libpayload: Allow for KBUILD_DEFCONFIG overridePaul Kocialkowski
In order to specify a defconfig to libpayload, one might want to declare KBUILD_DEFCONFIG in the make command line and run the defconfig target. Change-Id: I2ade6f4ff2f0b6478a0831158028ebc79b5daa81 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11112 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-31what-jenkins-does: make CPU count configurablePatrick Georgi
Change-Id: I55eb833dba3b13c46138f7d1facc31d999e52db4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11097 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-31what-jenkins-does: make its payload selection overridablePatrick Georgi
Change-Id: Ifbdc6bf73595a0d04a8ae09c80394787b6f76d13 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11096 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-31what-jenkins-does: Adapt to recent libpayload kconfig changesPatrick Georgi
Since we don't actually use this target at this time, it was bitrotting. Fix it up, so we can start to use it. Change-Id: I27d2ed4fb2640680acf739a87d61cb0d1463d705 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11095 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-31secimage: Don't link in gmp libraryStefan Reinauer
secimage does not use libgmp, so don't link it in. (Otherwise linking fails if the library is not installed) Change-Id: I24af21c7754ecd0109f3e86669fa34fa6991d7fe Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11079 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-30Add cscope/ctags generation for the current projectMartin Roth
Use the dependency files to generate ctags or cscope data for the current project instead of the entire coreboot tree. This isn't completely working for every platform at this point - while it finds all of the code in the coreboot/src tree, it doesn't find the code in 3rdparty right now. Change-Id: Ie8aabcf46c8a69f718940c9e0fd7e7b05c9ce1fb Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11074 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-07-30gigabyte/ga-b75m-d3h: Update device treeDamien Zammit
This patch resolves the outstanding issues with PCI device enumeration and getting the board to boot into GNU/Linux with VGA rom. Previously the board would not boot to GNU/Linux with video, even if VGA rom was used. Bugs in the devicetree were fixed according to superiotool output. Tested on GA-B75M-D3H with VGA rom. Booted to GNU/Linux (Fedora 22 4.0.4-301.fc22.x86_64) Change-Id: Ide1f406652659e6f99ee5d993719c187650fffe4 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/10895 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-30vendorcode: 64bit fixes for AMD CIMX SB800Stefan Reinauer
Make SB800 code compile with x64 compiler These fixes probably apply 1:1 to the other SB components in that directory. Change-Id: I9ff9f27dff5074d2faf41ebc14bfe50871d9c7f7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10573 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-30vendorcode: Port AMD Agesa for Fam14 to 64bitStefan Reinauer
Change-Id: Ic6b3c3382a6d3fdc6d716ea899db598910b4fe3e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10581 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-30SB800: Port to 64bitStefan Reinauer
Change-Id: I944fb254e9470c80b13c9eef9d6b1177a56e615f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10582 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-30README: improve description of compiler requirementsPatrick Georgi
People run into "building bootblock without the required toolchain" too often. Update documentation so they don't try to use random compilers to build coreboot. Change-Id: I9715b52a4bac9b886cc5627add074c04e06a0828 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11047 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-30amd/bettong: Enable fan controlWANG Siyuan
1. Use enable_imc_thermal_zone to enable fan control. 2. The ACPI method ITZE works on Ubuntu 14.04 and Windows 7 but does not work on Windows 8, so I didn't use it. After this issue is fixed, I'll add ACPI_ENABLE_THERMAL_ZONE in bettong/Kconfig. 3. Fan control works on Bettong. I used "APU Validation Toolkit" to test on Windows 8. This tool can put load to APU. The fan's behaviour is just like bettong/fchec.c defined. When the temperature is 40 Celsius, the fan start to run. Change-Id: I0fc22974a7a7cf3f6bdf5f1c66be95219a177e12 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10721 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-30AMD binary PI: add southbridge support for fan controlWANG Siyuan
1. Add functions to support fan control. 2. When IMC firmware is added, the current firmwares' layout cause build error. There is not enough space to add some firmwares, so HUDSON_PSP_OFFSET is added to fix this problem. Change-Id: Ie470a88cb9da256d9f72ea56bf268c15df195784 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10720 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-30AMD binary PI: add vendorcode support for fan controlWANG Siyuan
Binary PI doesn't provide fan control lib. HwmLateService.c and ImcLib.c are ported from Kabini PI. I have tested on AMD Bettong. The two files work. Change-Id: Ia4d24650d2a5544674e9d44c502e8fd9da0b55d3 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10719 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-29skylake: Update microcode reload in ramstage.Rizwan Qureshi
For Skylake, Microcode is being loaded from FIT, Skylake supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in bootclock and ramstage (MP init). Avoid the microcode reload by checking for PRMRR support. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:287513 Change-Id: Ic5dbf4d14dc1441e5b5acead589a418687df7dca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c599714b2aef476297eeaad5da8975731b12785a Original-Change-Id: Id3a387aa2d8fd2fd69052bfc7b4e88a7ec277a72 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287674 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11056 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-29Add SoC specific microcode update check in ramstageRizwan Qureshi
Some Intel SoCs which support SGX feature, report the microcode patch revision one less than the actual revision. This results in the same microcode patch getting loaded again. Add a SoC specific check to avoid reloading the same patch. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:286054 Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287513 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11055 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-29Skylake: Fix microcode reload in bootblock cpu initRizwan Qureshi
If Skylake microcode is being loaded from FIT, Skylake supports the PRMRR/SGX feature. If this is supported the FIT microcode load will set the msr (0x08b) with the patch ID one less than the ID in the microcode binary. This results in microcode getting reloaded again in the bootblock cpu init. Avoid the microcode reload by checking for PRMRR support. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 Change-Id: I06e59f5cad549098c7ba2dfa608cd94a0b3f0ae1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6242b9dea283149bd0c968af1ba186647d37162d Original-Change-Id: Iea5a223aa625be3fc451e8ee5d3510f548b07f8b Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286054 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11052 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-29arm, arm64, mips: Add rough static stack size checks with -Wstack-usageJulius Werner
We've seen an increasing need to reduce stack sizes more and more for space reasons, and it's always guesswork because no one has a good idea how little is too litte. We now have boards with 3K and 2K stacks, and old pieces of common code often allocate large temporary buffers that would lead to very dangerous and hard to detect bugs when someone eventually tries to use them on one of those. This patch tries improve this situation at least a bit by declaring 2K as the minimum stack size all of coreboot code should work with. It checks all function frames with -Wstack-usage=1536 to make sure we don't allocate more than 1.5K in a single buffer. This is of course not a perfect test, but it should catch the most common situation of declaring a single, large buffer in some close-to-leaf function (with the assumption that 0.5K is hopefully enough for all the "normal" functions above that). Change one example where we were a bit overzealous and put a 1K buffer into BSS back to stack allocation, since it actually conforms to this new assumption and frees up another kilobyte of that highly sought-after verstage space. Not touching x86 with any of this since it's lack of __PRE_RAM__ BSS often requires it to allocate way more on the stack than would usually be considered sane. BRANCH=veyron BUG=None TEST=Compiled Cosmos, Daisy, Falco, Blaze, Pit, Storm, Urara and Pinky, made sure they still build as well as before and don't show any stack usage warnings. Change-Id: Idc53d33bd8487bbef49d3ecd751914b0308006ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e5931066575e256dfc2295c3dab7f0e1b65417f Original-Change-Id: I30bd9c2c77e0e0623df89b9e5bb43ed29506be98 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236978 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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