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2018-06-21mb/google/poppy/variants/nautilus: Clear GPP_D0 when entering S5Seunghwan Kim
Nautilus 2nd SKU has a leakage voltage at GPP_D0 in S5 state. We need to set this to LOW when entering S5 for clear the leakage. BUG=None BRANCH=poppy TEST=Verified the leakage is gone after update coreboot Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21mb/google/poppy/variants/nautilus: Configure for 2nd nautilus SKUSeunghwan Kim
For supporting new SKU, we need to override GPIO table and device configuration. The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it. BUG=b:80052672 BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27147 Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-20fsp_broadwell_de: Add uncore ASL in common locationDavid Hendricks
This patch adds a file for uncore ASL code that is common among Broadwell-DE mainboards but is currently copy + pasted in each of their dsdt.asl files. This is only for clean-up purposes. It is unclear if the code itself is really necessary, but until we can do further investigation and testing it will be left in. Change-Id: I188e5e46dfa7c2ed3991fb97f2c1b5e062e2212d Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/27155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-20nb/intel/e7505: Leave ROM as un-cacheable in postcarKyösti Mälkki
Collected timestamps indicate LZMA decompression of ramstage is 4x slower when ROM is marked WP-cacheable, in contrast to having ROM as US. A simple copy WP->WB with uncompressed ramstage also appeared to be twice as slow as UC->WB copy. It should be noted that if POSTCAR_STAGE was removed from build, un-lzma takes 130 seconds instead of 45 milliseconds. Change-Id: I2cf995395ef2d303ad0bc044dbfa160990a705d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-20aopen/dxplplusu: Add romstage timestampsKyösti Mälkki
Change-Id: Ic6e2a350a976a3fcb421d47a0bf5600df994edc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-20mb/google/octopus: Configure EC_IN_RW correctlyFurquan Shaikh
This change fixes the following issues with EC_IN_RW signal: 1. EC_IN_RW is an input signal to the SoC. Configure it accordingly in GPIO table for baseboard and bip. 2. GPIO_EC_IN_RW is passed in coreboot tables so that payload can re-sample the GPIO at runtime. BUG=b:110084012 TEST=Verified that EC_IN_RW signal is read correctly in depthcharge. Change-Id: I1c5f5b4b914ced98e89a571dc398df5ba1fe8460 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-06-20mb/google/octopus: Enable Synaptics touchpad devicewuxy
This change adds Synaptics device to phaser project. BUG=b:110236590 TEST=emerge-octopus coreboot chromeos-bootimage reflash the coreboot to DUT,make sure the Synaptics Touchpad can work. Change-Id: Icc1e8c35a9de54ed04187fcf219a72a592d3bd81 Signed-off-by: Xingyu <wuxy@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27159 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-19payloads: Add LinuxBoot payload in u-root modePhilipp Deppenwiese
* Add LinuxBoot support * Add u-root mode * Download kernel and u-root from upstream sources. * Add customization options * Clean kernel only if directory exists Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23071 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-19lib: Add FIT payload supportPatrick Rudolph
* Add support for parsing and booting FIT payloads. * Build fit loader code from depthcharge. * Fix coding style. * Add Kconfig option to add compiletime support for FIT. * Add support for initrd. * Add default compat strings * Apply optional devicetree fixups using dt_apply_fixups Starting at this point the CBFS payload/ can be either SELF or FIT. Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3. Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0. Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52. Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-19Documentation: Add cavium SoC and mainboardPatrick Rudolph
* Add documentation for CN81XX SoC * Add documentation for CN81XX EVB SFF mainboard * Add documentation for BDK * Add documentation for BOOTROM and BOOTBLOCK behaviour * Alphabetically sort vendors Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-19lib: Raw import FIT parserPatrick Rudolph
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge Coding style and coreboot integration will be done in a separate commit. Change-Id: Iee56db328d7eeffb0eaf829841243b0b9195c199 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-19lib/prog_loaders: Move argument selection into selfloadPatrick Rudolph
Set the payload argument in selfload, as other (non self) payloads, are going to set a different argument. Change-Id: I994f604fc4501e0e3b00165819f796b1b8275d8c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25861 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-18mb/google/poppy/variants/nautilus: Correct USB OC pin configurationSeunghwan Kim
Due to schematic, we need to correct USB OC pin configuration. - OC0 for Type-C Port 1 - OC1 for Type-C Port 0 - OC2 for Type-A Port - OC3 to NC BUG=NONE BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-18mb/google/octopus: Enable Synaptics touchscreen deviceFurquan Shaikh
This change adds ACPI properties for SYTS7817 device. BUG=b:110013532 Change-Id: Ifdec4efce169c066f212a393df21089d43d8e4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-18mb/google/octopus: Create fleex variantJustin TerAvest
This creates a fleex variant for octopus. Nothing is set in the variant files here; everything is picked up from baseboard. BUG=b:110085182 TEST=None Change-Id: Ia8b8bb757f67bea997b7f43489c38cac62f7682d Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27105 Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-18cbfstool: Use endian.h and functions from commonlibWerner Zeh
The endian conversion function be32toh() is defined in src/include/endian.h, however this file is not used for cbfstool compilation. Currently the one provided by the host is used and if the host does not provide this endian.h file, the build will fail. However, we do have endian conversion functions in commonlib/endian.h which is available for cbfstool compilation. Switch from be32toh() to read_be32() in order to avoid relying on a host provided include file. We use functions from commonlib/endian.h already in cbfstool. Change-Id: I106274cf9c69e1849f848920d96a61188f895b36 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/27116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-17nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki
Boot tested on asus/p2b-ls and p2b-ds. Change-Id: I0154f1d120bef3b45286fb4314f0de419cd8341e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/26821 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-17nb/intel/i440bx: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: I96f42d5dc10d36855bdca64d1406a254250ee5b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26820 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-17cpu/intel/car/p3: Use variable MTRR countKyösti Mälkki
Change-Id: I323426e0d9ddee1be72d15702fee4f92c7b348cc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-17cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki
This moves CAR stack under variable MTRRs and removes old CAR code that used complex fixed MTRRs and placed stack in low memory. Change-Id: I75ec842ae3b6771cc3f7ff652adbe386c03b9a5f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/26586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-17cpu/intel/car: Remove obsolete filesKyösti Mälkki
These CAR init files are no longer used. The _ht variant will be used as basis for P3 CAR using with variable MTRRs so we only move file. Change-Id: Iace8762c11e2f282df1850f7be170c841d4881f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27084 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-17nb/intel/nehalem: Fix DEVEN definesPatrick Rudolph
The DEVEN defines are wrong, but weren't used at all. Fix them as they are needed by the hybrid_graphics_driver and use the defines instead of magic values. Tested on Lenovo T410: The IGD turns on with the correct value. Change-Id: Idf9fc0115de5c72f7d5d88cbb09ae1d2fee0afd0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-17mb/pcengines: Remove unneeded includes and dead codeElyes HAOUAS
Fix coding style. Change-Id: Id13c0ee284293c0c06d46c75c850bc7e81cfc1f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-17nb/intel/x4x: Issue a hard reset with empty MRC cache on warm resetArthur Heymans
The dram controller cannot fully initialize the dram on warm reset (receive enable calibration consistently fails) therefore requiring cached timings. This option is mostly useful when rebooting after having flashed a new rom which overwrites the mrc cache region. Change-Id: I405c0eca076fe081641ede9a670f734c98cbf8fc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-16drivers/spi: Add Winbond W25Q80Kyösti Mälkki
This is a small 8 megabit (1 MiB) part. Change-Id: I9890457d0d14beb17d0a428c2701e620ae8c2512 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-15mainboard/google/Kahlee: All variants identify as Grunt in SMBIOSMartin Roth
All Grunt variants should identify as grunt in SMBIOS so that they're recognized correctly as a unibuild Grunt variant. BUG=b:110244268 TEST=Careena identifies as grunt Change-Id: Iaf254149fbec9551d9220018d6d6a0a1be741538 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27117 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15Documentation: Add SandyBridge NRI feature matrixPatrick Rudolph
Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27093 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15soc/intel/{glk,apl} and mainboards: Configure LPC_CLKRUN# pin as GPIO for S0ixHannah Williams
This pin does not have a native function for eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO and kept unconnected to allow S0ix entry. Also removed initialization of LPC pins in mainboard code as they are already initialized in chipset code. The settings fpr LPC pins in chipset code were updated to those that were previously in mainboard code and have been validated on LPC flavor of Geminilake RVP. BUG=b:79251613 BRANCH=none TEST=From kernel prompt in bip, type powerd_dbus_suspend. Check on EC console that SOC enters S0ix. Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23742 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15util/cbfstool: Support FIT payloadsPatrick Rudolph
In order to support booting a GNU/Linux payload on non x86, the FIT format should be used, as it is the defacto standard on ARM. Due to greater complexity of FIT it is not converted to simple ELF format. Add support for autodecting FIT payloads and add them as new CBFS_TYPE 'fit'. The payload is included as is, with no special header. The code can determine the type at runtime using the CBFS_TYPE field. Support for parsing FIT payloads in coreboot is added in a follow on commit. Compression of FIT payloads is not supported, as the FIT sections might be compressed itself. Starting at this point a CBFS payload/ can be either of type FIT or SELF. Tested on Cavium SoC. Change-Id: Ic5fc30cd5419eb76c4eb50cca3449caea60270de Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-15mb/google/poppy/variants/nami: Update DPTF table from version 1.5John Su
Update dptf.asl and TCC parameters from tuning of the thermal team. BUG=b:72974136 TEST=Match the result from DPTF UI Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27086 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15mainboard/google/kahlee: Enable keyboard backlight for careena specific SKUKevin Chiu
Enable keyboard backlight by Careena SKUID Set to 10% as the same as google/snappy project BUG=b:110065836 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I7d302c4f50528b0e6b7ef4d990f342a69cff34f5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-14cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans
Tested on Google peppy (Acer C720). Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-14nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xceElyes HAOUAS
Change-Id: Ifb8aa43b6545482bc7fc136a90c4bbaa18d46089 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22957 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14driver/spi/macronix.c: Add MX25L8005Arthur Heymans
Change-Id: I595198d66193c63f6c80c39371fbec10065d2165 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14arch/arm/armv7: Fix coding styleElyes HAOUAS
Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14cpu/amd: Remove duplicated includesElyes HAOUAS
Change-Id: I3544ce4a573b6996d64b140d8acdaeb3de430896 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-14mb/lenovo/x200: Enable libgfxinitArthur Heymans
Change-Id: I6919845965d90fe8a20a07748ae4804fed0d0cef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27013 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14mb/*/*: Enable libgfxinit on x4x boardsArthur Heymans
TESTED Intel DG41WV with VGA, Intel DG43GT with VGA and HDMI1 and HDMI2. Change-Id: I774b79cc0ef9dc72ccf48901ab94376b27ed9c7a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
Some things were coding errors, other things need to be fsb specific. Most things here don't seem to matter all that much but better to get it right. Change-Id: I1afa637a16a083c3a945ba3e2a71292b005736fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14nb/intel/x4x: Work around a quirkArthur Heymans
It looks like this hardware has a bug where the display controller does not work properly when dram is clocked 533MHz and the channels are configured in non-stacked mode. The workaround is to select stacked mode in this configuration. Change-Id: I6f37ce15a4e98a4cdbd6d893f22846a65c8be021 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
There seems to be a hardware bug where the combination of non-stacked channel settings, both channels populated and 533MHz dram speed cause the display to be unusable. The code to actually select stacked mode based on hardware configuration will be add in a followup patch. This patch does the following: * Add option to the sysinfo struct for stacked mode * Fix programming channel 1 DRB which needs special care for the last populated rank in stacked mode TESTED on Intel dg41wv (with stacked mode hardcoded and dram at 533MHz) Change-Id: I95965bfea129b37f64163159fefa1c8f16331b62 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14stoneyridge: Increase SMM stack size to 2KRaul E Rangel
GSMI Set Event Log is taking more than 1K in stack. This causes the stack to overflow into the adjacent stack. This has the side effect of causing any CPU waiting for the SMI handler to complete to crash when the lock is unlocked because the return pointer has been smashed. BUG=b:80539294 TEST=built on grunt and tested by running `halt` from the OS. Change-Id: Ib170c7d03909ef3d20831726b285178a75007b06 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27033 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14cpu/x86: Make SMM stack size configurableRaul E Rangel
Stoneyridge is running into a stack overflow in the SMM handler. BUG=b:80539294 TEST=built on grunt Change-Id: I94e385497bd93c3638c69fb08d9b843c3bbb55ce Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27034 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14mb/google/poppy/variants/nocturne: config GPP_E2 for BT_DISABLE_LNick Vaccaro
GPP_E2 will be used as a BT reset line, so configure GPP_E2 as an output and initialize it high (high = out of reset). BUG=b:80089559 BRANCH=none TEST=none Change-Id: If45ef3a592c389a0b80298c59eea849d07d9671e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-14mb/google/poppy/variants/nocturne: config GPP_B4 for FCAM_PWR_ENNick Vaccaro
FCAM_PWR_EN signal is changing to connect to GPP_B4 instead of GPP_D8 as it needs a 3.3v gpio to provide enough power to also directly power the camera LED. BUG=b:79667559,b:78122599 BRANCH=none TEST=none Change-Id: Ie875ced45dfa2aa7069851004edde8f77329df34 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-14soc/intel/{glk,apl}: ensure C1E is disabled after S3 resumeCole Nelson
C1E is disabled by the kernel driver intel_idle at boot. This does not address the S3 resume case, so we lose state and C1E is enabled after S3 resume. Disable C1E for GLK as it is for APL. This gives a coherent state before and after S3 resume. TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3 resume with bit [1] set to zero (0x20005d). Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10 Signed-off-by: Cole Nelson <colex.nelson@intel.com> Reviewed-on: https://review.coreboot.org/27019 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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