summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2015-04-30intel/broadwell: Build monotonic timer driver for SMMPatrick Georgi
SPI flash drivers need it. Change-Id: I63d79472d70d75f7907e7620755c228d5a4918e1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10033 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30build system: Drop another vboot1 remnantPatrick Georgi
The vboot stage is now done totally different, as a real stage, and handled in the right location (src/vendorcode/google/chromeos/vboot2/Makefile.inc), so drop this vboot1 file. Change-Id: Ie9a4ae257c2702ddcd217f5b4ef8d8f22b5099f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30i2c/tpm: add final newlinePatrick Georgi
Change-Id: I0024c4d56f93eb6c9a54103e79c9d8a8b7d8d6fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10043 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30chromeos: Use __attribute__ normal formPatrick Georgi
Change-Id: Idf99c1491386578ac2471ca5cc8a153d2b5225e4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30chromeos: Add missing headersPatrick Georgi
Builds with CHROMEOS fail due to missing includes. Change-Id: I8c88bca8f8cc3247d3f3311777f794c4fdfee3c1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10029 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30vboot: add and rejuggle Kconfig optionsAaron Durbin
The ChromeOS machines employing vboot verfication require different combinations of support: 1. When vboot verification starts. 2. Is the vboot code a separate stage or program? 3. If a separate stage, does the that vboot program (verstage) return to the stage that loaded the verstage? For the above, #1 is dependent on when to load/run vboot logic which is orthogonal to #2. However, #3 is dependent on #2. The logic to act on the combinations follows in subsequent patches. Change-Id: I39ef7a7c2858e7de43aa99c38121e85a57f1f2f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10024 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30vboot: move Kconfig options for stage indiciesAaron Durbin
With vboot1 out of the way place all the associated Kconfig options in vboot2's Kconfig file (excluding main vboot verify option). More options will be added to accomodate vboot's various combinations of use cases. Change-Id: I17b06d741a36a5e2fefb2757651a61bfed61ae1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10023 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-30program loading: add optional is_loader_active() callbackAaron Durbin
Add a way for a loader to indicate if it is active. Such users of this callback would be vboot which can indicate to the rest of the system that it isn't active. is_loader_active() also gives vboot a chance to perform the necessary work to make said decision. Change-Id: I6679ac75b19bb1bfff9c2b709da5591986f752ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10022 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30i945/gma: Fix wrong comment about the documentation.Denis 'GNUtoo' Carikli
The GTT location is documented in the "309219" datasheet. For instance it can be found in the TOLUD register description. The 309219 datasheet is for the "Mobile Intel® 945 Express Chipset Family". It was published in 2008. Change-Id: I75ac095ebc577e031af566963ebffe9ed2587c96 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/9622 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30kbuild: Don't require intel/common changes for every socStefan Reinauer
In the true spirit of separating components more strictly and allowing to add new components to coreboot without touching existing code, move Intel common code selection to the soc Kconfig and out of src/soc/intel/common/Makefile.inc Change-Id: I0a70656bb9f4550b6088e9f45e68b5106c0eb9af Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10031 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30crossgcc: improve error message on missing toolsPatrick Georgi
People were confused about the 'missing toolchain', so improve the error message. Change-Id: Icaee338aeedce2255bcfdafe5407c9df02ad9c4a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10036 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2015-04-30cbmem: Add FSP timestampsLee Leahy
Add additional FSP timestamp values to cbmem.h and specify values for the existing ones. Update cbmem.c with the FSP timestamp values and descriptions. BRANCH=none BUG=None TEST=Build for Braswell and Skylake boards using FSP 1.1. Change-Id: I835bb090ff5877a108e48cb60f8e80260773771b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10025 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30cbmem: Identify the FSP areas in CBMEMLee Leahy
Add identifers and descriptions for the FSP areas within CBMEM. BRANCH=none BUG=None TEST=Build for Braswell and Skylake boards using FSP 1.1. Change-Id: I4d58f7f08cfbc17f3aef261c835b92d8d65f6622 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10026 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30imgtech/pistachio: Give some more space to the bootblockPatrick Georgi
The memory layout isn't very clear here, since there are two regions (bootblock and "SRAM") that are actually the same. So when increasing the bootblock's size, we also need to move the romstage around. Change-Id: Ib158a4ef96b7c1dd1132b6e8bd47a0eb9c3951d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10035 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-04-29kbuild: automatically include northbridgesStefan Reinauer
This change switches all northbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in northbridge/Makefile.inc or in northbridge/<vendor>/Makefile.inc. This means, vendor and northbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I8468154dbfaaaffcba9fda27ba2d7b9049ad5c19 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9800 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-29kbuild: automatically include SOCsStefan Reinauer
This change switches all SOC vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in soc/Makefile.inc or in soc/<vendor>/Makefile.inc. This means, vendor and SOC directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: Iede26fe184b09c53cec23a545d04953701cbc41d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9799 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-29kbuild: automatically include ECsStefan Reinauer
This change switches all ECs and the generic EC ACPI code to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in ec/Makefile.inc or in ec/<vendor>/Makefile.inc. This means, vendor and ec directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I29d757d1f8c10a1d0167a76fd0d0f97bac576f6d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9798 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-29dmp/vortex86: move PLL config to cpu KconfigMartin Roth
This moves the vortex86ex cpu's pll configuration out of the mainboard and into the cpu's Kconfig. Change-Id: I72ee1baa3a96586fceff03ff43c5f61e2498667e Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/9058 Tested-by: build bot (Jenkins) Reviewed-by: Andrew Wu <arw@dmp.com.tw> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-29mainboard/intel: Drop unused onboard.h filesKyösti Mälkki
Change-Id: I0851375f419202f62ddc8c80fa77e1d8c95ed50f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/9991 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-29crossgcc: don't use libdl while building GDB on FreeBSDIdwer Vollering
Since FreeBSD doesn't have libdl, these errors are shown: - config.log: /usr/bin/ld: cannot find -ldl - crossgcc-build.log: configure: error: C compiler cannot create executables Conditionally pass the presence of libdl in LDFLAGS. Change-Id: I79c48da7e6700a4606c9e0c1314241db8997d3f3 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/2342 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-29Use __ROMSTAGE__ to denote romstagePatrick Georgi
There were some remaining places that used __PRE_RAM__ for romstage, while it really means 'bootblock or romstage'. Change-Id: Id9ba0486ee56ea4a27425d826a9256cc20f5b518 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10020 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-04-29rules.h: add verstage macroPatrick Georgi
Change-Id: I5ba32e80a825a1f86d0e32da23e5fa0a2d85f4cd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10019 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-04-29vendorcode/intel: Add FSP 1.1 header filesLee Leahy
The second step in adding support for FSP 1.1 is to add the header files. Updates may be done manually to these files but only to support FSP 1.1. An FSPx_y tree should be added in the future as FSP binaries migrate to new FSP specifications. The files are provided in an EDK2 style tree to allow direct comparison with the EDK2 tree. BRANCH=none BUG=None TEST=Build for Braswell or Skylake boards using FSP 1.1. Change-Id: If0e2fbe3cf9d39b18009552af5c861eff24043a0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9974 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-28gitconfig: Use the right make executable in git hooksPatrick Georgi
When installing git hooks through $(MAKE) gitconfig, make knows itself (and is a GNU make). So let it splice itself into hooks where necessary by replacing %MAKE%. Change-Id: Iaf778bfa3f17a8fe31312f871571ed89a9de5385 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10018 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-28buildgcc: OpenBSD's tar and patch are sufficient, tooPatrick Georgi
No need to enforce GNU versions for them. Change-Id: Ieeb43298331fbefbcc1e230d41a90e9df56993eb Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-28board-status: Improve revision URL collectionPatrick Georgi
It now assumes that origin points to the official repo (while there may be more) and doesn't assume anymore that there's a user ID that needs to be pruned (although it is, if present). Change-Id: Id4c5ee2cb7c08e997eaba1c750097a2e2bf51af5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10016 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28cbfstool: compare pointer difference with ptrdiff_t valuePatrick Georgi
Fixes building cbfstool in 32bit environments. Change-Id: I3c94afc9c961eb8b41d1e08f4a16e5cab2a6bb8b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10015 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28Kconfig whitespace fixesMartin Roth
trivial whitespace fixes. Mostly changing leading spaces to tabs. Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28fsp platforms: consolidate FspNotify callsMartin Roth
Consolidate the FspNotify calls into the FSP driver directory, using BOOT_STATE_INIT_ENTRY to set up the call times. Change-Id: I184ab234ebb9dcdeb8eece1537c12d03f227c25e Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/9780 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28Fix some minor Kconfig issuesMartin Roth
- Remove Kconfig files that are no longer used: src/vencorcode/Kconfig src/soc/marvell/Kconfig - Fix the drivers/sil/Kconfig to point to drivers/sil/3114 which had the same code. - Make sure all Kconfig files have linefeeds at the end. This can cause problems, although it wasn't in this case. - Include cpu/intel/model_65x/Kconfig which was not being included. Change-Id: Ia57a1e0433e302fa9be557525dc966cae57059c9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/9998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28Makefile x86 SMM: Move smm_wrap recipesKyösti Mälkki
This is not used together with SMM_MODULES. Change-Id: I52621787cfa5a9e3863c150ce64f62aceb423eb4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10014 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28arm: guard verstage rulesAaron Durbin
Do not unconditially supply verstage rules for all platforms. Change-Id: Ic0713350aa21a9966fca828211750d25c2b6b71d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9969 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28vboot: remove vboot_helper.cAaron Durbin
This file was moved previously to get it out of the way for easier merging from the chromium repo. It's not used currently so remove it. Change-Id: I8e691623f29ac2218b83bc46f5b4a348e0e1b3ef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9960 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-28boards: remove VBOOT_(REFCODE|RAMSTAGE|ROMSTAGE)_INDEXAaron Durbin
These options will need to just be selected in within the .config files. There's not need in duplicating all these options. Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9959 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28chromeos: remove VBOOT2_VERIFY_FIRMWARE optionAaron Durbin
There's no need to have the VBOOT2_VERIFY_FIRMWARE distinction because it's the only game in town. Change-Id: I82aab665934c27829e1a04115bf499ae527a91aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9958 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28vboot: remove vboot1Aaron Durbin
In preparation for moving to vboot2 for all verified boot paths bring over Kconfig options to the common area from vboot1. Also remove vboot1 directory entirely. Change-Id: Iccc4b570216f834886618f0ba5f2e1dd6c01db4b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9957 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28marvell/bg4cd: merge verstage into bootblockDaisuke Nojiri
If verified boot is enabled, merge verstage into bootblock. This also requires custom bootblock code to actually call into verstage. [pg: modified to match upstream] BUG=chrome-os-partner:32631 BRANCH=ToT TEST=booted on cosmos development board. Change-Id: I53251aac966ee15da24232c23fefa636de8b253b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2b8ada263017b46afa755b5acb759574184dba06 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia0e1236357aa32bf553fb8cc98f3a8d29de17f45 Original-Reviewed-on: https://chromium-review.googlesource.com/229795 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10008 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28vboot2: Allow merging verstage into bootblockPatrick Georgi
Change-Id: I31cd7f84db8b7176c8854f33421aab5c176cd5ce Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10007 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28vboot2: Always enable timestampsPatrick Georgi
The vboot2 code requires them. Change-Id: I9afaf9b373297b0eebce9ffd7cc05766dee7d6fd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10006 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28vboot2: get rid of global variable that is used locally and only oncePatrick Georgi
Change-Id: Iaf6d6a8857451fb16916aaae97a6fd5c51bc8cc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10005 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28vboot2: Build verstage archive, then use that for building the stagePatrick Georgi
This slightly streamlines integrating the vboot2 library and prepares for merging verstage and bootblock on selected devices. Change-Id: I2163d1411d0c0c6bf80bce64796e1b6a5a02b802 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28lib: When used, add timestamp.c to bootblock and verstage, tooPatrick Georgi
Otherwise it won't build. Change-Id: If9e1435b0dc8bfe220b3a257976e928373fbc9a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10003 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-28arch/arm: Move inclusion of timestamps.c to the right directoryPatrick Georgi
Without this, building with COLLECT_TIMESTAMPS fails. Fixes a mistake during upstreaming in commit 0de8820. Change-Id: Ie56bd38649a821f6b22a1e5dee5f50ef397035fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-28build system: Allow using .a archives as sourcePatrick Georgi
Change-Id: I1d61971f1458ca7e4257abb6a9c2aa15ac08e1d0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10001 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-28OxPCIe: Fix UART base addressesKyösti Mälkki
The offset of 0x2000 was for a configuration with two separate OxPCIe chips. The setup we support is a single chip with 8 UART pors. Change-Id: If4be046a14464af7b90b86aca5464c6b3400dffc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8780 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28intel SMI handlers: Refactor GPI SMI/SCI routingKyösti Mälkki
Move the GPI interrupt routing selection between SMI/SCI from mainboards to southbridge. There is speculation if this is all just legacy APM stuff that could be removed with a followup. Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7967 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-04-28x60,t60,x201,macbook21 : Declare GPIs for ECKyösti Mälkki
For lenovo/x201, this also changes GPI_ROUT (0xb8-0xbb) programming to use GPI1 between SCI/SMI modes, while previous programming was for GPI12. Change-Id: I3ac0feaa1d10c8f0e53a5fa5af72366503bb5d2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8656 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28xcompile: improve mips toolchain handlingVadim Bendebury
The mips toolchain used by coreboot so far comes from Chrome OS chroot and is built explicitly for little endian code generation. Other flavors of MIPS toolchain usually generate big endian code by default and require command line options to switch to little endian mode. This patch adds another variable to the set of compiler flags examined to determine compiler compatibility. This results in adding another nested for loop in test_architecture(). To avoid the need to break from different levels of nesting, processing of the successful case is taken out from test_architecture(). With this change the Mentor Graphics provided mips GCC toolchain is accepted by xcompile, resulting in the following output: ARCH_SUPPORTED+=mips SUBARCH_SUPPORTED+=mips mipsel CC_mips:=mips-linux-gnu-gcc CFLAGS_mips:= -Wno-unused-but-set-variable -fno-stack-protector -Wl,--build-id=none -mno-abicalls -fno-pic -EL CPP_mips:=mips-linux-gnu-cpp AS_mips:=mips-linux-gnu-as LD_mips:=mips-linux-gnu-ld NM_mips:=mips-linux-gnu-nm OBJCOPY_mips:=mips-linux-gnu-objcopy OBJDUMP_mips:=mips-linux-gnu-objdump READELF_mips:=mips-linux-gnu-readelf STRIP_mips:=mips-linux-gnu-strip AR_mips:=mips-linux-gnu-ar Change-Id: I4da384b366880929693c59dc0e1c522b35c41bea Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9997 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-28xcompile: Use local variables and make cosmetic changesVadim Bendebury
Declaring function variables local improves bash scripts' robustness. Cosmetic changes among other things include renaming variables from plural to singular and vice versa as appropriate, and replacing spaces with tabs. Tested by confirming that sorted output generated by util/xcompile/xcompile is the same before and after the change. Change-Id: I7305b3a4e45478ed3653b7d915dde4f83965f6c1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9996 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28make: avoid problems with mv aliasesVadim Bendebury
Make fails to update .xcompile in case there is an mv alias preventing silent overwrites of existing files. To avoid ambiguity, invoke mv from standard location. While we are at it, drop the code creating a unique .xcompile instance before copying it into destination: this was done for the case of running multiple independent make processes in parallel, but there is a problem with this approach with multiple processes copying their unique copies into the same destination file. The tool running multiple make invocations in parallel should explicitly invoke xcompile first. Change-Id: Iedc5e288fbcc5dfc18ce39de5c067bb869a13275 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9994 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-24 03:35:04 +0000