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2016-07-22google/reef: Update gpio config for audioSathyanarayana Nujella
This changelist updates gpio config for speaker SDMODE pin. It disables speaker by default. Audio kernel is expected to enable this when audio rendering starts. Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8983e7 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15433 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22soc/intel/apollolake: clarify meaning of LPDDR4 density meaningAaron Durbin
The 'dram density' is a misnomer because the memory initialization code treats that input parameter as a per rank density. Therefore, update the variables to further clarify how it's actually being used. BUG=chrome-os-partner:55446 Change-Id: Ie4c944f35b531812205ac0bb1c70f39ac401495e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15773 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22mainboard/google/reef: indicate dual rank LPDDR4 skusAaron Durbin
The 16Gb devices use two ranks per channel within the DRAM module. However, the density settings are really on a per rank basis so indicate dual rank with a device density of 8Gb. BUG=chrome-os-partner:55446 Change-Id: Ib5dba6f9ed248750d68b726996c71def9b75961e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15772 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-22soc/intel/apollolake: add dual rank option to meminitAaron Durbin
Despite the UPD comments the Chx_RankEnable fields are a bit mask which indicates which ranks are enabled for physical channel. Add the ability to set the rank mask correctly for dual rank LPDDR4 modules. BUG=chrome-os-partner:55446 Change-Id: I9dbed7bb6a4b512e57f6b4481180932a7cce91ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15771 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22soc/intel/apollolake: die() when FSP silicon init failsAaron Durbin
The reset requests are handled in the FSP 2.0 wrapper, but the current code doesn't check any non-successful return values. Provide parity with the memory init path which die()s under those circumstances. Change-Id: I9df61323f742b4e94294321e3ca3ab58a68ca4dd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15766 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-22intel car: Unify postcodesKyösti Mälkki
Not all are matched, but this makes it easier to backport MTRR changes from haswell. Change-Id: Ida5943b1469fc0089a31ff3b18131fb82b0941c6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15760 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22intel car: Unify whitespace and comment fixesKyösti Mälkki
Change-Id: Icd0cc7d27f38bdaee6addb98abec6f310cdd9fae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15759 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22intel car: Remove guard on XIP_ROM_SIZEKyösti Mälkki
These guards have been removed starting with model_206ax. Change-Id: Id63034ec4080e37eee2c120aa1f1ef604db5b203 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15758 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-22intel model_106cx: Include CAR from socket directoryKyösti Mälkki
Since the socket layer is implemented with this CPU model, there could potentially be multiple CPU models included. There can be only one cache_as_ram include, so select it directly within the socket directory. Change-Id: Ia52bb152276eddfd1fb33ddb7f5d153ab8e8163c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15757 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-21mainboard/google/reef: handle eMMC power signal polarity changeAaron Durbin
The EVT board uses an active high power control signal while the previous board used an active low signal. Update the tables to reflect the differences. BUG=chrome-os-partner:55470 Change-Id: I198c0e4e019fcffe2cf748d382351ac965a81077 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15763 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21mainboard/google/reef: reverse the memory config bitsAaron Durbin
I mistakenly assumed the order of the bits matched how one would assign values as they wrote them msb .. lsb. However, the gpio lib doesn't do that. Correct the order so that values are read out correctly. BUG=chrome-os-partner:54949t Change-Id: I5304dfe2ba6f8eb073acab3377327167573ec2cc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15753 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21timestamp: Drop duplicate TS_END_ROMSTAGE entriesKyösti Mälkki
This entry gets added in run_ramstage(). Change-Id: I18cda4ead3614c6d07c3269cbee53e6def6408c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15755 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21AMD k8 fam10: Fix CAR GLOBALS late in romstageKyösti Mälkki
Zero-filling memory below 1 MiB resets car_migrated variable so any CAR GLOBALs are not addressed correctly for the remaining time in romstage. Also there is no actual need to do this as ramstage loader handles BSS. This fixes regression with commit 70cd54310 that broke fam10 boards with romstage spinlocks enabled. Change-Id: I7418821997a980ae5b818bd57e8a1b6507a543af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15754 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-07-21buildgcc: Never set GMP CFLAGS manually in order to get the right flagsPaul Kocialkowski
When no CFLAGS are explicitly provided to it, the GMP configure script will figure out the best optimization flags to use on its own. In particular, it will setup the march, mfpu and mtune flags based on hardware detection. However, when CFLAGS are provided, they are used as-is and such detection doesn't happen. When the march, mfpu and mtune flags are not provided (which happens when GMP wasn't built already), not only will related optimizations be disabled, but some code might not build because of missing support. This happens with NEON instructions on ARMv7 hosts. Thus, it is better not to set CFLAGS and leave it up to the GMP configure script to get them right and still reuse those later. Change-Id: I6ffcbac1298523d1b8ddf29a8bca1b00298828a7 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15452 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-07-21soc/intel/apollolake: Add new Intel HD Graphics Device ID's.Abhay Kumar
B stepping onwards we have to support two Graphics Device ID. BUG=chrome-os-partner:55449 Change-Id: I520791ad8573dc5deb6ea1e33e1486f05050438c Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/15767 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-20coreinfo: Add support to read timestampsAntonello Dettori
Read timestamps from the last boot sequence and display the information as if using cbmem -t. Tested on QEMU with a SeaBIOS payload. Change-Id: I44f1f6d6e4ef5458aca555c8a7d32cc8aae46502 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15600 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-20cbmem: share additional time stamps IDsAntonello Dettori
Split the additional time stamps concerning depthcharge from the cbmem utility sourcecode and move them into commonlib/timestamp_serialized.h header. Change-Id: Ic23c3bc12eac246336b2ba7c7c39eb2673897d5a Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15725 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-20google/reef: Add wake signal for trackpadFurquan Shaikh
EVT has a wake signal for track pad which is routed to GP_15. BUG=chrome-os-partner:54960 Change-Id: I9a73a3dc74e3bbed63509a3c076ec17a6559da55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15723 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-20tpm2_tlcl: Use signed integer for tpm2_marshal_command return valueDuncan Laurie
The tpm2_marshal_command() function returns a negative value on error, so we must use a signed type for the return value. This was found by the coverity scan: https://scan.coverity.com/projects/coreboot?tab=overview CID:1357675 CID:1357676 Change-Id: I56d2ce7d52b9b70e43378c13c66b55ac2948f218 Signed-off-by: Duncan Laurie <dlaurie@google.com> Found-by: Coverity Scan Reviewed-on: https://review.coreboot.org/15717 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-07-20soc/intel/quark: Fix legacy GPIO readsLee Leahy
Add missing break to LEG_GPIO_REGS case to return the correct value for legacy GPIO reads. Fixes coverity issue CID 1357460. Found by Coverity, Fixes: * CID 1357460 (#1 of 1): Unused value (UNUSED_VALUE) returned_value: Assigning value from reg_legacy_gpio_read(step->reg) to value here, but that stored value is overwritten before it can be used. value_overwrite: Overwriting previous write to value with value from reg_pcie_afe_read(step->reg). TEST=Build and run on Galileo Gen2. Change-Id: I6c52e8801a32f510ac94276fe0c097850cbfde57 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15732 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-20amd/db-ft3b-lc: Add board supportKyösti Mälkki
Change-Id: Ibab9039306730bfd3063b34cf085e854e4608902 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14970 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-20amd/db-ft3b-lc: Copy of amd/olivehillplusKyösti Mälkki
Change-Id: I70330278bae54392e236d762716ba7c4d39a05a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14969 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-19rockchip/rk3399: Remove unused variableMartin Roth
The 'speed' variable isn't being used after refactoring. Change-Id: Id27a920c61b2bba18d391a7bfefe570235402dec Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15749 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19intel/amenia: Add DA7219 support in acpiHarsha Priya
Add DA7219 support in acpi. DA7219 has advanced accessory detection functionality. Also add DA7219's AAD as a ACPI data node. Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45021 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15625 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-19drivers/intel/fsp2_0: Split reset handling logicAndrey Petrov
FSP 2.0 spec only defines 2 reset request (COLD, WARM) exit codes. The rest 6 codes are platform-specific and may vary. Modify helper function so that only basic resets are handled and let SoC deal with the rest. Change-Id: Ib2f446e0449301407b135933a2088bcffc3ac32a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15730 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-19arch/riscv: Enable unaligned load handlingJonathan Neuschäfer
Change-Id: If1c63971335a6e2963e01352acfa4bd0c1d86bc2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15590 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19soc/intel/apollolake: Implement reset_prepare()Andrey Petrov
At first boot CSE spends long time preparing media for use. As result it may not be able to deal with a CPU reset. Add reset_prepare() callback that polls CSE readiness. BUG=chrome-os-partner:55055 TEST=build with release version of fsp, reboot, observe polling for CSE, then proper reboot happening Change-Id: I639ef900b97132f1a7f269bb864d70009df9fdfe Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15721 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19soc/intel/common: Add reset_prepare() for common resetAndrey Petrov
Some Intel SoC may need preparation before reset can be properly handled. Add callback that chip/soc code can implement. BUG=chrome-os-partner:55055 Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19soc/intel/apollolake: Add basic HECI supportAndrey Petrov
Add functions to read Host Firmware Status register and a helper function to determine if CSE is ready. BUG=chrome-os-partner:55055 TEST=none Change-Id: If511a51c04f7e59427d7952fa67b61060e2be404 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15713 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19drivers/intel/fsp2_0: handle reset requests from FSPSAaron Durbin
The FSPS component can request resets. Handle those generically. BUG=chrome-os-partner:52679 Change-Id: I41c2da543420102d864e3c5e039fed13632225b4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15748 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: handle reset requests from FSPMAaron Durbin
The FSPM component can request resets. Properly handle those. BUG=chrome-os-partner:52679 Change-Id: If21245443761cb993e86c0e383c8bca87f460a85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15747 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: range check stack provided to FSPMAaron Durbin
Ensure that the stack provided to FSPM doesn't overlap the current program which is loading the FSPM component. If there is a conflict that's an error since it could cause the current program to crash. BUG=chrome-os-partner:52679 Change-Id: Ifff465266e5bb3cb3cf9b616d322a46199f802c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15746 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: don't use saved memory data in recovery modeAaron Durbin
If the system is in recovery mode force a full retrain. BUG=chrome-os-partner:52679 Change-Id: I4e87685600880d815fe3198b820a10aa269baf37 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15745 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: honor FSP revision for memory training dataAaron Durbin
Utilizing the FSP revision while saving the memory training data is important because it means when the FSP is updated the memory training is redone. The previous implementation was just using '0' as a revision. Because of that behavior a retrain would not have been done on an FSP upgrade. BUG=chrome-os-partner:52679 Change-Id: I1430bd78c770a840d2deff2476f47150c02cf27d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15744 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19drivers/intel/fsp2_0: remove unused fsp_load_binary()Aaron Durbin
Remove the now unused fsp_load_binary() function. BUG=chrome-os-partner:52679 Change-Id: I5667eb71689a69a9e05f7be05cb0c7e7795a55d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15743 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: load and relocate FSPS in cbmemAaron Durbin
The FSPS component loading was just loading to any memory address listed in the header. That could be anywhere in the address space including ramstage itself -- let alone corrupting the OS memory on S3 resume. Remedy this by loading and relocating FSPS into cbmem. The UEFI 2.4 header files include path are selected to provide the types necessary for FSP relocation. BUG=chrome-os-partner:52679 Change-Id: Iaba103190731fc229566a3b0231cf967522040db Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15742 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: John Zhao <john.zhao@intel.com>
2016-07-19drivers/intel/fsp2_0: handle XIP and non-XIP for FSPM componentAaron Durbin
The previously implementation for loading the FSPM component didn't handle platforms which expects FSPM to be XIP. For the non-XIP case, romstage's address space wasn't fully being checked for overlaps. Lastly, fixup the API as the range_entry isn't needed any longer. This API change requires a apollolake to be updated as well. BUG=chrome-os-partner:52679 Change-Id: I24d0c7d123d12f15a8477e1025bf0901e2d702e7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15741 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: separate component validation from loadingAaron Durbin
The current FSP component loading mechanism doesn't handle all the requirements actually needed. Two things need to be added: 1. XIP support for MemoryInit component 2. Relocating SiliconInit component to not corrupt OS memory. In order to accommodate those requirements the validation and header initialization needs to be a separate function. Therefore, provide fsp_validate_component() to help achieve those requirements. BUG=chrome-os-partner:52679 Change-Id: I53525498b250033f3187c05db248e07b00cc934d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15740 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: implement common memory_init() tasksAaron Durbin
Instead of performing the same tasks in the chipset code move the common sequences into the FSP 2.0 driver. This handles the S3 paths as well as saving and restoring the memory data. The chipset code can always override the settings if needed. BUG=chrome-os-partner:52679 Change-Id: I098bf95139a0360f028a50aa50d16d264bede386 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15739 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: set BootLoaderTolumSize genericallyAaron Durbin
The amount of reserved memory just below the DRAM limit in 32-bit space is defined in the FSP 2.0 specification within the FSPM_ARCH_UPD structure. There's no need to make the chipset code set the same value as needed for coreboot. The chipset code can always change the value if it needs after the common setting being applied. Remove the call in soc/intel/apollolake as it's no longer needed. BUG=chrome-os-partner:52679 Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: fix hand-off-block types and sizeAaron Durbin
The gcc compiler treats sizeof(void) == 1. Therefore requesting a 1 byte reservation in cbmem and writing a pointer into the buffer returned is wrong. Fix the size of the request to be 32-bits because FSP 2.0 is in 32-bit space by definition. Also, since the access to the field happens across stage boundaries it's important to ensure fixed widths are used in case a later stage has a different pointer bit width. BUG=chrome-os-partner:52679 Change-Id: Ib4efc7d5369d44a995318aac6c4a7cfdc73e4a8c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15737 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19soc/intel/apollolake: remove unused FIT_POINTER defineAaron Durbin
Change-Id: I97be4f8cecbf9cf2adda2e0c1650e03acd7eb1cb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15736 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19commonlib: fix 'AFTER CAR' spacing to align with othersAaron Durbin
The cbmem string for 'AFTER CAR' didn't have the proper spacing so when that entry is added to cbmem it results in a misaligned log entry with the others. Change-Id: If940e85b7dc5fb8372d7e2845270dadad67ab3a0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15735 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19lib: provide memrange library in romstageAaron Durbin
BUG=chrome-os-partner:52679 Change-Id: I79ffc0749fba353cd959df727fb45ca2ee5c1bf6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15734 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19mainboard/google/reef: explicitly set shipping Chrome OS optionsAaron Durbin
The Chrome OS options that will be shipped on this platform were being set in the chromium repo with an external config file. Set the options in the mainboard Kconfig file so there's no discrepancy as to what will be used. Change-Id: I05f0d1245611c16f54273728519a08e6edff3429 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15733 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19soc/intel/apollolake: Fix bitshift issue in bootblockAndrey Petrov
Fix issue where zero-sized BIOS region could cause bitshift for '-1' which is an unspecified behavior. Change-Id: Icb62bf413a1a0d293657503ef21fe97b5f9a5484 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15727 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19nb/intel/x4x: Fix CAS latency detectionDamien Zammit
Fix and use the failsafe CAS detection logic rather than recalulating the values from raw SPDs. Tested on GA-G41M-ES2L with 2x2GB DDR2-800 DIMMs (which worked before and still work) Change-Id: I6af0f1705d099f7bcbff8c9baa94a68dae689e01 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15726 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2016-07-18arch/riscv: Remove enter_supervisorJonathan Neuschäfer
This function is unused since coreboot starts payloads in machine mode, and it uses the obsolete eret instruction. Change-Id: I98d7d0de5a3959821c21a0ba4319efb610fdefde Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15729 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-18arch/riscv: Change all eret instructions to .word 0x30200073 (mret)Jonathan Neuschäfer
Using the opcode directly is necessary for the transition to the GCC 6.1.0 based toolchain, because the old toolchain only supports eret and the new toolchain only supports mret. Change-Id: I17e14d4793ae5259f7ce3ce0211cbb27305506cc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15290 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-18google/oak & elm: initialize touchscreen reset gpioYH Huang
In order to save power in S3, we remove reset gpio setting in kernel. We still need to initialize touchscreen ic. Do it by pulling low reset gpio for 500us and then pulling high in firmware. BRANCH=none BUG=chrome-os-partner:55170 TEST=build on elm. Change-Id: Idbe0175a1fc1fa0b05e81706194c79d52c6101f6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: f40cc9a22c2551c2c9455cb8b60f36353602bca6 Original-Change-Id: If2ac815c4fd5c5ae15443348a49eb31449b724b1 Original-Signed-off-by: YH Huang <yh.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/360312 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Johnny Chuang <johnny.chuang@emc.com.tw> Reviewed-on: https://review.coreboot.org/15719 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 06:08:37 +0000