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2016-03-09northbridge/intel/gm45: Use TSC for ramstage timer per defaultStefan Reinauer
This is a step towards isolating the timer drivers. Change-Id: I4c9349054be0cf520cd4407be9fb393b664223a4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13922 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-09payloads: Move secondary payloads inside of a submenuMartin Roth
To keep the list of 'secondary' payloads from cluttering the payloads menu, move them into their own menu under the payloads menu. Then they don't need any dependencies other than the architecture. Change-Id: I95119750c6ef627ef0de9b5f5cbad085a51ac2bb Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13941 Tested-by: build bot (Jenkins) Reviewed-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-09Makefile: Update payload clean targetsMartin Roth
Move payload clean targets into payloads/Makefile.inc Add clean targets for coreinfo, nvramcui, Memtest86+ Change-Id: I70c13582311dfba3e309805053159f8a039cb109 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13940 Tested-by: build bot (Jenkins) Reviewed-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-09drivers/intel/fsp2_0: remove struct resource usageAaron Durbin
There's no need to use a struct resource type for fsp_find_reserved_memory(). struct resource is mainly associated with a device and that memory is added to cbmem after memory init. Other uses ins FSP 2.0 just use struct range_entry. Use that instead for consistency. Change-Id: Id7d39da1c2e23f97cdaafd7f5d281cefa6fee543 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13960 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09drivers/intel/fsp2_0: add TODOs to fix deficienciesAaron Durbin
The FSP 2.0 implementation doesn't handle FSP modules for SoCs that are required to be XIP. There is no notion of "loading" in that situation where one should be copying anything anywhere. Additionally, the loading code does not handle overlaps within the current running program which is doing the loading. Change-Id: Ide145581f1dd84efb73a28ae51b3313183fa127a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13959 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09drivers/intel/fsp2_0: don't leak resourcesAaron Durbin
rdev_mmap() was not followed by rdev_munmap(), thus leaking resources. Fix the leak. Change-Id: Ibdd30d6b64616038013b4bb748f2ad4a98db5472 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13958 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09soc/intel/apollolake: correct comment to reference top of CARAaron Durbin
The memory provided to MemoryInit() for its own usage is at the top of the CAR region. Change-Id: I8685b5ab138182e24123b14cac6f7b32e5e784d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13957 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09lib/memrange: add function to initialize range_entryAaron Durbin
In order to enforce the semantics of struct range_entry provide an init function, range_entry_init(), which performs the field initialization to adhere to the internal struture's assumptions. Change-Id: I24b9296e5bcf4775974c9a8d6326717608190215 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13956 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09Add option for "timeless" buildsNico Huber
Builds with BUILD_TIMELESS=1 shall always give a bit identical output for stable inputs. This should help verifying that resulting rom files stay the same across commits that shouldn't change the outcome. To be useful for builds that rely on 3rdparty/arm-trusted-firmware, this needs a similar change there. Change-Id: Ia0a22e3e79fbd0abbd2a9071ecbeef6541787a08 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13412 Tested-by: build bot (Jenkins) Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-09payloads/seabios: Upgrade stable from 1.9.0 to 1.9.1Paul Menzel
SeaBIOS 1.9.1 was released on February 15th, 2016 [1][2] with the changes below. ``` $ git log --oneline --reverse rel-1.9.0..rel-1.9.1 3403ac4 build: fix typo in buildversion.py fe4154e xhci: Check for device disconnects during USB2 reset polling c016236 xhci: Wait for port enable even for USB3 devices 0240428 sdcard: Only enable error_irq_enable for bits defined in SDHCI v1 spec fe8d986 sdcard: fix typo causing 32bit write to 16bit block_size field e902d3f nmi: Don't try to switch onto extra stack in NMI handler dc6498e scsi: Do not call printf() from scsi_is_ready() 6027043 coreboot: Check for unaligned cbfs header 73f00bc fw/pci: do not automatically allocate IO region for PCIe bridges b3ef39f biostables: Support SMBIOS 2.6+ UUID format ``` [1] http://www.seabios.org/Releases#SeaBIOS_1.9.1 [2] http://seabios.org/pipermail/seabios/2016-February/010493.html Change-Id: I4bc8224c2a80cbcce54621e941a9c3a92ca04215 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/13933 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); Replace that with x86_setup_mtrrs_with_detect() since it is equivalent. Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13936 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-08nyan: Fix timestamps and CBFS SPI integrationJulius Werner
Nyan is an old board that was committed before several core code modernizations to timestamp and CBFS code. Not all of those later patches were correctly integrated with old boards like this, and the core code has evolved to a point where it doesn't actually boot anymore. This patch fixes that issue and brings the Nyan boards more in line with how later ARM platforms look. BRANCH=None BUG=None TEST=My Blaze boots again. Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717 Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328543 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/13832 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-03-08mainboard/skylake: Include WRDD method in WIFI ACPI deviceDuncan Laurie
Include the code to add the WRDD method to the existing WiFi Device in the mainboard ACPI code. BUG=chrome-os-partner:50516 BRANCH=glados TEST=boot on chell with 'region'='us' in VPD and see that it is properly read out by calling WRDD method on the WiFi device. Compile for the other platforms that are modified. Change-Id: Ibcff7585744071ba9018d0ba50e274e63365b150 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: b74bb553415f7ce224ddcb0c2c5ae509b8fed516 Original-Change-Id: Ieb24e0e64974ee3686d14a234e148f5d07fc8b12 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329296 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13840 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08skylake: Add and fill out CID1 NVS fieldDuncan Laurie
Add a country identifier field to NVS and populate it with the call to wifi_regulatory_domain() which will (by default) do a lookup for the 'region' identifier in VPD on a Chrome OS device. BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: Ie7531848e620095732772c22156a85b7f8a6df5c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: dafdb3760a0302e3effdc0e83977c1bfd5c9d3b2 Original-Change-Id: Ic83ab008045a469d0e0756f7e4d42f1b3894c529 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329295 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13839 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08intel/wifi: Add WRDD ACPI methodDuncan Laurie
Add an ACPI file containing a generic WRDD method that is used by Intel wireless kernel drivers to determine the country code to be used for regulatory domain configuration of the wireless radios. This requires an NVS variable called 'CID1' to provide an ISO-3166-2 alpha-2 country code or it will just return 0 instead. This is implemented as a bare method because this needs to be included directly into the wifi device that is defined by the mainboard as it may have board-specific settings like _PRW that need to be provided as well. BUG=chrome-os-partner:50516 BRANCH=glados TEST=boot on chell with 'region'='us' in VPD and see that it is properly read out by calling WRDD method on the WiFi device. Change-Id: I27a5e27f65d05ff62a0e79a87a32c1ef0c5d0ef3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 2da0cf76ca3cc5e3dfbc4a0859733523de780cf5 Original-Change-Id: I9d83c3938cceafc77ef8747a5c47f586ee84437e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329294 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13838 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08Chromeos: Modify wifi_regulatory_domain to use "region" key in VPDHuang, Huki
In ChromeOS VPD spec the right name is "region". Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://chromium-review.googlesource.com/322851 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: mukesh agrawal <quiche@chromium.org> (cherry picked from commit 21ea0663e7f3ffe3aaea6b6ce0e1216fcd9ca23e) BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: I4ba9a9c65af3732fa263030640495ab5bea91d1f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 848f18e731eb11dd3037d12607d7364f95e64e34 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ib96036f9cd76449f170af5c3dd6ef6e8e91ded94 Original-Reviewed-on: https://chromium-review.googlesource.com/329293 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08lib: Implement framework for retrieving WiFi regulatory domainFelix Durairaj
Platforms that need to initialize WRDD package with the regulatory domain information should implement function wifi_regulatory_domain. A weak implementation is provided here. Signed-off-by: fdurairx <felixx.durairaj@intel.com> Reviewed-on: https://chromium-review.googlesource.com/314384 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Commit-Queue: Hannah Williams <hannah.williams@intel.com> Tested-by: Hannah Williams <hannah.williams@intel.com> (cherry picked from commit c25d7221679d1fab830d614eeabfa3436bce6ac1) BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: I1cbdf4e940b009c74ee8ed8f4fca85f4f5c943b2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 27bba336e620a2d3d331e350d4f46164e337fabc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: I84e2acd748856437b40bbf997bf23f158c711712 Original-Reviewed-on: https://chromium-review.googlesource.com/329291 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08soc/intel/quark: Set the UPD values for MemoryInitLee Leahy
Set the UPD values for MemoryInit. * Update the FspUpdVpd.h file which specifies the parameters for MemoryInit. * Add the necessary values to chip.h to enable values to come from the mainboard's devicetree.cb file * Add the parameters to the mainboard's devicetree.cb file * Locate the platform configuration database file (pdat.bin) * Copy the data values from the chip_info structure into the UPDs * Display the UPD values Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful when the UPD data is displayed before the call to MemoryInit Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13896 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-08archive: build archive tool with HOSTCCDaisuke Nojiri
BUG=chromium:502066 BRANCH=tot TEST=Tested on Jerry Change-Id: Ic227287784bd0c76a0c4c20a40c581d37420b98c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1b4e818e91998135288978c6cb68a63288bb20e5 Original-Change-Id: I28f5decabcbaf1e61c9b4e549b11e568dace8c09 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312902 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12926 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08util: add archive toolDaisuke Nojiri
'archive' concatenates files into a single binary blob. Files are indexed by the base names. See archive.h for the format description. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: Iea108160e65c8c7bd34c02af824a77cb075ee64b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 21a9ba860f29599ac029f8d49d32399c4e3a73a8 Original-Change-Id: I46b4efb339e3a1e05772ae752f2861026ca09cfc Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311200 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://review.coreboot.org/12925 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-08soc/intel/apollolake: Add cbmem_top() implementationAndrey Petrov
On Apollolake CPU memory mapping is similar to previous SoC, and we place CBMEM right under TSEG. Change-Id: I606f690449ba98af6e9fc3074d677c7287892164 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13883 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08Kconfig: Remove unneeded UDELAY_IO redeclarationStefan Reinauer
UDELAY_IO is defined in src/cpu/x86/Kconfig, so it does not need to be redefined in the AMD cpu or board Kconfigs. Change-Id: I6676881c0ba5d1634230fc3d3c37da3afbc6fceb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13780 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08cpu/x86/mtrr: add helper function to detect variable MTRRsAaron Durbin
The current MTRR API doesn't allow one to detect variable MTRRs along with handling fixed MTRRs in one function call. Therefore, add x86_setup_mtrrs_with_detect() to perform the same actions as x86_setup_mtrrs() but always do the dynamic detection. Change-Id: I443909691afa28ce11882e2beab12e836e5bcb3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13935 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-03-08soc/intel/quark: Add the UPD support for SiliconInitLee Leahy
Add the routines to handle the UPDs for SiliconInit. Currently no support is required. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful if coreboot calls SiliconInit Change-Id: I5176ab4b1ea7681c3095f102a86f4b614366c0fc Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08crossgcc: Build make per defaultStefan Reinauer
Build make with the rest of the toolchain, since the targets using a Chromium EC need make 4.x Change-Id: I7efb0c25f605f16c2d9a1e7c4b203f3bcdae671b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13923 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08cpu/x86: Sort some Kconfig optionsStefan Reinauer
Change-Id: I25ea327ed151e18ccb5d13626d44925d2a253d08 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/10012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08soc/intel/apollolake: Enable using FSP 2.0 driverAndrey Petrov
Change-Id: I5d50fecca51e89aed597e1cfafbcd4515d4d4388 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08soc/intel/apollolake: Add romstage that calls FSP2.0 driverAndrey Petrov
This romstage is minimalistic. Its goal is to set up some BARs that FSP expects to be set and then invoke FSP driver to train memory. Change-Id: I3fa56aafe99cf6cf062a46dece3a0febeafdbfad Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13805 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08soc/intel/apollolake: Add support for memory-mapped boot mediaAndrey Petrov
On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13706 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add framebuffer graphics supportAlexandru Gagniuc
This adds a few helper functions that are intended to assist setting up framebuffer. Change-Id: Id8ed4de1f9de32e9222b0120c15a6d33676346e7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13802 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add hand-off-block parsersAlexandru Gagniuc
FSP creates hand-off-blocks (HOBs) to exchange information with coreboot. This adds a set of utilities to parse HOBs and extract some useful information from them. Change-Id: If55dbfaa021cd68c312813a5532a36c68806dbbc Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13801 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add Notify Phase APIAndrey Petrov
This adds Notify Phase API. This is an important call that is used to inform FSP runtimes of different stages of SoC initializations by the coreboot. Change-Id: Icec770d0c1c4d239adb2ef342bf6cc9c35666e4d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13800 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add SiliconInit APIAndrey Petrov
This adds SiliconInit API that is needed to be called after memory has been trained. This call is needed to let the blob do various initialisations of IP blocks. Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add MemoryInit APIAndrey Petrov
This adds implementation of fsp_memory_init() that is used to train memory. Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13798 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08roda/rk9: Remove #include early_serial.c from romstageAntonello Dettori
Remove dependency on early_serial.c and instead use the Super I/O's header to access the functions needed. Also re-organize some of the superio code in order to succesfully compile the rom. Change-Id: I85a6f1352ae3b91c3c98e4d3fa0b90b87e02babc Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/13925 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07MAINTAINERS: Add Timothy Pearson to the maintainers listMartin Roth
Change-Id: Ic0ae87ca1fff6d912702190d3fe8ab21285c8630 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13920 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-03-07intel/fsp_baytrail: use 20K PU/PD for GPIOBen Gardner
The E3800 datasheet only lists 2K and 20K Pull Strength for the GPIOs. The 10K and 40K values map to 'reserved'. This brings the code closer to the non-FSP baytrail. Change-Id: I77078bdbbccc00976525dc43fb98f5b2e79eae03 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/13907 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07soc/intel/quark: Split out MTRR supportLee Leahy
Split out the MTRR support into a new module: mtrr.c. TEST=Build and run on Galileo Change-Id: Ib9ec479d171dbbc062509e14fbe246f6d90e903a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-07mainboard/intel/galileo: Enable SD flash cardsLee Leahy
Turn on the SD controller to allow it to claim resources. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when at the UEFI shell prompt: * After issuing: * "connect -r" * "map -r" * The "dir" command displays the contents of the SD flash card * The "drivers" command shows an SD host and SD media connection Change-Id: I883dc87270045786ddb931bea83fc36646a128e6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-07Documentation/Intel: Add EDK-II linksLee Leahy
Add a link to the "Driver Writer's Guide" and a link to the "EDK II firmware for Intel Quark SoC X1000" document. TEST=None Change-Id: I8d629d06accfe24a0b8971b5b5868849587c3db7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13893 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-07Documentation/Intel: Making a bootable SD cardLee Leahy
Add a link to "Making a bootable SD card" TEST=None Change-Id: I5682fdd51a4ba37f97ad35475e11d9843f1498fb Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-05BuildSystem: Add Memtest86+ as a secondary payloadMartin Roth
This allows memtest86+ to be added to CBFS as a 'secondary' payload on x86 systems, to be loaded by the main payload if desired. Selecting this option, which defaults to no, builds the memtest86+ payload and adds it to CBFS as `img/memtest` which can then be loaded by for example SeaBIOS or GRUB. Change-Id: Iecf876aaf588ba1df7abdf6668cb26f089bf5f42 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13858 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2016-03-05tpm/acpi/tpm.asl: Only include tpm.asl if tpm is enabledMartin Roth
If the TPM code isn't getting built in, the Kconfig symbol CONFIG_TPM_TIS_BASE_ADDRESS doesn't exist. This ends up creating an invalid operating region in the ACPI tables, causing a bluescreen in windows. This should fix this issue: https://ticket.coreboot.org/issues/35 "commit 85a255fb (acpi/tpm: Gracefully handle missing TPM module) breaks Windows" Change-Id: I32e0e09c1f61551a40f4842168f556d5e1940d28 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-05arch/x86: Add common assembly code for stages that run in CARAndrey Petrov
This adds a few assembly lines that are generic enough to be shared between romstage and verstage that are ran in CAR. The GDT reload is bypassed and the stack is reloaded with the CAR stack defined in car.ld. The entry point for all those stages is car_stage_entry(). Change-Id: Ie7ef6a02f62627f29a109126d08c68176075bd67 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13861 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-05arch/x86: document CAR symbols and expose them in symbols.hAndrey Petrov
Attempt to better document the symbol usage in car.ld for cache-as-ram usage. Additionally, add _car_region_[start|end] that completely covers the entire cache-as-ram region. The _car_data_[start|end] symbols were renamed to _car_relocatable_data_[start|end] in the hopes of making it clearer that objects within there move. Lastly, all these symbols were added to arch/symbols.h. Change-Id: I1f1af4983804dc8521d0427f43381bde6d23a060 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13804 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-05lint-kconfig: pipe stderr to stdout to catch script errorsMartin Roth
Because the perl error messages go to stderr, we were not catching these on the build server. If the script has an issue, we want to know immediately, so change the bash script that calls into the perl lint tool to pipe these to stdout. Change-Id: Ieeec9ccbd59177cfd1859a9738a4ee1fab803d28 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13877 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-05amd/thatcher: Removed #include early_serial.c from romstageAntonello Dettori
Remove dependency on early_serial.c and instead use the Super I/O's header to access the functions needed. Change-Id: I9edf7fc2501aa832106dda9213e702dbcc1200b4 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/13887 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-03-05include/device/dram: Fix DDR3-1866Patrick Rudolph
The PLL multiplier value is off by one for DDR3-1866 due to a wrong TCK value, resulting in DDR3-1600 being used by the PLL. Needs test on real hardware ! Change-Id: I657b813889945f0d9990dd11680a3d3a25b53467 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13613 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-05sandybridge/gma_lvds: support both Sandy&Ivy on one boardIru Cai
Sandy and Ivy Bridge processors use the same socket, and a mainboard with the socket can support both types of CPUs. However, they use different native graphics init code for LVDS and cause a crash if running the wrong code. This change detects the CPU type and then selects the right code to run. It will add some more code in ramstage. It also merges the {SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS. Tested on a Lenovo T520 with i7-2630qm and i7-3720qm Signed-off-by: Iru Cai <mytbk920423@gmail.com> Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91 Reviewed-on: https://review.coreboot.org/12087 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2016-03-05Hide EC_GOOGLE_CHROMEEC_SPI_BUS.Vladimir Serbinenko
It's mobo architecture, not a user-adjustable setting. Change-Id: I8bb81638f391cf0ba880801e4707d8f0957897c8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13906 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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