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2012-03-27Add RDC R8610 PCI IDs.Rudolf Marek
Change-Id: I3f3585f15265aa1377f72ba23accf1adb08cb8ac Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/806 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-26Fix cleaning SeaBIOS from coreboot makefileMarc Jones
The coreboot makefile didn't pass the OUT and CC variables to seabios, so the clean didn't clean anything. Change-Id: Ieaf0c417d6e5dfb9e0a11df70b03d6313919578b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/801 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-26Disable the GDB stub by defaultRudolf Marek
I would prefer to see the exception dump on serial rather than cryptic GDB protocol. Change-Id: Ib25513d33e6a31da24586fecb00adb5206bb43bd Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/811 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-03-25Fix possible deadlock on SMP stop_this_cpuKyösti Mälkki
Do not use printk on the running thread after it has been sent the INIT IPI, execution may halt with console spinlock held. Change-Id: I64608935ea740fb827fa0307442f3fb102de7a08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/776 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-25Intel cpus: Fix deadlock on hyper-threading initKyösti Mälkki
Only the BSP CPU was able to start its hyper-threading CPU siblings. When an AP CPU attempts this it calls start_cpu() within start_cpu(), deadlocking the system with start_cpu_lock. At the time intel_sibling_init() is run, the BSP CPU is still walking the cpu_bus linked list in lapic_cpu_init: start_other_cpus(). A sibling CPU appended at the end of this list will get started. Also fail compile with #error if SERIAL_CPU_INIT==0, as microcode updates on hyper-threading sibling CPUs must be serialized. Tested with HT-enabled P4 Xeons on dual-socket604 platform. Change-Id: I0053f58f49ed604605ce0a55e826d3e1afdc90b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/775 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-25Makefile: rename linker intermediate variableKyösti Mälkki
Renamed CONFIG_ROMBASE to ROMSTAGE_BASE and removed it from Kconfig. Removed no-op calculation in ldscript. Change-Id: I53d39b60f07db76c8537b3133e59360687b9d4a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/802 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-25gitconfig: Improve commit-msg hookPatrick Georgi
There was some corner case where commit-msg failed. Update to latest upstream version. Change-Id: I822d6c3f64728de7356401465e00575ac5af8196 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/798 Tested-by: build bot (Jenkins) Reviewed-by: Bernhard Urban <lewurm@gmail.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-25Replace ramtest pattern to assist in DIMM configurationKyösti Mälkki
This is developer's testtool. Output from a "rotate ones" -style pattern helps figure out how DIMM addresses are encoded or routed on a certain mainboard. Scattered test should cover every data and address lines on the memory bus, but is probably limited to the first bank of first DIMM. Change-Id: I533a7a873bcc434f99e7faed9dc9337d9ab64196 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> [pg: rebase] Reviewed-on: http://review.coreboot.org/294 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-24i82801gx: Support power-on-after-power-fail betterPatrick Georgi
Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/444 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-24i82801gx: Use CMOS variable if available for power-on on power failurePatrick Georgi
We used a hard coded value for some reason. Don't do that, but use CMOS instead. Change-Id: Ib83aa07a3e55bed075150354a060317ebc9d5ba7 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/443 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-24printf: Remove some L modifier usesPatrick Georgi
We use the L modifier in a non-standard way (for long long instead of long double, which we have no business with). clang complains, to reduce its use, to make emulation/qemu-x86 happier. Long term, we should consider eliminating public uses of 'L' (but internal use in vtxprintf to denote long long is fine) Change-Id: If9a17d9ae9925cdc8736445e7d5eedc59c7028c6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/781 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-21Fix libpayload alloc() size and gcc pointer optimization problems.Marc Jones
The previous commit was incomplete and missed setting the entire alloc area. There are also additional problems with gcc optimizations of the pointer math. The "auto" casting by gcc wouldn't return warnings, but it was causing the optimization to be incorrect. We are now very explicit in the casting in the pointer math. Change-Id: I020808c8d1dda544fe862b9efb0e5345eeab5aab Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/804 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-20Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 ↵Rudolf Marek
class cpu. Change-Id: Ic7c4452a1b55bae0cefee118003540ec39ef9fd4 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/683 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-17Another indirection for normal/fallback bootblockPatrick Georgi
Provide a way to redefine the names of normal and fallback via CBFS. This way updates can use some more expressive naming scheme (numbers, dates, version numbers) and replace the coreboot-stages file to point to the new version (with the current version as new "old"). If coreboot-stages doesn't exist, the default behaviour remains to use "normal" and "fallback". Change-Id: I77c134d79ed95831ad5098b7663c15e95d3b5a2a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/589 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-17Intel cpus: Include CAR from socketKyösti Mälkki
It was not obvious which CAR was compiled in. Also build would fail if a socket included two models with both having an include for CAR. Change-Id: I000c2e24807c3d99347a43d120333c13fbf91af4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Fix AMD Fam15 CBMEM allocationStefan Reinauer
The Fam15 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: I8a00e05884bdb1d1a4a012433b0adfbb9eb22983 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/796 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16Fix AMD Fam12 CBMEM allocationStefan Reinauer
The Fam12 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: I1eca18e21fa59ae32e802d8452e42e8b7a3575cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/795 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16Fix AMD Fam10 CBMEM allocationStefan Reinauer
The Fam10 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: Id6c4128d8f5f6a417f83daa3a39b2bfc8e810f8a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/794 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16AMD Agesa: delete no-op bootblock filesKyösti Mälkki
Removes files: src/northbridge/amd/agesa/family10/bootblock.c src/northbridge/amd/agesa/family12/bootblock.c src/northbridge/amd/agesa/family14/bootblock.c src/northbridge/amd/agesa/family15/bootblock.c Change-Id: Ic3617a673b38d065ca272c4de8ef765ecd3f98b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/793 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki
Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove the explicit selects from the mainboards. Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/792 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Fix AMD Agesa leaking KconfigKyösti Mälkki
Kconfig leaked XIP_ROM_SIZE to other platforms and also defined obsolete option XIP_ROM_BASE. Alias AMD_AGESA as NORTHBRIDGE_AMD_AGESA. Break the circular dependency with family15 Kconfig. Change-Id: Ic7891012220e1bef758a5a39002b66971d5206e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/773 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16ROMCC boards have no XIP limitPatrick Georgi
So set their XIP configuration to ROM_SIZE. Change-Id: I6c1abccec3b1d7389c85df55343ff0fc68a61eec Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/797 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2012-03-16Use search path when building dependenciesPatrick Georgi
clang is more picky on that. Change-Id: Iaa8472beb6e275c39037d11e1a72dbb80d46424b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/779 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-16xchg is atomic with side-effectsPatrick Georgi
clang doesn't know about the side effect, so we have to tell it that it's okay not to care about the result. Change-Id: Ib11890bff6779e36cf09c178d224695ea16a8ae8 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-16clang: Don't use mmx nor ssePatrick Georgi
clang is much more trigger happy than gcc on those. Change-Id: Ie7c219de3cc26675692eab7361a4ad551f1c65a7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/786 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-16Intel northbridge I945: Apply un-written naming rulesKyösti Mälkki
Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build. Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time which model of I945 the driver is built for. Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/684 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Via Epia-N and C3: Set ioapic delivery type in KconfigPatrick Georgi
The original comment says it's a Via C3 and not Epia requirement to deliver IOAPIC interrupts on APIC serial bus. Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/435 Tested-by: build bot (Jenkins)
2012-03-16VIA southbridge K8T890: Apply un-written naming rulesKyösti Mälkki
Use separate Kconfig option to select a driver directory for build and the specific type of southbridge to support. Change-Id: I9482d4ea0f0234b9b7ff38144e45022ab95cf3f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/685 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Fix address of IDT in real-mode entryKyösti Mälkki
In a case of CS & 0x0fff != 0x0, lidt memory operand does not point to nullidt, this can raise an exception and shutdown the CPU. When an AP CPU receives 8-bit Start-Up IPI vector yzH, it starts execute at physical address 000yz000H. Seems this translates to either yz00:0000 or y000:z000 (CS:IP), depending of the CPU model. With the change entry16.inc is relocatable as the commentary suggests and can be used as ap_sipi_vector on SMP systems. Change-Id: I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/707 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Fix AMD Fam14 cbmen allocationMarc Jones
The Fam14 northbridge.c had hardcoded the cbmem size. It should use in cbmem.h instead. Change-Id: I910329fc98a4cf04dc81ef66f3aa05a1916f5b1d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/790 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-03-15Clean up whitespace in fam14 northbridge.cMarc Jones
Change-Id: Id7947d7f3c67fdda67861065b1bc7a519b97208f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/789 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-14Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is availableGabe Black
Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available by including byteorder.h Change-Id: I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/709 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-14AGESA family 12 changes to fix torpedo warningsMartin Roth
Fixes the warnings generated in the torpedo mainboard build by AGESA. Removing broken tests. Change-Id: Ib444fa2bf4dd94cadb4ce33040eb5650d1c0325b Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/667 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-13Union Station: Fixes to turn on HDMIFrank Vibrans
This commit includes the changes to enable the HDMI on Union Station. The changes switch the output from the display port to the HDMI. Change-Id: I4e15ff6db7d056f156791ff1406d4bae35ff2767 Signed-off-by: Frank Vibrans <frank.vibrans@se-eng.com> Reviewed-on: http://review.coreboot.org/788 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-13Union Station: Remove SIO supportFrank Vibrans
Because the Union Station platform doesn't have an SIO chip, this commit removes the Fintek SIO support. Change-Id: Idba4222ce136821dee2530a72d1630eb5ad613a2 Signed-off-by: Frank Vibrans <frank.vibrans@se-eng.com> Reviewed-on: http://review.coreboot.org/787 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-03-11No need to setup include paths with .s filesPatrick Georgi
They're already preprocessed, and clang whines. Change-Id: I57fe936f84a2fe1aa50ee8510fef606f2ed2ea23 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/782 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-03-11malloc: size is unsigned, don't test for size < 0Patrick Georgi
clang complains Change-Id: Ifadf73cf377c0d1808e20731803e01101bad7e1d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/780 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-03-11mainboard/aopen/Kconfig: remove extra whitespacePatrick Georgi
Change-Id: I69ee67c35113d98e034bdccf5d00e8452d3d9bd2 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/778 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-10Portability improvementPatrick Georgi
Makefile.inc uses $( ) syntax on the shell. That's isn't as universal as one would like. Change-Id: I9a8fd511eef7fefc1458d5bae2cd7ef5475b7392 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/777 Tested-by: build bot (Jenkins) Reviewed-by: Bernhard Urban <lewurm@gmail.com>
2012-03-10Make libpayload alloc() memory pointers volatileMarc Jones
gcc4.6.2 was optimizing the libpayload alloc() function and failing to reload a pointer after the memory had been manipulated by a pointer in the inlined function setup(). Change the pointer type to volatile and now pass it to the setup() function. Also clean up the declaration so that it isn't cast a bunch times in the function. Change-Id: I1637bd7bd5d9cf82ac88925cbfe76d319aa3cd82 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/705 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-10If the memory mapped UART isn't present, leave it out of the cb tables.Gabe Black
This way u-boot won't try to use a UART that isn't plugged in. Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/729 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-03-10tell superiotool about the ITE 8772Stefan Reinauer
no dumping yet Change-Id: I4e687ca816c8d6d1c95255b0abf6a19513e23f86 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/734 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-09Increase size of the coreboot table areaStefan Reinauer
Packing a device tree into the coreboot table can easily make the table exceed the current limit of 8KB. However, right now there is no error handling in place to catch that case. Increase the maximum memory usable for all tables from 64KB to 128KB and increase the maximum coreboot table size from 8KB to 32KB. Change-Id: I2025bf070d0adb276c1cd610aa8402b50bdf2525 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/704 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Fix compilation when USE_OPTION_TABLE is not defined.Duncan Laurie
Change-Id: Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/702 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Fix coreboot table size calculations.Vadim Bendebury
The code when reporting the coreboot table size did not account for the last added table record. This change fixes the problem. . rebuild coreboot, program it on the target, restart it . look for 'Wrote coreboot table at:' in the console log . observe the adequate table size reported $ grep 'Wrote coreboot table:' /tmp/cb.log Wrote coreboot table at: 00000500, 0x10 bytes, checksum c06f Wrote coreboot table at: 7f6fc000, 0x1a73 bytes, checksum 3e45 $ Change-Id: Ic55501a4ae06fab2bcda9aea58e362325f2edccf Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/703 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Clean up use of CONFIG_ variables in coreboot_table.cStefan Reinauer
CONFIG_ variables are used inconsistently within the file src/arch/x86/boot/coreboot_table.c. #ifdef will do the wrong thing if the option is disabled. #if (CONFIG_FOO == 1) is not needed. Change-Id: Ifcac6ceac5fb34b931281beae500023597b3533b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/701 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-09Fix dependency problem for uart8250.c as wellStefan Reinauer
If you build in parallel, option_table.h will occasionally not be there yet and the build will fail. Change-Id: I828956ab2e05c48d20c2f7c55616cc8fa19e1227 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/698 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-09Fix compilation with CONFIG_USE_OPTION_TABLE enabledStefan Reinauer
Change-Id: I6c5d973442bc1770702180a8964f1bf6ed6062ed Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/696 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Add helper function to find a Local APIC by ID in the device tree.Duncan Laurie
Change-Id: Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/695 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Don't try to compute I/O for empty sub buses.Stefan Reinauer
I am not sure if the sub bus being 0 is a problem, or if the assumption there has to be at least one non empty link is just wrong. It certainly does not hurt to add a small consistency check in either case. Change-Id: I098446deef96a8baae26a7ca1ddd96e626a06dc5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/693 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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