Age | Commit message (Collapse) | Author |
|
Without the brackets, the string seems to be added as a list of
characters, and since there's no extension called 's', sphinx
bails out.
Change-Id: If0fc9c1a74f334b6154df3cb26836509de913567
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44114
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Remove const struct imd *imd and const struct imdr *imdr parameters from
the prototypes of imdr_entry_size(), imd_entry_size() and imd_entry_id()
functions since they are not used anywhere.
Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: I6b43e9a5ae1f1d108024b4060a04c57f5d77fb55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43999
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ib7c6ab0a2e5a03f30b70c4bbb1091fa9c689c23b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44094
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In kernel clk for AMD SoCs we expose a generic clk by the name oscclk1.
This oscclk1 is a fixed 48Mhz frequency clk in RV.
In Zork oscout system clock is linked to rt5682 mclk. Setting mclk-name to
oscclk1 tells rt5682 driver its mclk is oscclk1.
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
BUG=b:158906189
TEST=rt5682 driver get the correct clk and tested audio playback
Change-Id: Ic565e8e0573e085e5759b2d3688cc0a4533b67fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
RV has difference in clk framework. In RV we get a 48Mhz fixed clk,
while in ST we had 25Mhz, 48mhz clocks and a Mux to select between them.
To differentiate set the fmw property to 1 for boards using RV family of SoC.
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
BUG=b:158906189
TEST=rt5682 driver get the correct clk and tested audio playback
Change-Id: I685ded1607c2c7edc5e48f0bada258ebde192bb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook
firmware)
- Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick
- VGA: Video works with VGA rom extracted from UEFI
- SeaBIOS (runs the option rom) tested, works in text mode
- GRUB2 (coreboot runs the option rom) tested, works in VESA mode,
no video in text mode
- USB: Both USB2.0 ports work using the EHCI controller
- Works in both SeaBIOS, GRUB2 and Linux
- Serial: driven by an IT8728F SuperIO
- Works as a console in coreboot, SeaBIOS and GRUB2
- Works with interrupts in Linux after a cold boot, after a warm
reboot IRQs get lost
- SATA: 2 ports on board (one is mSATA)
- SATA init works with both refcode.elf and native refcode
(patch CB:43133)
- Booting from SATA works with GRUB2, SATA works in Linux
- Patch CB:44088 fixes SATA in SeaBIOS
- 4 PCIe Intel ethernet controllers
- Only tested in Linux, all 4 work with the igb driver
- Power button, reset button and both indicator LEDs work
- Optional fan header is not tested as the appliance is passively
cooled
- TXE (ME): optional, does not shut down after 30 minutes without the
TXE blob
- Works with TXE blob left as is, shows up on PCI
- Works with the entire TXE section wiped, no device on PCI,
intelmetool can't find anything
Used rambi as an example, but almost everything is modified as the two
boards are very different.
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
- The Bay Trail MRC fails to read the SPDs from SMBus.
- Instead the SPDs are read into a buffer and the buffer is passed to
the MRC.
Change-Id: I7f560d950cb4e4d118f3ee17e6e19e14cd0cc193
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44092
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This follows CB:44047 which probably missed this because it's a
custom assert macro (in code that has only recently been added to
build checks). Without this change, building with gcov fails because
gcc_assert(0) can be build-time verified (as introduced by CB:44044)
while we need runtime failure semantics here.
Change-Id: I71a38631955a6a45abe90f2b9ce3a924cc5d6837
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Before this change, we have this problem (boot log from DeltaLake
config A server):
Jumping to boot code at 0x00040000(0x755f6000)
Stack overrun on CPU0 (address 0x7574a000 overwritten). Increase stack from current 4096 bytes
ERROR: BUG ENCOUNTERED at file 'src/lib/stack.c', line 43
Linux version 4.16.18
Configure STACK_SIZE to make it larger to fix above problem.
Now, we have this boot log:
BS: BS_PAYLOAD_LOAD exit times (exec / console): 326 / 21727 ms
Jumping to boot code at 0x00040000(0x752f2000)
CPU0: stack: 0x75746000 - 0x7574a000, lowest used address 0x7574681c, stack used: 14308 bytes
Linux version 4.16.18
TESTED=booted YV3 config A to target OS.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ia04a3ee0cd37177ecab65469855a1cf920742458
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2. SKX-SP continues
to select PLATFORM_USES_FSP2_0, as SKX-SP FSP is FSP 2.0.
Correct DCACHE_RAM_BASE. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE,
and adjust DCACHE_RAM_SIZE accordingly. Thus the workaround of hardcoding
StackBase and StackSize FSP-M UPD parameters is removed.
Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable()
to indicate that FSP-S multi phase init is not enabled, since it is
not supported by CPX-SP FSP.
TESTED=booted YV3 config A to target OS.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44049
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Some settings are suspicious, and have been annotated with FIXMEs.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I7755867cb92745f542a4261db5dd118ca905612b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I44db564c757647f493e92d35602178ef8b722517
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Like the QPI Link device, there can be more of these devices on
multi-socket platforms. So, name it Physical Layer 0.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: Ia5f6e42a742bc69237de38f1833e56c8da7c4f7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Id226a2fdcbd0fe48822c4f65746e14fb00db6b2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
On multi-socket platforms, there can be two QPI buses, each with its own
PCI device. We only have one QPI link on Arrandale, though. In case
support for multi-socket processors ever gets added, name it Link 0.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This register resides within the SAD's config space, and is 64-bit.
Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Let's hope this cheers up the poor System Address Decoder device.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Only some registers have such a prefix. Drop it for consistency.
Change-Id: I1ef7307d10a06db8f3c1a05bd9184f21fceb9d90
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Uppercase variable names can be confused with register definitions. Use
lowercase names instead, conforming to the coding style guidelines.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I61a28bf964ea8c2c662539825ae9f2c88348bdba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This is the only instance of `BETTER_MEMORY_MAP` in the tree.
Change-Id: I118e5b5a0f10da56e2335828477caed81c5bf855
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This register does not seem to exist on Ironlake.
Change-Id: I3fba6a3fd443f2c9eab874e1d1b8f081f58b1536
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Remove duplicated definitios and sort them by ascending offsets.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: Idcfa64a39c12a4ac06a342ef9b51a01b806d4c84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Looks like some registers are defined twice. Also, group some QPI
registers together. They were scattered around and mixed with the host
bridge registers, probably because other northbridges have such
registers in the host bridge's PCI config space. But not Ironlake.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I6e60f7fcb1467f302618eeab1b0d995920a98569
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Sort them by ascending offsets.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I521aa3e49b17a9fb6b279ae758801356e510d054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.
Change-Id: I12d6adb8f130599a33d71d7c9f71914ee7c9e8ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I8d68a1dd49769ac49009a8e628f7994bf461a05f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I2c59099f6ff0e9162c700c888fb8fbb3906b65e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Observed thermal shutdown initiated by DPTF due to CPU temperature
reaching critical temperature trip value. During stress testing with
heavy workload like WebGL Aquarium, sometime CPU temperature spikes
till 99 degree Celsius and DPTF initiates system shutdown. This
updates CPU critical temperature trip value to 105 degree Celsius
to avoid system shutdown.
BUG=b:161993459
BRANCH=None
TEST=Built and tested on dedede system
Change-Id: If15a873a997aa80f20940f27bbafd4498908c091
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44054
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Support 8GB MT53E2G32D4NQ-046 discrete DDR bootup.
BUG=b:159301679
BRANCH=kukui
TEST=Boots correctly on Kukui.
Change-Id: Ide01f029c5ebd6c3ae6350f73f3c60b818d51353
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Implement setting processor information to BMC based on
document YosemiteV3_BMC_Feature_Spec_v1.7.
TEST=Use get command in OpenBMC to check.
Command and information are shown as below:
root@bmc-oob:~# ipmi-util 1 0xd8 0x11 0x4c 0x1c 0x00 0 1
DC 11 00 47 65 6E 75 69 6E 65 20 49 6E 74 65 6C 28 52 29
20 43 50 55 20 30 30 30 30 25 40 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00
root@bmc-oob:~# ipmi-util 1 0xd8 0x11 0x4c 0x1c 0x00 0 2
DC 11 00 1A 34 00 DC 05 41 30
root@bmc-oob:~#
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I3d53ac241a11ca962572816283a0c653fcde9f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Some UPD options are already set in `xeon_sp/cpx/romstage.c`. Remove
them from the board configuration to avoid duplicating this code.
Change-Id: Ic79245103c33427e06c7ea881be778e3d219c45f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43924
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
According to src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h,
use FSP_M_CONFIG structure fields to configure UPD options for FSP-M
in romstage instead of raw offsets.
Change-Id: Idb25d8954b09805b496ab97b341a8ef1ac38bb6a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add RTL8822CE support for Madoo.
BUG=b:162390420
BRANCH=None
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage, build successful
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I6e471be2b2856977e6f728d5a2ca78942725bea6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
1. Add Elan touchpad support.
2. Follow schematic to disable I2C1 and I2C3.
BUG=b:160869188,b:161407664
BRANCH=NONE
TEST=emerge-dedede coreboot chromeos-bootimage", build successful
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I154a1ff2597968d200d1d0693718f90cd2744616
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
Add Goodix touchscreen support.
BUG=b:160868197
BRANCH=None
TEST=emerge-dedede coreboot chromeos-bootimage", build successful
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I9bf27d69d0895cb4ea8620a6da49e98d25e05c23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44012
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1. Add _DSM method
2. Add support to turn on/off the power enable signal in _PS0/_PS3
methods.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I4f944caa535bdc946eef1e0f518fe3ee344187b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
Converts bit fields macro to target PAD_CFG_*() macros, which were
hidden in the comments. To do this, the following command was used:
./intelp2m -n -t 1 -p apl -file ./test/up-gpio.h
This is part of the patch set
"mb/up/squared: Rewrite pad config using intelp2m":
CB:42608 - 1/3 Decode raw register values
CB:42915 - 2/3 Exclude fields that are not in PAD_CFG*
CB:39765 - 3/3 Converts bit field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I266ec6fa10a9691a7b7d3cd6f2792624e8bd53d5
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch excludes bit fields that must be ignored in order to convert
current macros to target PAD_CFG_*() macros. The following commands
were used for this:
./intelp2m -ii -fld cb -ign -t 1 -p apl -file ./up-gpio.h
This is part of the patch set
"mb/up/squared: Rewrite pad config using intelp2m":
CB:42608 - 1/3 Decode raw register values
CB:42915 - 2/3 Exclude fields that are not in PAD_CFG*
CB:39765 - 3/3 Converts bit field macros to PAD_CFG
Change-Id: Ic9b6e63c1b84b97726886bef35c434dd9153eb78
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
|
|
Use the intelp2m utility [1] with -fld=cb options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to
generate the target macro in the comments, so that it is easier to
understand what result we should get:
./intelp2m -ii -fld cb -t 1 -p apl -file ./up-gpio.h
This is part of the patch set
"mb/up/squared: Rewrite pad config using intelp2m":
CB:42608 - 1/3 Decode raw register values
CB:42915 - 2/3 Exclude fields that are not in PAD_CFG*
CB:39765 - 3/3 Converts bit field macros to PAD_CFG
[1] https://review.coreboot.org/c/coreboot/+/35643
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I2523439af8842365c7de901bdfad85ad16d25dcf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
From a log of a machine using Crystal Well CPU [1], Crystal Well CPUs
use some new PCI IDs. Without this patch, the Crystal Well northbridge
cannot be initialized in ramstage, thus the machine cannot boot. Some
PCI IDs of Crystal Well related devices can be found in the PCI ID
database [2].
Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS. The board
boots to SeaBIOS with boot screen displayed on HDMI output, and then
boots Arch Linux on a USB disk.
[1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/DNHLQTNTRQT43T67DG7L2HVI5CV74ZCM/
[2] https://pci-ids.ucw.cz/read/PC/8086
Change-Id: Icfe55323fd06187148c788ebfa7b679b6944e4f3
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41658
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Without this change, there will be no console output when using a
Crystal Well CPU.
Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS.
Change-Id: Id18645c52d9c4a4ea7acb602bcb39b796d9e24b9
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Many places in coreboot seem to like to do things like
assert(CONFIG(SOME_KCONFIG));
This is somewhat suboptimal since assert() is a runtime check, so you
don't see that this fails until someone actually tries to boot it even
though the compiler is totally aware of it already. We already have the
dead_code() macro to do this better:
if (CONFIG(SOME_KCONFIG))
dead_code();
Rather than fixing all these and trying to carefully educate people
about which type of check is more appropriate in what situation, we can
just employ the magic of __builtin_constant_p() to automatically make
the former statement behave like the latter.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I06691b732598eb2a847a17167a1cb92149710916
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
I would like to make assertions evaluate at compile time where possible,
but sometimes people used a literal assert(0) to force an assertion in a
certain code path. We already have BUG() for that so let's just replace
those instances with that.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I674e5f8ec7f5fe8b92b1c7c95d9f9202d422ce32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
According to my SC7180 reference manual, these three GPIOs are in the
NORTH TLMM, but our pin table lists them as SOUTH. That means all
accesses our code has been doing to them have just been hitting empty
address space.
BUG=b:160115694
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If9c03ac890a7975855394c2e08b8433472df204d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Adding implementation of standard library strstr()
See https://review.coreboot.org/c/coreboot/+/43741 for context.
Change-Id: I63e26e98ed2dd15542f81c0a3a5e353bb93b7350
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|