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2012-03-09Increase size of the coreboot table areaStefan Reinauer
Packing a device tree into the coreboot table can easily make the table exceed the current limit of 8KB. However, right now there is no error handling in place to catch that case. Increase the maximum memory usable for all tables from 64KB to 128KB and increase the maximum coreboot table size from 8KB to 32KB. Change-Id: I2025bf070d0adb276c1cd610aa8402b50bdf2525 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/704 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Fix compilation when USE_OPTION_TABLE is not defined.Duncan Laurie
Change-Id: Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/702 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Fix coreboot table size calculations.Vadim Bendebury
The code when reporting the coreboot table size did not account for the last added table record. This change fixes the problem. . rebuild coreboot, program it on the target, restart it . look for 'Wrote coreboot table at:' in the console log . observe the adequate table size reported $ grep 'Wrote coreboot table:' /tmp/cb.log Wrote coreboot table at: 00000500, 0x10 bytes, checksum c06f Wrote coreboot table at: 7f6fc000, 0x1a73 bytes, checksum 3e45 $ Change-Id: Ic55501a4ae06fab2bcda9aea58e362325f2edccf Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/703 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Clean up use of CONFIG_ variables in coreboot_table.cStefan Reinauer
CONFIG_ variables are used inconsistently within the file src/arch/x86/boot/coreboot_table.c. #ifdef will do the wrong thing if the option is disabled. #if (CONFIG_FOO == 1) is not needed. Change-Id: Ifcac6ceac5fb34b931281beae500023597b3533b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/701 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-09Fix dependency problem for uart8250.c as wellStefan Reinauer
If you build in parallel, option_table.h will occasionally not be there yet and the build will fail. Change-Id: I828956ab2e05c48d20c2f7c55616cc8fa19e1227 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/698 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-09Fix compilation with CONFIG_USE_OPTION_TABLE enabledStefan Reinauer
Change-Id: I6c5d973442bc1770702180a8964f1bf6ed6062ed Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/696 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Add helper function to find a Local APIC by ID in the device tree.Duncan Laurie
Change-Id: Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/695 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Don't try to compute I/O for empty sub buses.Stefan Reinauer
I am not sure if the sub bus being 0 is a problem, or if the assumption there has to be at least one non empty link is just wrong. It certainly does not hurt to add a small consistency check in either case. Change-Id: I098446deef96a8baae26a7ca1ddd96e626a06dc5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/693 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09OXPCIe: Reinitialize UART after pci_dev_set_resources()Stefan Reinauer
... and only pull in early init code if the OXPCIe is used for console. Change-Id: I01feca3b9e8376a75c17554ba1bd200d523dff8d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/692 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09move console includes to central console/console.hStefan Reinauer
Because it's included everywhere anyways. Change-Id: I99a9e6edac08df57c50ef3a706fdbd395cad0abc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/691 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Add support for the Startech PEX1XS1PMINIStefan Reinauer
It has a smaller footprint than the already supported MPEX2S952 Change-Id: Ie36b67f9628882d516ca34ff164f0e8918955a5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/690 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Don't run any Option ROMs stored outside of the system flashStefan Reinauer
Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-03-09Add an implementation for the memchr library functionGabe Black
Change-Id: Icded479d246f7cce8a3d2154c69f75178fa513e1 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/708 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-03-09Fix lint-stable checkin hooks on MacOS XStefan Reinauer
- wc adds a number of leading spaces which broke cut - sed can't replace spaces with new lines, so use tr for that. - make sure directories are created if they're not there. Change-Id: Ia0db059683abe3d97b0ab6feaece660a1f4e5079 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/774 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-08Don't run VGA option ROMs on S3 resume.Stefan Reinauer
This will save us a few 100 ms on resume. Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/715 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-08Unify Local APIC address definitionsPatrick Georgi
We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-08Add support for A-Open DXPL Plus-U motherboardKyösti Mälkki
This is an old (pre-2005) entry-level server mainboard. The code is adapted from mainboard/intel/xe7501devkit. Featured chips: - Dual socket604 - E7505 northbridge - 82801DB southbridge (with EHCI debug port) - 82870p2 PCI-X bridge - LPC47M102S-MC super-io - 512kB FWH flash (flashrom does the job well) What works: - Dual-Xeon P4/HT boot with microcode update - RAM: registered ECC DDR266 in dual-channel - PCI-X slot interrupts with ACPI and I/O apic - On-board PCI-X GbE and SCSI - ACPI power-off and wakeup with PME# Notes : - Current ACPI is more or less a mess - Interrupts do not route correctly with PIRQ - MP-table is not implemented - Issues with reboots remain (cold and warm) - Many superio devices are disabled by default - Audio codec is not investigated Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/303 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-07Move C labels to start-of-linePatrick Georgi
Also mark the corresponding lint test stable. Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-07lint: test that labels begin at start-of-linePatrick Georgi
Some attempt at enforcing style Change-Id: Ibbfb86402ecc57e8db6c3857c8e0193085ed4fc2 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/771 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-07correctly mark code segments as code in SELFStefan Reinauer
In bios_log, find that the first segment of the payload is shown as code rather than data. Sample: Got a payload Loading segment from rom address 0xfff29378 code (compression=1) ... Change-Id: I82eaad23f08c02f4ed75744affa8835255cf5c17 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/767 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-07selfboot: drop dead codeStefan Reinauer
As a left over from elfboot times, selfboot keeps the segments to load in the order in which they appeared in the original file as well as in the order they will later appear in memory. This is not needed in selfboot, so drop the code and structure members that handle the in-file order. Change-Id: I6be7a3a1bdf717fec1ee8e5b3227c63150580b41 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/768 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-06Revert "Use -mno-sse to prevent overzealous gcc optimizations"Patrick Georgi
AGESA uses SSE intrinsics :-( This reverts commit 05f4b03fb64999ba373fe61256f358e5371bf8ae Change-Id: I7c48e07a261eafda2119354d282bd05eac5a14b6 Reviewed-on: http://review.coreboot.org/706 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-03-03Use -mno-sse to prevent overzealous gcc optimizationsStefan Reinauer
The offending part that made coreboot crash with some toolchains was that gcc emits SSE instructions but coreboot did not enable SSE at that point. Since the gain for coreboot using SSE instructions is not measurable, let's not use SSE instructions rather than enabling SSE early on. One rationale behind this is that other parts of coreboot, like the SMM handler would need fixing because the XMM registers are not saved on SMM entry. Thus keep it simple. Change-Id: I14f0942f300085767ece44cec570fb15c761e88d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/694 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-02Fix ECC disable option for AMD Fam10 DDR2 and DDR3.Marc Jones
The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/670 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-01gitconfig: Add lint-stable as pre-commit hookPatrick Georgi
When configuring the tree with "make gitconfig", a pre-commit hook is installed that runs the stable lint tests. If any of these fail, the log is visible (on stdout) and the commit is aborted. Change-Id: Ie2a26e87f466c63b24db8dca8827057a18ac7f3e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/682 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-01lint: create two classes of tests, stable and devPatrick Georgi
We have tests that pass (and should be enforced soonish) and those that don't pass yet (and thus shouldn't break the build). The plan is simple: As soon as a test passes, it's marked stable so things remain that way. "make lint" runs all tests, "make lint-stable" runs only those that shouldn't fail. Change-Id: Iaa85d71141606d9756e29b37c7a34c2a15e573ac Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/681 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-01Fix lint test for build directoriesPatrick Georgi
config files are rename()d, which fails across filesystem borders. So force temporary config files in current directory. Change-Id: I583c2ab9a822a6f99f838778aa17ffd2d47eaed1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/680 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-01Drop support for BROKEN markerPatrick Georgi
We used to support marking boards broken. We don't need that anymore. Change-Id: I9d21fdf22c9a8e0e69488fc7896f2a81bf629201 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/675 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-01Rename vendor identifiers in KconfigPatrick Georgi
Board identifiers use them without underscore, too. Unify that. Change-Id: I146384ef6dbe601ad131dada8224f43e6c18433d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/674 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-29Fix x86 cpu_phys_address_sizeKyösti Mälkki
After CPUID, requested feature flag is in edx, not eax. Change-Id: I9ce27c22186f17cc64986be342d7d1ac78a79898 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/688 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-02-29tint requires more heap space for PDCurses.Marc Jones
tint was failing with the message "initscr(): Unable to create curscr." tint uses the initscr() to enable vga windows, which allocates more heap space with PDCurses than with tinycurses. Expanding the heap from 16KB to 64KB resolves the issue. Change-Id: I1d38651e2b77f55613969c29614fb3b2be38a00c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/687 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-29AMD southbridge: remove sp5100Kyösti Mälkki
Southbridge SP5100 support was compiled with SB700 code, but static device info structure would use sp5100/chip.h. To solve this drop support for separate chip sp5100 and adjust the relevant Kconfig options. Removes chip directory: src/southbridge/amd/sp5100/ Rename Kconfig option from: SOUTHBRIDGE_AMD_SP5100 to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100 Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/679 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-27asus/m4a785t-m: correct the CPU microcode patch selectionDenis 'GNUtoo' Carikli
Thanks to ruik on #coreboot Freenode IRC channel for explaining to me how to get the cpu revision: Feb 21 22:07:32 <ruik> ruik@ruik:~/coreboot$ cpuid | grep ^00000001 Feb 21 22:07:32 <ruik> 00000001 00020f32 00020800 00000001 178bfbff [..] Feb 21 22:07:44 <ruik> the 20f32 is mine CPUID The rest was just looking at the correspondance in src/cpu/amd/model_10xxx/update_microcode.c like Marc Jones explained(thanks Marc Jones) in the mailing list here: http://www.coreboot.org/pipermail/coreboot/2012-February/068332.html Change-Id: Ie0f004990e6b65456de009a4dcc306498bdb47e9 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/669 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-02-24Ati video: Apply un-written naming rulesKyösti Mälkki
Rename Kconfig to match directory name. Change-Id: Idebc203bbc9a02599dfc3e65be021aa9e1b23d61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/678 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-02-23Revert "Fix multipleVGA cards resource conflict on Windows"Marc Jones
This reverts commit 8660a1aa56caeb31bfaf15464285ca650638515e This commit has been found to cause problems with vbios and option rom init in seabios. It has been found by several people and requires more analysis before being recommitted. Change-Id: Ie5f54e417e7a0d8bd8ca4c0a573976afeaa9e230 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/671 Tested-by: build bot (Jenkins) Reviewed-by: Denis Carikli <GNUtoo@no-log.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-22ACPI: More ../../.. removalPatrick Georgi
CPP is ran with src/ as part of its search path, so using <northbridge/...> and the like is safe. Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/649 Tested-by: build bot (Jenkins)
2012-02-22amd/sb600: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/660 Tested-by: build bot (Jenkins)
2012-02-22Remove old AMD fam10 fixme commentMarc Jones
The family10 code had a very slow decompress before the cache settings were fixed. This has been fixed for some time. Remove all the old messages from the serial stream. Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/672 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-02-20libpayload: fix compile error with enabled USB_DEBUGMathias Krause
Commit c4348d0 ("libpayload: Remove bitfield use from OHCI data structures") missed to adapt a debug message. This patch fixes this. Change-Id: I5f6a4be9c7f6f99cb103926772717e15a3cbca70 Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Reviewed-on: http://review.coreboot.org/653 Tested-by: build bot (Jenkins) Reviewed-by: Bernhard Urban <lewurm@gmail.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-02-20Force SB600 bootblock to use I/O for PCI configDave Frodin
If PCI config cycles use MMIO instead of I/O in the SB600 bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O and configures the southbridge decode range to what is defined by the mainboards Kconfig. Change-Id: I85297237f32f37b3fc1ff5b488cca0a43bcf20fd Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/632 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20Force SB700 bootblock code to use I/O for PCI config cycles.Dave Frodin
If PCI config cycles use MMIO instead of I/O in the SB700 bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O and configures the southbridge decode range to what is specified by the mainboards Kconfig. Change-Id: I15a89a27645edf594d14ef20f129f75a315e9672 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/631 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20Force SB800 bootblock to use I/O for PCI configDave Frodin
If PCI config cycles use MMIO instead of I/O in the bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O. Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/630 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.Marc Jones
The MTRR check for WB TOM2 setting was only checking revF, not extended family revisions. All families above revf indicate 0xf in the family field and have additional bits in the extended family field. Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/627 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20Torpedo mainboard changes to fix warnings.Martin Roth
Fixes the warnings generated in the torpedo mainboard build. Most of these changes are similar to fixes already implemented in the persimmon mainboard. Change-Id: Ib931be51c0e6448c00c8cfeb13073e1f392582a5 Signed-off-by: Martin L Roth <martin@se-eng.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/634 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20Fixes Fam10/SR5650 cpu not recognized message.Dave Frodin
Extend the Family10 revisions checked byt the printk message. Change-Id: Ia94daeefb1aabfb128c577b1e0aa52cf63d5cf44 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20IEI-Kino Fam10 MPtable fix.Dave Frodin
Make changes to MPtable to match the ACPI tables. Change-Id: Icc18c9a25695d01d88d6ee5367064d527cc42bc1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/629 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20IEI Kino Fam10 ACPI table fixes.Dave Frodin
Fix the ACPI IRQ routing. Also, fix the SSDT generations and TOM2 fixup. Change-Id: Ica4a992d11bab63a510238dcd468b9fe80136def Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/628 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17nvidia/mcp55: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/659 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-02-17amd/sb700: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/661 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-02-17intel/i82801cx: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ifba0b65d81af60774f368d151e935ae1cc768336 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/662 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 00:44:04 +0000