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2013-07-10ARMv7: normalize ramstage code flowStefan Reinauer
In ram stage, all code flow should be tied to the resource allocator. Stuff that has to happen before everything else goes into the mainboard enable function in mainboard.c. This patch empties the main() wrapper around hardwaremain.c, allowing to get rid of this special case in the ARM port. Change-Id: Ide91a23f1043b64acf64471f180a2297f0f40d97 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3638 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10FUI: reorganize include filesRonald G. Minnich
We've got enough of a handle on this to realize some things: drm_dp_helper.h is by design device and architecture independent i915.h is common to most intel graphics chipsets going back several years i915_reg.h is as well Move these files to src/include/device, and adjust the .c files accordingly. Change-Id: I07512b3695fea0b22949074b467986420783d62a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3637 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Provide support for setting up the framebuffer from EDIDRonald G. Minnich
Add three functions to edid.c: void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr) takes an edid and uintptr_t, and fills in a static lb_framebuffer struct as well as setting the static vbe_valid to 1 unless some problem is found in the edid. The intent here is that this could be called from the native graphics setup code on both ARM and x86. int vbe_mode_info_valid(void) returns value of the static vbe_valid. void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) copies the static edid_fb to lb_framebuffer. There is now a common vbe.h in src/include, removed the two special ones. In general, graphics in coreboot is a mess, but graphics is always a mess. We don't have a clean way to try two different ways to turn on a device and use the one that works. One battle at a time. Overall, things are much better. The best part: this code would also work for ARM, which also uses EDID. Change-Id: Id23eb61498b331d44ab064b8fb4cb10f07cff7f3 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3636 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ChromeEC: Fix the default, depends for EC_GOOGLE_CHROMEEC_I2C.Gabe Black
The default for this variable should be n, it should only depend on EC_GOOGLE_CHROMEEC, and it should be (and is) explicitly enabled when needed. This prevents it from being turned on when the EC bus is SPI. Change-Id: Idc6651a764be4f055341a36b9b4a58990f050b0c Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3737 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Drop some duplicates of PCI-e config functionsKyösti Mälkki
These are not specific to Intel. Further work needs to be done to combine these with MMCONF_SUPPORT in arch/io.h. Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3502 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Fix MMCONF_SUPPORT_DEFAULT for ramstageKyösti Mälkki
Define at one place whether to use IO 0xcf8/0xcfc or MMIO via MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage. The implementation of pci_default_config() always returned with pci_cf8_conf1. This means any PCI configuration access that did not target bus 0 used PCI IO config operations, if PCI MMIO config was not explicitly requested. Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3606 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-10southbridge/intel/i82801gx: Make compilation possible with CONFIG_SMM_TSEGDenis 'GNUtoo' Carikli
Without that fix, and with CONFIG_SMM_TSEG, we have: src/southbridge/intel/i82801gx/smihandler.c: In function 'southbridge_smi_sleep': src/southbridge/intel/i82801gx/smihandler.c:340:3: error: implicit declaration of function 'smi_release_lock' [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors make: *** [build/southbridge/intel/i82801gx/smihandler.smm.o] Error 1 The fix is modelled after src/cpu/x86/smm/smihandler.c which ifdefs smi_release_lock(). Change-Id: Icdc6d039b34a1d95d0e607419bba2484d21abc5e Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3281 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10i82801gx: smihandle: sync with southbridge/intel/bd82x6x/smihandler.cDenis 'GNUtoo' Carikli
Change-Id: Ic725b169061bd426aa8206dc1d6d31e67cc639f2 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3304 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10southbridge: i82801gx: smihandler.c: Correct outl->outw mistake.Denis 'GNUtoo' Carikli
This mistake was spoted by comparison with the src/southbridge/intel/bd82x6x/smihandler.c file. Change-Id: I1516f0131d524bd7d001e6780e9a45402d1814d1 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3303 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10sandybridge: Add option to lock SPI regions on resumeNico Huber
Add an option to mark all SPI regions write protected on each S3 resume. We were used to lock the SPI interface in the payload which isn't run on the resume path. So we have to do it here. For the write protection to be effective, all write opcodes in the opmenu have to be marked correctly (as write operations) and the whole SPI interface has to be locked. Both is already done. Change-Id: I5c268ae8850642f5e82f18c28c71cf1ae248dbff Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3594 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-09fox_wtm2: First step support for coreboot-based graphics startupRonald G. Minnich
This code is the initial version of FUI for haswell and wtm2. The code is simplified from before in many ways. I've gotten rid of the opcode table, because it obscured meaning and I don't think it is needed any more. Register sets, mainly used for reset, are just lines of code -- not many of them. There are a bunch of not-yet-documented registers here; the VBIOS seemed to think they were necessary and testing shows they seem to be right. As a bit of added paranoia, we always include the VBIOS code as our emergency recovery path. You have to run it now anyways, so this is no regression from our current situation; and, if all goes well, in a week (or so), you'll never have to run it again, but like the Force and nose hair, it will be with you always. The code can return in three ways. The first, best way is success: panel is up and the VBIOS need not run. The second mode is that we tried to light up the panel but could not, for some reason, but will return with the panel partly up. In this case, it's ok not to power cycle the panel. The third, worst case, which will NEVER happen, ha ha, is that we have to turn the panel off and wait the required 600ms for it to cycle. Life sucks sometimes. This failure mode is in the 'hang on we're going to fix it' category now that we have ramstage in RW. The Big Goal here is to create something other coreboot ports can use as well. The guys doing the x60 report that the link FUI works, without too many mods, on that chipset, so it seems Intel is keeping things from changing too much over time. Also, again, please note: this and the next 3 versions will ALWAYS fail. The goal is to verify the correctness of the recovery path. The bizarre tab-space formatting in drm_dp_helper.h is from the original, as in i915_reg.h Change-Id: I6ecf454633029d185c29d470980b5a0f3114a8ce Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3635 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-09FOX_WTM2: First pass at FUI.Ronald G. Minnich
This lights up the display. We don't get graphics but we are missing the gttsetup at this point, so that is no shock. The real shock is that anything works at all. Change-Id: I03fc470334e96878aeb8465044b3cc9c90378735 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3634 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-08msrtool: Fix verbose ignored by cpuid().Benoît Legat
This is a trivial patch moving cpuid() call after reading argv so that verbose is set. Change-Id: Ic621191ef650495614a041413c1a0f707d4469e6 Signed-off-by: Benoît Legat <benoit.legat@gmail.com> Reviewed-on: http://review.coreboot.org/3627 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-08Fix Vortex86EX devicetree.cb indentation.Andrew Wu
Change-Id: If357b55b91618ee2438e6c6b2efb7018c56d26d0 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3628 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-08Revert "Radio and dock support in EC on X60 and X201"Peter Stuge
This reverts commit 7d1ebbff5ad224591a2d1972737611f96a13145c Change-Id: I4a9d0cd31a3df3d1e092193953f334697ca65167 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3616 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-06am335x: Implement support for the UART.Gabe Black
This patch was started by Dave Hendricks and implements the procedure for setting up the UART as described in the manual. Some unused code was removed. Change-Id: If26a424cac401ef3eafaec081147f41184fbcee9 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3490 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-07-05Add support for DMP Vortex86EX PCI mainboard.Andrew Wu
Change-Id: I8d42f765519e356d8f0cc6ed339d9b74f0a3e4d7 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3610 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04w83627hf/acpi: Fix offset of logical device activationNico Huber
The PnP's logical device activation normally resides at 0x30. This might have been overlooked as 0x29 looks very close to 0x30 in human eyes. Change-Id: Id5d5a92f2683ebe1808b943f686c062151d216da Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3592 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-04w83627hf/acpi: Fix type error in floppy drive enumeration codeChristoph Grenz
The enumeration method tried to evaluate an one-byte OperationRegion instead of a field in this OperationRegion, which resulted in an AE_TYPE error at runtime. Indexing the OperationRegion with a single field fixes this error. Change-Id: I15dd7aa6ecafb3a215d165d2b721003446815025 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3603 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04intel/i5000: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Change all PCI configuration accesses to MMIO on two boards with i5000 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: I26f1c2da5ae98aeeda78bdcae0fb1e8c711a3586 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3601 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04Move select MMCONF_SUPPORT under northbridge (fix)Kyösti Mälkki
I missed the board with gm45 when I moved MMCONF_SUPPORT lines. Also, the intel/i3100 does not have MMCONF_SUPPORT implemented even though it was previously selected for intel/eagleheights board. Change-Id: I9c7f6b0a150b4d54288a1e015277b9d98467fca4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3598 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04intel/i945: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Change all PCI configuration accesses to MMIO on all boards with i945 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3584 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-04intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Change all PCI configuration accesses to MMIO on all boards with SandyBridge and IvyBridge. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3576 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-03Move select MMCONF_SUPPORT under northbridgeKyösti Mälkki
Move/remove MMCONF_SUPPORT reference under mainboard Kconfig, as that feature originates from northbridge and cannot be disabled for a single mainboard. Change-Id: I6d6861079876ddddaff90b10f18edb6936e93bd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3589 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03Add support for DMP Vortex86EX PCI southbridge.Andrew Wu
Change-Id: Iad11cb1b22e9d1e2953b12221541b1478cad9665 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03winbond/w83627dhg: Fix logical device power down in ACPINico Huber
The W83627DHG has some power managements bits to power down individual logical devices. These are called `* Power Down`. Counterintuitively and in contrast to `Immediate Power Down` (bit to power down the whole chip), these bits are set when the respective logical device is powered. Unfortunately, our ACPI code set them wrong which led to disabled devices after a S3 suspend/resume. Adding an option how to set the PM bits and setting them to zero for the W83627DHG, corrects it. Tested with kontron/ktqm77. Change-Id: I8a472d480d4277721bd17c9f7c2ce44fa84e8ae2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3590 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03pnp: Add some default functions to enter/exit config stateNico Huber
Implement some common default functions to enter and exit the configuration state. Also provide default pnp_mode_ops for common enter()/exit() function pairs. The following cocci ensures their use: @ mode_match @ identifier enter, exit, ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = enter, .exit_conf_mode = exit, }; @ enter_match_8787 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } @ depends on enter_match_8787 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_8787, }; @ enter_match_55 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x55, dev->path.pnp.port); } @ depends on enter_match_55 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_55, }; @ depends on enter_match_8787 || enter_match_55 @ identifier mode_match.enter; @@ -enter(...) {...} @ exit_match_aa @ identifier mode_match.exit, dev; @@ exit(...) { outb(0xaa, dev->path.pnp.port); } @ depends on exit_match_aa @ identifier mode_match.exit, mode_match.ops; @@ struct pnp_mode_ops ops = { - .exit_conf_mode = exit, + .exit_conf_mode = pnp_exit_conf_mode_aa, }; @ depends on exit_match_aa @ identifier mode_match.exit; @@ -exit(...) {...} @ depends on enter_match_8787 || enter_match_55 || exit_match_aa @ @@ #include <device/pnp.h> +#include <superio/conf_mode.h> @ mode_match_55_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_55, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_55_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_55_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; @ mode_match_8787_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_8787, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_8787_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_8787_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3484 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-02Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c`Paul Menzel
Use the same indentation, comment placement and spelling of words. Run `indent -linux …`. Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3220 Reviewed-by: Nico Huber <nico.huber@secunet.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-02Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900Dave Frodin
The MAX_PIRQ_LINKS is defined in src/Kconfig with a default value of 4. The src/northbridge/via/vx900/Kconfig also defines MAX_PIRQ_LINKS with a default of 8 and it ends up giving us a value of 8 for non-VIA platforms. Change-Id: Iee1938d38a93ab7c35c8cb6fe9656a92cf3fa21e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3586 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-01w83627hf: Add comments about parallel port modes in superio.aslChristoph Grenz
Add comments in PAR0._PRS explaining which dependent resource descriptor puts the parallel port into EPP or SPP mode. Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3495 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-01cbmem: Fix makefileStefan Tauner
The .dependencies rule did not use the CPPFLAGS variable which led to funny behavior: a spurious termination message the first time (after checkout/make distclean) one executes make. Afterwards the (wrongly) empty .dependencies file hides the problem and the binary is created anyway. $ make cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory compilation terminated. cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem $ make make: Nothing to be done for `all'. $ make clean rm -f cbmem *.o *~ $ make cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem $ make distclean rm -f cbmem *.o *~ rm -f .dependencies $ make cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory compilation terminated. cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem I fixed that by adding the CPPFLAGS variable to the .dependencies recipe, just like Stefan Reinauer did in Chromium (Ia9d2e10a3ef122f30d681d16c2291eb108ead835), hence the split sign-off for this tiny change. :) Change-Id: Icd11b146ad762cbdf9774630b950f70e1253a072 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3548 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-01beaglebone: Enable the clocks and pins for the configured UART.Gabe Black
Set up the pinmux to enable the pins and the clocks for whichever UART is currently configured. Change-Id: Iac13f16d9d84320555b99734ea83eafd0a2803fe Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3573 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-01am335x: Fix the address of the pinmux registers.Gabe Black
The pinmux register data structure describes a subset of the control module registers, but the address which pointed to the base of the pinmux registers was actually being set to the beginning of all the control module registers, not just those having to do with the pinmux. With this address fixed, the UART now works on the beaglebone black. Change-Id: I7c99b6f37d7da359af074127cd0c1a86fda2d9a0 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3574 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-01usbdebug: Support i82801dx/ex southbridgeKyösti Mälkki
Tested on i82801dx system with board aopen/dxplplusu. Change-Id: I522455ac79c87b9b6fc9cd8c4dc0da3563dfbfad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3381 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-01usbdebug: Unify Intel southbridge buildsKyösti Mälkki
EHCI controller enable is identical on the affected chipsets. Change-Id: I91830b6f5144a70b158ec1ee40e9cba5fab3fbc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3424 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-07-01usbdebug: Drop duplicates of EHCI BAR relocation codeKyösti Mälkki
All the additional work that needs to be done in EHCI BAR relocation is independent of the hardware platform and was functionally identical in all the copies removed. When USBDEBUG is not selected, PCI EHCI controllers use standard pci_dev_read_resources() call. With USBDEBUG selected, PCI EHCI controller's device_operations .read_resources is replaced with pci_ehci_read_resources() call, which in turn will replace the device_operations .set_resources call. The replacement for .set_resources reconfigures usbdebug driver side, and calls the original .set_resources to configure hardware side. Change-Id: I8e136a5da4efedf60b6dd7068c0488153efaaf8e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3412 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-29AMD S3 resume: Add framwork to write bigger dataSiyuan Wang
This patch is based on 'AMD S3: Program the flash in a bigger data packet'[1] Some AMD south bridge can write bigger data when saving S3 info. In this patch, I use config 'AMD_SB_SPI_TX_LEN' to contral data size. AMD_SB_SPI_TX_LEN is defined in 'src/southbridge/amd/Kconfig' and then can be overridden in the Kconfig for specific southbridges that support larger size. I have tested on AMD Parmer and Thatcher. We will release a new board whose south bridge can transfer more than 4 bytes each time. [1] http://review.coreboot.org/#/c/2306/ Change-Id: Id984955d46eae487e39d45979f1a90054aa9f54b Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3413 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-28ELOG: Fix warning to fix the compilation.Denis 'GNUtoo' Carikli
Without that fix we have: src/drivers/elog/elog.c: In function 'elog_is_header_valid': src/drivers/elog/elog.c:213:3: error: format '%u' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format] Change-Id: I71b80a94c03a04eedb688ae107d92c05a878315e Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3551 Reviewed-by: Nico Huber <nico.huber@secunet.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-28libpayload: Add strerrorStefan Tauner
Change-Id: I33d45ad7d09473b8c6f5b7ee5fbadc0d184f9dcd Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3537 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-06-28Drop WARNINGS_ARE_ERRORS exceptionsStefan Reinauer
Thanks to Bruce's great work, we can finally drop this workaround. Change-Id: Ie92d1e53ef867fa34aa2489ccfb682d73195b213 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3569 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-28Supermicro H8SCM/H8QGI: Increase size of bus variable to meet APIBruce Griffith
Users of mptable_write_buses() pass two pass-by-reference parameters reflecting a maximum bus number and a search bus number. These bus numbers are expected to be held in "int" variables and are updated by the function. Both of the Supermicro boards define the search bus number as a byte value in mptable.c. For now, change the two Supermicro boards to use "int" to hold the search bus index. Change-Id: Ie71850719c1fa3cda0ac9c8773bb80650de95c70 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3546 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28AMD Dinar: Eliminate warnings (initializers/prototypes/unused var)Bruce Griffith
Fix a bunch of compiler-generated warning messages. These fixes are mainly braces for grouping initializers. These changes are not intended to change any code functionality. There are two changes where function prototypes are added, and two cases where unused variables are eliminated. Change-Id: I93cef8899170b5575e7fb7c55181b381a7bcd9d8 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3545 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28AMD SB700 boards: Set Azalia configuration flagsBruce Griffith
The existing code for setting Azalia configuration assumes that the configuration bits are contiguous within a single byte and can be set using a byte copy addressed into the lowest 2-bit subfield. The fix in Family 14 defines a union that can be addressed as a byte to overlay the bit fields. Since the offset of the four subfields is not necessarily fixed, change the code to initialize each of the four subfields individually. Change-Id: I1dff20bb8bd3e1bcd8b4e6b0537e20779d2a3521 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3544 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28supermicro/h8scm: Add a type cast for printk to correct a warning messageBruce Griffith
Copy a type cast from the other cases of the same switch statement to eliminate compiler warning messages. Change-Id: I8d0a88892f6a5f8e43227ab5f830041894b07f6a Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3543 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28Dinar, H8SCM, H8QGI: Add prototype of get_bus_conf()Bruce Griffith
On Dinar, H8SCM, and H8QGI, add <cpu/amd/amdfam15.h> as an include to pick up the prototype definition of get_bus_conf(). Change-Id: Ie4887670ac52aa194745881362df19cd1d75773e Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3542 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28amd/cimx/sb700/late.c: Add type cast to (UINT8)Bruce Griffith
This change inserts a type cast to eliminate a compiler warning. Change-Id: If223f61f1565caeadb1b7e0762975b1b2412eda5 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3541 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28amd/cimx/rd890/amd.h: Eliminate redefinition of NULLBruce Griffith
This change replaces a redefinition of NULL with the standard definition from <stddef.h> to eliminate a compiler redefinition warning. Change-Id: I441fa569f545c0efb00284b5ee58aa27cb6617ba Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3540 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28amd/agesa/family15/northbridge.c: Delete unused variableBruce Griffith
This change eliminates an unused variable that causes a build warning. Change-Id: I02487c7dd80d458f562d7afe1827eefcc0fb678b Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3526 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28Add support to enable/disable builtin GbE (again)Stefan Reinauer
This requires a new system agent binary (v6 / v11 on haswell). Note that the existing system agent binaries are long time obsolete and won't work with current coreboot, so this update is overdue. Change-Id: I48d8649576ca84d2b85ab082ce06f3462e189059 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3568 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-28amd/agesa/f15/Lib/amdlib.c: Add missing breaks to switch statementBruce Griffith
Static analysis often flags case statements that do not include a terminating "break;" statement. Eclipse's CODAN is an example of this. This changelist modifies amdlib.c to terminate case statements with "break;". Change-Id: I3d43acaf64e2e2d9717421cb547fec35e582cf8b Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3539 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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