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2016-01-22util/crossgcc: Don't build gnattoolsNico Huber
I thought we'd be using gnatmake but it's deprecated. Who needs it anyway? Change-Id: Ic08add72e771fa346c8a736ea901863ea5737d91 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13041 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-22lib: Implement framework for retrieving WiFi regulatory domainFelix Durairaj
Platforms that need to initialize WRDD package with the regulatory domain information should implement function wifi_regulatory_domain. A weak implementation is provided here. Original-Reviewed-on: https://chromium-review.googlesource.com/314384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I84e2acd748856437b40bbf997bf23f158c711712 Signed-off-by: fdurairx <felixx.durairaj@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12744 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22soc/braswell: Add method for Wifi regulatory domainFelix Durairaj
Get the WRDD domain code from VPD and put it in global nvs. WRDD method in wifi.asl returns this value from global nvs. This wifi.asl should be included in dsdt.asl under the root port where wifi module resides. Original-Reviewed-on: https://chromium-review.googlesource.com/314373 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Change-Id: I809d28f10e80681471a785e604df102fb943a983 Signed-off-by: fdurairx <felixx.durairaj@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22intel/strago: Set POWER_SOURCE_CONFIG in devicetree.cbKane Chen
SVID config set to SVID_PMIC_CONFIG BUG=none BRANCH=none TEST=build, boot to OS and check the register is set properly Change-Id: If63b8112d4da0347c3a2c4c6d82b12a1f618291c Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308576 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13117 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/cyan: Add Wifi regulatory methodHannah Williams
WRDD method in wifi.asl returns the regulatory domain code. This value is read from VPD in wifi_regulatory_domain() and saved to global nvs if CONFIG_HAVE_REGULATORY_DOMAIN is enabled. It returns default code if CONFIG_HAVE_REGULATORY_DOMAIN is not enabled. Change-Id: I6e96bdf0fe93ae30a3afdcb63a0f89ce21023704 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13055 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22lib/Makefile.inc: Link hexdump.c in the bootblock as wellAlexandru Gagniuc
Change-Id: Id58f252e238cc3eb3fe9632493642d2a37c2a772 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/12873 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-22intel/strago: Add method for Wifi regulatory domainHannah Williams
WRDD method in wifi.asl returns the regulatory domain code. This value is read from VPD in wifi_regulatory_domain() and saved to global nvs if CONFIG_HAVE_REGULATORY_DOMAIN is enabled. It returns default code if CONFIG_HAVE_REGULATORY_DOMAIN is not enabled. Original-Reviewed-on: https://chromium-review.googlesource.com/315131 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I52e0a052d31f36c6dc04e6a0953456350e7d86c3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22lib/hexdump: Refactor to skip lines with all ones as wellAlexandru Gagniuc
We already do this for lines with all zeroes, so it makes sense to treat all ones the same, for symmetry. Change-Id: I4b637b07a49e0c649331aa200995b474dd9a2682 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/12872 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-22src/Kconfig: Indent with tabs instead of spacesMartin Roth
Change-Id: I47776d842b8d684fc11ac448b751892ee2bc5ecc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13116 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-22skylake mainboards: Enable CONFIG_VBOOT_EC_SLOW_UPDATEDuncan Laurie
Updating EC+PD takes long enough to update that it is good to show the "critical update" screen when doing an EC/PD update. BUG=chrome-os-partner:49650 BRANCH=glados TEST=Build and boot on chell in normal mode with an EC update payload and ensure that it reboots to enable graphics, shows the "critical update" screen, and then reboots to disable graphics init again. Change-Id: I436b96b95595b68273e594bdcfe2db0789ee26b2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 08e45decd066f8f57ad103ff8b76cb7a916afa9e Original-Change-Id: Ie250f4531437e4a0ce14b5aeb0fe564e9461fe4d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13075 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22intel/fsp1_1: Fix for passing VBT when vboot requests itDuncan Laurie
In order to support vboot requesting graphics support in normal mode the VBT needs to be passed to FSP when it is requested outside of the usual developer/recovery path. To make this integrate cleaner use the generic bootmode provided display_init_required() function instead. Also have it print a message indicating when it does not pass VBT to GOP so it is easier to see what happened in the console logs. BUG=chrome-os-partner:49560 BRANCH=glados TEST=Enable EC_SLOW_UPDATE on chell and test that when vboot requests graphics support in normal mode FSP will get passed VBT and bring up the panel. Change-Id: I07bc54d37d687134b21baa60b5c278b5041241cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 41efd322951b8f3a8a687944832bfd89fd3014ca Original-Change-Id: I1b68760eabbf3af1d962cb2a3199e504a7852042 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322782 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22vboot2: Handle slow EC SW sync and graphics driver loadingDuncan Laurie
Add flag handling for CONFIG_VBOOT_EC_SLOW_UPDATE to indicate to vboot that it should show the "critical update" screen during software sync for EC+PD. In order to make this work on x86 where we do not run graphics init in the normal path add handling for CONFIG_VBOOT_OPROM_MATTERS and indicate to vboot when the option rom has been loaded. BUG=chrome-os-partner:49560 BRANCH=glados TEST=Build and boot on chell in normal mode with an EC update payload and ensure that it reboots to enable graphics, shows the "critical update" screen, and then reboots to disable graphics init again. Change-Id: I5ca46457798a22e9b08aa2febfec05b01aa788f9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6a1bb8572c3485f64b9f3e759288321b44184e66 Original-Change-Id: I9f66caaac57bb9f05bc6c405814469ef7ddf4d0a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322781 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13073 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22intel/skylake: Fix klockwork violationNaresh G Solanki
File: src/soc/intel/skylake/flash_controller.c Line: 192 Variable 'ret' might be used uninitialized in this function. Hence initializing it with initial value of zero. BRANCH=None BUG=chrome-os-partner:48542 TEST=Built & booted Kunimitsu board. Change-Id: I4e63612890057a2180f38b2e74419d98b02b70c1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b93ca876912d2336dae25b9b84e56ffb171b215b Original-Change-Id: Ied8c909f5294d56daddb2806111d477246f98957 Original-Reviewed-on: https://chromium-review.googlesource.com/322082 Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13072 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22intel/skylake: PL2 override changespchandri
Override the default PL2 values with ones recommended by Intel. BUG=chrome-os-partner:49292 BRANCH=glados TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W MMIO 0x59A0[15] to find PL1 enable/disable = Disable MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W Here PL2 is set to 25W and PL1 is disabled. CQ-DEPEND=CL:321392 Change-Id: I338b1d4879ae1b5f760e3c1d16e379a2baa1c965 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa6a115227385bef44abfacf58af306c16ed478a Original-Change-Id: I3bfc50256c9bdd522c984b11faf2903d7c44c81f Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/322454 Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/13071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22intel/skylake: Thermal Design Power PL1 and PL2 Config Changespchandri
Override the default PL2 values with one recommended by Intel. Disable PL1 configuration via MMIO register. BUG=chrome-os-partner:49292 BRANCH=glados TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W MMIO 0x59A0[15] to find PL1 enable/disable = Disable MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W Here PL2 is set to 25W and PL1 is disabled. Change-Id: I10742f91cc7179de1482d42392338976e8082afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1b7771ccb34bdff92ffa9870733bd641e4644cdf Original-Change-Id: Iefa93912008c71b41f2b20465e8acfd42bb6c731 Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321392 Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/13070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/veyron_*: Add dual-rank 2GB Hynix module to SDRAM configsDavid Hendricks
This is a follow-up to CL:320623 to make veyron DRAM configs uniform (except for Rialto). As discussed in chrome-os-partner:43626, the mr[3] value and ODT are set diffently for Mickey, thus the .inc files for other boards have mr[3] = 1 and ODT disabled. BUG=none BRANCH=veyron TEST=compile tested for veyron Change-Id: I61798cfef779b0a3a510fd354ab53ffc63ca6c95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3b7cea6331bcec8aba09a204060e093d3dd732cb Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Iacf821645a2dcceaed1c1c42e3e1b1c312b31eab Original-Reviewed-on: https://chromium-review.googlesource.com/321870 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13109 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-01-22cbfstool: Add attributes for position and alignment constraints.Werner Zeh
Add functionality to cbfstool to generate file attributes for position and alignment constraints. This new feature can be activated with the -g option and will generate, once the option has been enabled, additional attributes for the files where position, xip or alignment was specified. Change-Id: I3db9bd2c20d26b168bc7f320362ed41be349ae3a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/12967 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-01-21vboot: Install files into FW_MAIN_A and FW_MAIN_B unless they're for ROPatrick Georgi
Setup an initial rule to make use of the updatable CBFS regions in fmap. Change-Id: I1fe1c6e7574854b735760c85590da6e297f6e687 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13060 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21chromeos: import Chrome OS fmapsPatrick Georgi
These are generated from depthcharge's board/*/fmap.dts using the dts-to-fmd.sh script. One special case is google/veyron's chromeos.fmd, which is used for a larger set of boards - no problem since the converted fmd was the same for all of them. Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT region ends up at the beginning of flash). This becomes necessary because we're working without a real cbfs master header (exists for transition only), which carved out the space for the offset. Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21build system: allow assigning files to regionsPatrick Georgi
Using the regions-for-file function, the build system can now declare which (CBFS formatted) fmap region(s) a file should end up in. The default is to put them in the regular COREBOOT region, but more complex boot schemes (eg. vboot or fallback/normal) can use the function to implement suitable policies. Change-Id: I5e2e6b8e8759fda2cfb0144d5b998ba3e05650c8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13039 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-01-21cbfstool: don't rewrite param.baseaddress in cbfs_addPatrick Georgi
cbfs_add calculated a base address out of the alignment specification and stored it in param.baseaddress. This worked when every cbfstool invocation only added a single file, but with -r REGION1,REGION2,... multiple additions can happen. In that case, the second (and later) additions would have both alignment and baseaddress set, which isn't allowed, aborting the process. Change-Id: I8c5a512dbe3c97e08c5bcd92b5541b58f65c63b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21Kconfig: add comments for toolchain choicesMartin Roth
- While we're working on fixing clang for coreboot, mark it as not currently working so that it doesn't look like a reasonable choice. - Add help on how to make the toolchains Change-Id: Ib37093ca98d0328fad40dd7886c98d00f78bd58e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13053 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21Chromeos: Implement wifi_regulatory_domain using "regions" key in VPDFelix Durairaj
Implement wifi_regulatory_domain function by getting country code from VPD Original-Reviewed-on: https://chromium-review.googlesource.com/314385 Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ia6a24df110a3860d404d345571007ae8965e9564 Signed-off-by: fdurairx <felixx.durairaj@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12743 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21Makefile.inc: allow coreboot to be a git submoduleBen Gardner
When coreboot is pulled in as a submodule, the .git "folder" is a file, not a folder. Use the '-e' test instead of '-d' to allow for that. Without this change, build.h will contain: #define COREBOOT_VERSION "coreboot-unknown" Change-Id: Ia141371cc892a0817d3566dc37ed0401675ad8d8 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/13061 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-01-21build system: Initialize all CBFS regionsPatrick Georgi
Regions marked "(CBFS)" in the fmd weren't actually initialized with a CBFS structure, just the default CBFS region (COREBOOT). This made cbfstool add (etc) fail on those regions, so explicitly initialize all those regions. Change-Id: Ib321fa73cd2ecc8057b52408521fd214d6df7f2e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13059 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21fmaptool: emit list of CBFS regions on requestPatrick Georgi
The CBFS flag in fmd files isn't stored in the fmap, so allow storing it out of band using the -R option. Change-Id: I342772878d7f8ce350de1a32dc7b2a5b07d6617d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13058 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21util/lint: Fix linter for old license headersMartin Roth
Somehow I lost a $ on headerlist between when I tested the script and when I submitted it, turning headerlist into plain text instead of a variable name. This makes the test always pass. - Fix variable bug. - exclude this script from the check. - update test for empty HEADER_DIRS variable. Change-Id: I6080c520bc741e9d689f7c66ee97879afc8ba38c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13057 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-21intel/skylake: remove third paragraph of license headerMartin Roth
We had another one that crept in while the linter was broken. Change-Id: Ie690e2d7fc7ad31b3b674de1618723bb100ac961 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13056 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-21memlayout: Fix unified CBFS_CACHE macroJulius Werner
commit a8aef3ac (cbfs_spi: Initialize spi_flash when initializing cbfs_cache) introduced a bug that makes the rarely-used unified CBFS_CACHE() memlayout macro break when used in conjunction with cbfs_spi.c (since that macro does not define a separate postram_cbfs_cache region). This patch fixes the problem by making all three region names always available for both the unified and split macros in every stage (and adds code to ensure we don't reinitialize the same buffer again in romstage, which might be a bad idea if previous mappings are still in use). BRANCH=None BUG=None TEST=Compiled for both kinds of macros, manually checked symbols in disassembled stages. Change-Id: I114933e93080c8eceab04bfdba3aabf0f75f8ef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f270f88e54b42afb8b5057b0773644c4ef357ef Original-Change-Id: If172d9fa3d1fe587aa449bd4de7b5ca87d0f4915 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/318834 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21google/veyron_mickey: Update Hynix memory configurationLang Zhang
Update Hynix memory configuration for mickey so that it can boot on Hynix board. BUG=chrome-os-partner:48637 BRANCH=master TEST=Boot on mickey hynix board Change-Id: Ibbf90cf76793005e23a720b97540b268ebf0864d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 071167b667685c26106641e6899984c7bd91e84b Original-Change-Id: Id63d74cac36b9fd84bdb88969291982e14fa7d01 Original-Signed-off-by: Lang Zhang <kingsley_zhang@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320623 Original-Commit-Ready: lang zhang <kingsley_zhang@asus.com> Original-Tested-by: lang zhang <kingsley_zhang@asus.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/13048 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21arch/x86: Add files needed for C environment bootblock on x86Alexandru Gagniuc
This provides symbols needed by CBFS and FMAP APIs, and allows running run_romstage() in an x86 bootblock. Note that console-related files are not added in this patch, as they are not essential for the functinality on an x86 environment bootbock. Change-Id: I36558b672a926ab22bc9018cd51aee32213792c2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/12880 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-21*/Makefile.inc: Compile files needed by uart8250 in x86 bootblockAlexandru Gagniuc
These files provide symbols needed by console and uart drivers. This was not an issue in the past, as we were not setting up a C environment this early in the boot process. Change-Id: Ied5106ac30a68971c8330e8f8270ab060994a89d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/12869 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-21console: Simplify bootblock console Kconfig selection logicAlexandru Gagniuc
Instead of depending BOOTBLOCK_CONSOLE on a set of architectures, allow the arch or platform to specify whether it can provide a C environment. This simplifies the selection logic. Change-Id: Ia3e41796d9aea197cee0a073acce63761823c3aa Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/12871 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-21arch/x86/include: Rename bootblock_common to bootblock_romcc.hAlexandru Gagniuc
This header is only used for the bootblock compiled with ROMCC. As the follow-on patches introduce a bootblock which does not make use of ROMCC, rename this header to prevent confusion. Change-Id: Id29c5bc6928c11cc7cb922fcfac71e5a3dcd113c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/12867 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-21google/tidus: initial upstream migrationMatt DeVillier
Migrate google/tidus (Lenovo ThinkCentre Chromebox) from Chromium tree to upstream, using google/guado as a baseline. TEST=built and booted tidus with full functionality Change-Id: I9d7a976345566bee63226d1a44ba7d5ec137a742 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12801 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21ec: Add support for EC used on Purism Librem laptopsDuncan Laurie
This adds basic ACPI support for the EC used on Purism Librem laptops. The EC firmware appears to use the topstar laptop interface that has support in the linux kernel for handling the special keys. Supported functions: - Battery information - AC presence - Lid switch - Special keys (after loading topstar-laptop driver in linux) - EC events for turbo enable/disable when on AC power Things it does not do: - EC SMI handling - Fan is left under EC control This was developed and tested on a Librem 13 laptop, and has not been directly tested on an Librem 15. Change-Id: Ib85a24e4cc8ab09b14147060043cff372863c2d1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/13025 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21drivers/intel/wifi: Only compile if SMBIOS tables are generatedDuncan Laurie
This driver adds an SMBIOS table for Intel WiFi, but if SMBIOS table generation is disabled then it should not attempt to compile or it will fail to find the "get_smbios_data" member of the device_operations structure. Tested by compiling and booting on purism/librem13 with SMBIOS table generation disabled. Change-Id: Iac6c265da7daae1be4d7585dab7b54561ff4e631 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/13046 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-21broadwell: gpio.asl: Make GWAK method serializedDuncan Laurie
This method creates named objects and must be serialized to prevent a warning from IASL. Tested by compiling purism/librem13 which includes this ASL. Change-Id: Ic043ea479e681d2180421fcf8e0583b62e6fcd71 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/13045 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-20lib: compile mdelay for bootblockPatrick Georgi
Mediatek's bootblock needs mdelay, which depends on a udelay implementation. Compiling the file for bootblock poses no harm: Either udelay exists (in which case mdelay is usable) or it doesn't in which case we see exactly the same kind of build time error (just with udelay instead of mdelay). Change-Id: I7037308d2d79c5cb1b05bb2b57a0912ad11cd7a6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13049 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-20sb/intel/i82801gx: Clean up sata.cDamien Zammit
This tidies up the setting of the PCS register. An assumption is made that bit 4 of this register is read-only, which according to the ICH7 datasheet, it is. Change-Id: Ia9b7d38a87e26236f6ebc951c169cae12b13139f Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13015 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-01-20Kconfig: Remove selects that enable 'choice' symbolsMartin Roth
Selecting Kconfig symbols that were created inside a 'choice' block have no effect. Remove these so people aren't confused by them. Change-Id: I7de9131d8d8afb65f86648afb9728f09cb67e122 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12970 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-20nb/intel/pineview: Use macro names for memory base registersDamien Zammit
Change-Id: I0b79ddcf9248c6a6964dd60e30a6ea18e27bc186 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13032 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-20cbfstool: Add header file for ntohl & htonl on Applezbao
On Apple OS X, the ntohl and htonl need including header, #include <arpa/inet.h> Please refer the manpage for these command on OS X, https://developer.apple.com/library/mac/documentation/Darwin/Reference/ManPages/man3/htonl.3.html Change-Id: Ia942c58f34637c18222fbf985b93c48abf63c5b8 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/11672 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-20cpu: Fix typo that spelled "allocate" as "allocte."Jacob Laska
The error informing the user that the CPU device cannot be allocated has a typo incorrectly spelling "allocate" as "allocte". TEST=Compiled Change-Id: I2a6bad56133e375e2fd6a670593791414bf0dc2c Signed-off-by: Jacob Laska <jlaska91@gmail.com> Reviewed-on: https://review.coreboot.org/13030 Tested-by: build bot (Jenkins) Reviewed-by: Ben Frisch <bfrisch@xes-inc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-19lenovo/t400: Revise onboard IRQ routingNico Huber
All southbridge interrupt pin and routing registers (D*IP and D*IR) are left at their default values (see ICH9 datasheet) and this file just has to reflect them. Change-Id: I1e9732e178bb8422b284d80d9f3d34b72f2e2415 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13040 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19cbfstool: accept read-only files when possibleVadim Bendebury
cbfstool tries opening the input file for write access even if the command does not require modifying the file. Let's not request write access unless it is necessary, this way one can examine write protected files without sudo. BRANCH=none BUG=none TEST=running cbfstool /build/<board>/firmware/image.bin print in chroot does not require root access any more. Change-Id: Ic4e4cc389b160da190e44a676808f5c4e6625567 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ef6a8e25d9e257d7de4cc6b94e510234fe20a56d Original-Change-Id: I871f32f0662221ffbdb13bf0482cb285ec184d07 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317300 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12931 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19arch/x86/Makefile.inc: Add a comment to fix syntax highlightingMartin Roth
Trivial fix for syntax highlighting in editors. Some get confused by the double quote that doesn't have a close quote and stop highlighting at that point. This comment closes the quote and the paren pair so that they can recover. Change-Id: I2bdb7c953a86905fc302d77eb9ad1200958800b7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19Braswell: add code to support customization of I2C data hold timeKane Chen
The I2C data hold time can be vary on different boards/devices. So, it needs to be customized by boards/devices TEST=compile ok and check IC_SDA_HOLD is changed if the hold time is defined in onboard.h Original-Reviewed-on: https://chromium-review.googlesource.com/308623 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I66c799de400670916cebbcb529d4f59d5b0f081b Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/12740 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19intel/skylake: Fix issues found by klockworkNaresh G Solanki
src/soc/intel/skylake/acpi.c Function cbmem_find may return NULL, check before using its result. src/soc/intel/skylake/flash_controller.c Remove dead code: spi_claim_bus is a no-op, always returning 0. src/soc/intel/skylake/gpio.c Check for NULL before using pointers. src/soc/intel/skylake/igd.c Don't copy 0-termination of signature string. src/soc/intel/skylake/lpc.c Don't check unsigned >= 0. src/soc/intel/skylake/systemagent.c Explicitly cast result to 64bit. BRANCH=None BUG=chrome-os-partner:48542 TEST=Built & booted Kunimitsu board. Change-Id: I6cbf4f78382383d3c8c3b15f66c5898ab5bf183a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d98a8cdd3d095a6943c0e104cd4938639a62bd14 Original-Change-Id: Id2a31402618f4c9f6f53525ebcf6b71fd67428db Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317522 Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12991 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-19intel/kunimitsu: Add device properties for Nuvoton codecYong Zhi
This patch added default values for two SAR properies introduced by updated nau8825 codec driver. Also updated sar-threshold to improve button detection accuracy. Bug=chrome-os-partner:49394 BRANCH=glados TEST=Build for kunimitsu. Tested with 4-button headset Change-Id: I4096c60be54819d0ab2bf4b72a1e403f88d96af0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b747e9dffed1c51131f0028879d4c22283c8ec5 Original-Change-Id: I3e222ff58c1483e261acf1cea297164966bf8689 Original-Signed-off-by: Yong Zhi <yong.zhi@intel.com> Original-Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/322241 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13014 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 06:10:15 +0000